BCR08AS-12 Triac Low Power Use REJ03G0292-0200 Rev.2.00 Mar 22, 2007 Features • • • • • Non-Insulated Type • Planar Passivation Type • Completed Pb Free IT (RMS) : 0.8 A VDRM : 600 V IFGTI, IRGTI, IRGT : 5 mA IFGT : 10 mA Outline RENESAS Package code: PLZZ0004CA-A (Package name: UPAK) 1 2 RENESAS Package code: PLZZ0004CB-A LZ ZZ0004 (Package name: SOT-89)) 2, 4 3 4 1 2 4 3 3 1. 2. 3. 4. 1 T1 Terminal T2 Terminal Gate Terminal T2 Terminal Applications Hybrid IC, solid state relay, electric fan, washing machine, and other general purpose control applications Maximum Ratings Parameter Symbol Voltage class 12 (Mark BF) Unit VDRM VDSM 600 720 V V Repetitive peak off-state voltageNote1 Non-repetitive peak off-state voltageNote1 Parameter RMS on-state current Symbol IT (RMS) Ratings 0.8 Unit A Surge on-state current ITSM 8 A I2 t 0.26 A2s PGM PG (AV) VGM IGM Tj Tstg 1 0.1 10 1 – 40 to +125 – 40 to +125 W W V A °C °C — 50 mg I2t for fusing Peak gate power dissipation Average gate power dissipation Peak gate voltage Peak gate current Junction temperature Storage temperature Mass Notes: 1. Gate open. REJ03G0292-0200 Rev.2.00 Mar 22, 2007 Page 1 of 7 Conditions Commercial frequency, sine full wave Note3 360° conduction, Ta = 40°C 60Hz sinewave 1 full cycle, peak value, non-repetitive Value corresponding to 1 cycle of half wave 60Hz, surge on-state current Typical value BCR08AS-12 Electrical Characteristics Parameter Repetitive peak off-state current On-state voltage Gate trigger voltageNote2 Gate trigger currentNote2 Gate non-trigger voltage Thermal resistance Critical-rate of rise of off-state Note4 commutating voltage Ι ΙΙ ΙΙΙ ΙV Ι ΙΙ ΙΙΙ ΙV Symbol IDRM VTM Min. — — Typ. — — Max. 2.0 2.0 Unit mA V Test conditions Tj = 125°C, VDRM applied VFGTΙ VRGTΙ VRGTΙΙΙ VFGTΙΙΙ IFGTΙ IRGTΙ IRGTΙΙΙ IFGTΙΙΙ VGD Rth (j-a) — — — — — — — — 0.1 — — — — — — — — — — — 2.0 2.0 2.0 2.0 5 5 5 10 — 65 V V V V mA mA mA mA V °C/W Tj = 25°C, VD = 6 V, RL = 6 Ω, RG = 330 Ω Tj = 125°C, VD = 1/2 VDRM Junction to ambientNote3 (dv/dt)c 0.5 — — V/µs Tj = 125°C Tc = 25°C, ITM = 1.2 A, Instantaneous measurement Tj = 25°C, VD = 6 V, RL = 6 Ω, RG = 330 Ω Notes: 2. Measurement using the gate trigger characteristics measurement circuit. 3. Soldering with ceramic plate (25 mm × 25 mm × t0.7 mm). 4. Test conditions of the critical-rate of rise of off-state commutating voltage is shown in the table below. Test conditions 1. Junction temperature Tj = 125°C 2. Rate of decay of on-state commutating current (di/dt)c = – 0.4 A/ms 3. Peak off-state voltage VD = 400 V REJ03G0292-0200 Rev.2.00 Mar 22, 2007 Page 2 of 7 Commutating voltage and current waveforms (inductive load) Supply Voltage Time Main Current (di/dt)c Time Main Voltage (dv/dt)c Time VD BCR08AS-12 Performance Curves 101 7 5 4 3 2 102 7 5 3 2 101 7 5 3 2 100 7 5 3 2 Surge On-State Current (A) Tj = 125°C Tj = 25°C 0 1 2 3 4 Gate Trigger Voltage (Tj = t°C) × 100 (%) Gate Trigger Voltage (Tj = 25°C) 102 7 5 4 3 2 6 4 2 2 3 4 5 7 101 2 3 4 5 7 102 On-State Voltage (V) Conduction Time (Cycles at 60Hz) Gate Characteristics Gate Trigger Current vs. Junction Temperature VGM = 10V PGM = 1W PG(AV) = 0.1W VGT IFGT I, IRGT I, IRGT III IGM = 1A IFGT III VGD = 0.2V 10–1 100 2 3 5 7 101 2 3 5 7 102 2 3 5 7 103 103 7 5 4 3 2 8 0 100 5 Gate Trigger Current (Tj = t°C) × 100 (%) Gate Trigger Current (Tj = 25°C) Gate Voltage (V) 10 100 7 5 4 3 2 10–1 Rated Surge On-State Current 103 7 5 4 3 2 Typical Example IFGT III IFGT I, IRGT III, IRGT I 102 7 5 4 3 2 101 –60 –40 –20 0 20 40 60 80 100 120 140 Gate Current (mA) Junction Temperature (°C) Gate Trigger Voltage vs. Junction Temperature Maximum Transient Thermal Impedance Characteristics (Junction to ambient) Typical Example VFGT I VFGT III VRGT I VRGT III 101 –60 –40 –20 0 20 40 60 80 100 120 140 Junction Temperature (°C) REJ03G0292-0200 Rev.2.00 Mar 22, 2007 Page 3 of 7 Transient Thermal Impedance (°C/W) On-State Current (A) Maximum On-State Characteristics 102 2 3 5 7 103 2 3 5 7 104 2 3 5 7 105 103 7 * 25mm×25mm×t0.7mm 5 Ceramic plate 3 2 102 7 5 3 2 Junction to ambient * 101 7 5 3 2 100 10–1 2 3 5 7 100 2 3 5 7 101 2 3 5 7 102 Conduction Time (Cycles at 60Hz) BCR08AS-12 Allowable Ambient Temperature vs. RMS On-State Current Maximum On-State Power Dissipation 160 1.2 0.8 0.4 Latching Current (mA) 0 0.4 0.8 1.2 1.6 25mm×25mm×t0.7mm 140 Ceramic plate 120 Curves apply regardless of conduction angle Resistive, inductive loads Natural convection 100 80 60 40 20 0 2.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 RMS On-State Current (A) RMS On-State Current (A) Repetitive Peak Off-State Current vs. Junction Temperature Holding Current vs. Junction Temperature 105 7 Typical Example 5 3 2 104 7 5 3 2 103 7 5 3 2 102 –60 –40 –20 0 20 40 60 80 100 120 140 102 7 5 3 2 Holding Current (Tj = t°C) × 100 (%) Holding Current (Tj = 25°C) Repetitive Peak Off-State Current (Tj = t°C) × 100 (%) Repetitive Peak Off-State Current (Tj = 25°C) 0 360° Conduction Resistive, inductive loads Ambient Temperature (°C) 1.6 103 7 5 Typical Example 3 2 102 7 5 3 2 101 –60 –40 –20 0 20 40 60 80 100 120 140 Junction Temperature (°C) Junction Temperature (°C) Latching Current vs. Junction Temperature Breakover Voltage vs. Junction Temperature Distribution T2+, G– Typical Example 101 7 5 3 2 100 7 5 3 T2+, G+ 2 T2–, G– Typical Example T2–, G+ 10–1 0 40 80 –40 120 Junction Temperature (°C) REJ03G0292-0200 Rev.2.00 Mar 22, 2007 Page 4 of 7 160 Breakover Voltage (Tj = t°C) × 100 (%) Breakover Voltage (Tj = 25°C) On-State Power Dissipation (W) 2.0 160 Typical Example 140 120 100 80 60 40 20 0 –60 –40 –20 0 20 40 60 80 100120 140 Junction Temperature (°C) Breakover Voltage vs. Rate of Rise of Off-State Voltage Commutation Characteristics 101 160 Typical Example Tj = 125°C 140 120 I Quadrant 100 80 60 40 III Quadrant 20 0 100 2 3 5 7 101 2 3 5 7 102 2 3 5 7 103 Critical Rate of Rise of Off-State Commutating Voltage (V/µs) Breakover Voltage (dv/dt = xV/µs) × 100 (%) Breakover Voltage (dv/dt = 1V/µs) BCR08AS-12 3 2 100 7 5 Gate Trigger Current (tw) × 100 (%) Gate Trigger Current (DC) 103 7 5 4 3 2 Typical Example Minimum 10–1 10–1 2 3 I Quadrant 5 7 100 6Ω Gate Current Pulse Width (µs) REJ03G0292-0200 Rev.2.00 Mar 22, 2007 Page 5 of 7 5 7 101 6Ω A A 6V 330Ω 330Ω V Test Procedure I Test Procedure II 6Ω 6Ω A 6V 2 3 4 5 7 102 3 Gate Trigger Characteristics Test Circuits V 2 3 4 5 7 101 2 Rate of Decay of On-State Commutating Current (A/ms) 6V 102 7 IRGT I IRGT III IFGT I 5 IFGT III 4 3 2 101 0 10 III Quadrant 3 Characteristics 2 Value Rate of Rise of Off-State Voltage (V/µs) Gate Trigger Current vs. Gate Current Pulse Width Typical Example Tj = 125°C IT = 1A τ = 500µs VD = 200V 7 5 V 330Ω Test Procedure III A 6V V 330Ω Test Procedure IV BCR08AS-12 Package Dimensions Previous Code UPAK / UPAKV RENESAS Code PLZZ0004CA-A 4.5 ± 0.1 (1.5) 2.5 ± 0.1 4.25 Max 0.44 Max 0.8 Min 0.53 Max 0.48 Max 1.5 1.5 3.0 JEITA Package Code RENESAS Code Package Name MASS[Typ.] SC-62 PLZZ0004CB-A SOT-89 0.48g (0.2) φ1 Unit: mm 1.5 ± 0.1 0.44 Max 0.4 1.8 Max MASS[Typ.] 0.050g (2.5) JEITA Package Code SC-62 (0.4) Package Name UPAK Unit: mm 4.6Max 1.5 ± 0 0.1 4.2Max Max 0.8Min 0.8M 2.5 ± 0 0.1 1.6 ± 0.2 0.58Max 1.5 3.0 REJ03G0292-0200 Rev.2.00 Mar 22, 2007 Page 6 of 7 0.48Max +0.03 0.4 –0.05 BCR08AS-12 Order Code Lead form Surface-mounted type Standard packing Taping Quantity 4000 Standard order code Type name +A –T +Direction (1 or 2)+4 Note : Please confirm the specification about the shipping in detail. REJ03G0292-0200 Rev.2.00 Mar 22, 2007 Page 7 of 7 Standard order code example BCR08AS-12A-T14 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. 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