R8A66171DD/SP A2RT (ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) REJ03F0269-0100 Rev. 1.00 Feb.19.2008 DESCRIPTION The R8A66171 is an integrated circuit for asynchronous serial data communications. It is used in combination with an 8-bit microprocessor and is produced using the silicon gate CMOS technology. R8A66171 is the succession product of M66230. FEATURES ● Baud rate generator ● 4-byte FIFO data buffer for transmission and reception ● Error detection : CRC-CCITT ● Wakeup function ● Majority-voting system by sampling three points of received data ● Transmission / reception data format ( number of bits ) Start bit 1 Data bit 8 Wakeup bit 1 or nil Parity bit 1 or nil Stop bit 1 or 2 ● Transmission speed 500Kbps (max) ● Access time ta (/RD-D) : 100ns ● High output current IOH=-24mA IOL=24mA TxD, /RTS, P0, P1 pins ● Schmitt triggered input RxD, /CTS, /RESET pins ● Wide operating supply voltage range (Vcc=3.0~3.6V or Vcc=4.5~5.5V) ● Wide operating temperature range (Ta=-40~85OC) APPLICATION Data communication control that uses microprocessor PIN CONFIGURATION (TOP VIEW) DATA BUS D0 1 24 V CC D1 2 23 TxD TRANSMISSION DATA OUTPUT D2 3 22 RxD RECEPTION DATA INPUT D3 4 21 CTS CLEAR-TO-SEND INPUT D4 5 20 RTS REQUEST-TO-SEND OUTPUT D5 6 19 P0 D6 7 18 P1 PORT OUTPUT D7 8 17 INT INTERRUPT OUTPUT READ CONTROL INPUT RD 9 16 CS CHIP SELECT INPUT WRITE CONTROL INPUT WR 10 15 RESET RESET INPUT COMMAND/DATA C/D CONTROL INPUT GND 11 14 X1 CLOCK INPUT 12 13 X2 CLOCK OUTPUT REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 1 of 22 R8A66171DD/SP FUNCTION The R8A66171 is a UART (Universal Asynchronous Receiver/Transmitter) and is used in the peripheral circuit of a MCU. The R8A66171 receives parallel data, converts into serial format, and then transmits the serial data via the TxD pin. The device also receives data via the RxD pin from external circuits and converts it into parallel format, and sends the parallel data via the data bus. BLOCK DIAGRAM Reset input Command/Data control input Read control input Write control input Chip select input RESET C/D 15 11 RD 9 WR 10 CS 16 D0 1 D1 2 D2 3 READ/ WRITE CONTRO L CIRCUIT 8 TRANSMIT DATA BUFFER 4-BYTE FIFO 8 TRANSMIT CONTROL, ERROR DETECTION CODE GENERATION(CRC) CIRCUIT 8 D3 4 D4 5 D5 6 D6 7 D7 8 Clock input X1 14 Clock output X2 13 Data bus TRANSMIT BUFFER COMMAND REGISTER 24 VCC 12 GND 23 TXD Transmission data output 21 CTS Clear-to-send input 20 RTS Request-to-send output 22 RXD Reception data input 19 P0 18 P1 17 INT 8 STATUS REGISTER DATA 8 BUS BUFFER RECEIVE CONTROL, ERROR DETECTION(CRC) CIRCUIT 8 RECEIVE DATA BUFFER 4-BYTE FIFO RECEIVE BUFFER SAMPLING CLOCK REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 2 of 22 BAUD RATE GENERATOR 1/16 DIVISION CIRCUIT TRANSFER CLOCK Port output Interrupt output R8A66171DD/SP OPERATION The R8A66171 is interfaced to a system bus and provides all functions needed for data communication. 16 A0 Address bus Decoder 4 Control bus I/OR I/OW RESET 8 Data bus 8 C/D CS D0~D7 RD WR RESET R8A66171DD/SP Fig.1 Interface between the R8A66171 and MCU system bus When using the R8A66171, it is necessary to program the initial setting, baud rate, character length, CRC, parity, in accordance with the communication system. Once programmed, the communication system functions are executed continuously. When initial setting of R8A66171 is completed, data communication becomes possible. When the transmitter is transmit-enabled (TXEN) by a command instruction and /CTS is low-level, data transfer starts up. If these conditions are not satisfied, data transmission is not executed. Reception is possible when the receiver is receive-enabled (RXEN) by a command instruction. The MCU is able to read data when the interrupt output, /INT, goes low by packet end (PE) or buffer full (BF). While receiving data, the R8A66171 checks for errors and provides status information. It checks for four types of errors : CRC, parity, overrun and framing errors. When an error occurs, R8A66171 continues operation. The error status is maintained until the error reset, (ER) is modified by a command instruction. The access method of the R8A66171 is shown Table 1. C/D RD WR CS R8A66171 operation L L H L Data bus Receiving data buffer(FIFO) Read receive data L H L L Data bus Transmit data buffer(FIFO) Write transmit data H L H L Data bus Status register Read the status H H L L Data bus Command register Write the command X H H L Data bus : High impedance - X X X H Data bus : High impedance - Note : X="L" or "H" TABLE 1. Access method of the R8A66171 REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 3 of 22 MPU operation R8A66171DD/SP PIN DESCRIPTIONS Pin Name I/O X1 Clock input Input X2 Clock output Output RESET Reset input Input This reset is a master reset, therefore commands should be loaded after the reset. CS Chip select input Input A low level signal on the chip select input enables the R8A66171. The device can not be accessed when the signal is high-level. C/D Command/Data control input Input This signal distinguishes whether the information on the R8A66171 data bus is data, command or status information. When the signal is high-level, the data bus has command or status information. When the signal is low-level, the data bus has data. RD Read control input Input The receiving data or status information is output to the data bus from the R8A66171 by a low-level signal. WR Write control input Input The data or command output from the MCU is written to the R8A66171 by a low-level signal. D0~D7 Data bus This is an 8-bit bi-directional bus buffer. Command, status Input/ information, and transfer data are transferred to/from the MCU via Output this data bus buffer. INT Interrupt output This is used as an interrupt request to MCU. The interrupt request is generated when the receive FIFO is full, the transmit FIFO is Output empty or the block reception is complete. D2 bit of command 6 controls the switching of low-level and high-level interrupt. RxD Reception data input TxD Transmission data output P0 Port output Output P1 Port output This pin has the same function as that of P0 pin and provides Output information of packet transmission's completion. The switching of this function is controlled by command 6, D1 bit. CTS Clear-to-send input Input When the TXEN bit (D0) of command 4 is set to 1 and the /CTS input is low-level, serial data is sent from the TxD pin. This is used as the clear-to-send signal. RTS Request-to-send output Output This is used as the request-to-send signal. This pin is controlled by the D3 bit of command 4. Input Function A crystal is externally connected to these pins for generating an internal clock. An external clock signal can be input to X1 instead of a crystal. Then X2 output opened. The serial data is sent to this pin. Output The serial data is transmitted from this pin. REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 4 of 22 This is an ordinary port pin. This pin is controlled by the D0 bit of command 6. R8A66171DD/SP DISCRIPTION OF FUNCTION ● Baud rate generator The 8-bit programmable divider (baud rate generator) generates the baud rate for transmit or receive. The division rate is (n+1) with a range of n=0~255. The baud rate is calculated by the following formula: baud rate = f(X1) prescaler division (2 or 32)・baud rate generator division rate (n+1)・16 The prescaler division rate is set by the D0 bit of command1. The baud rate generator division rate is set by command2. Example as follows: 9600bps = 9.8304MHz 2・(31+1)・16 ● Block length counter The R8A66171 can handle multiple-bytes of data as one block (packet). Therefore, CRC of bytes is possible. The block length counter is a 6-bit programmable counter. The block length is (m+1) bytes with the allowed values of m=0~63. ● Transmit data buffer (FIFO) The transmit data buffer (FIFO) consists of 4-bytes. The transmit data buffer (FIFO) functions according to the block length. Block length=1~3 When the transmit data buffer (FIFO) becomes empty (buffer empty) and /INT is set to low-active, the interrupt output /INT is set to a low-level. The MCU verifies the buffer is empty when the D2 bit of the status1 information is read. The MCU should write the block length data to the transmit data buffer (FIFO) at this moment. When a block of data is written to the transmit data buffer (FIFO), /CTS is low-level and TXEN is highlevel, the data in the transmit data buffer (FIFO) is sent to the transmit buffer. If /CTS is high-level while data is transmitted, all data is transmitted (including the data in the transmit data buffer (FIFO)). When the buffer becomes empty, the data in the transmit data buffer (FIFO) is not be sent to the transmit buffer until MCU writes a new block of data to the transmit data buffer (FIFO). The MCU can not write new data to the transmit data buffer (FIFO) until the buffer becomes empty. Example : Block length=2 DATA DATA MCU Transmit data buffer(FIFO) TxD pin Transmit buffer(P→S) Block length=4 or more When the transmit data buffer (FIFO) becomes empty and /INT is set low-active, the interrupt output /INT becomes low. The MCU verifies the buffer is empty by reading the D2 bit of the status1 information. When this happens, the MCU should write the 4-bytes of data to the transmit data buffer (FIFO). The data in the transmit data buffer (FIFO) is sent to the transmit buffer when /CTS is low-level and TXEN is high-level. When the number of bytes from the MCU becomes less than 4 at the last stage of the block transmission, the same operation should be made as the block length=1~3. When the buffer becomes empty, the data in the transmit data buffer (FIFO) is not be sent to the transmit buffer until MCU writes data of the fixed block length to the transmit data buffer (FIFO). The MCU cannot write data to the transmit data buffer (FIFO) until the buffer becomes empty. REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 5 of 22 R8A66171DD/SP Example : Block length=6 DATA DATA DATA DATA MCU Transmit data buffer(FIFO) TxD pin Transmit buffer(P→S) or DATA DATA Transmit data buffer(FIFO) ● Receive data buffer (FIFO) The receive data buffer (FIFO) consists of 4-bytes. The receive data buffer (FIFO) functions according to the block length. Block length=1~3 When the data of the block length is received and /INT is set to low-level, the interrupt output /INT becomes low-level. The MCU acknowledges the packet end by setting the D0 bit of the status1 information. In this case, the MCU should read all data from the receive data buffer (FIFO). At the packet end, the data from the receive buffer cannot be transmitted to the receive data buffer (FIFO) until the MCU reads all data in the receive data buffer (FIFO). The MCU cannot read data in the receive data buffer until the packet end. Example : Block length=2 DATA DATA MCU Receive data buffer(FIFO) (Interrupt-packet end) RxD pin Receive buffer(P←S) Block length=4 or more When 4-byte data enters the receive data buffer (FIFO) (buffer full) and /INT is set to low-active, the interrupt output /INT becomes low-level. The MCU acknowledges the buffer full status by setting the D1 bit of the status1 information. In this case, the MCU should read all data in the receive data buffer (FIFO). When the last data enters the receive data buffer (FIFO), the packet end becomes the same operation as for 1~3 byte block length. If the block length is a multiple of four, the D0 and D1 bits of the status1 information are set when the last data enters the receive data buffer (FIFO). At packet end or buffer full, the new data cannot be transferred from the receive buffer to the receive data buffer (FIFO). The MCU cannot read data in the receive data buffer (FIFO) until packet end or buffer full occurs. Example : Block length=6 DATA DATA DATA DATA MCU Receive data buffer(FIFO) (First interrupt-buffer full) or DATA DATA Receive data buffer(FIFO) (Second interrupt-packet end) REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 6 of 22 RxD pin Receive buffer(P←S) R8A66171DD/SP SUPPLEMENTARY DESCRIPTION FIFO The major purpose is not to interrupt the MCU by each character. The MCU is interrupted when: Transmit data buffer (FIFO) empty Receive data buffer (FIFO) full or packet end The MCU interruption interval is as follows: Approximately 90µs (min) until the FIFO becomes full at 500kbps. Approximately 36.7ms (min) until the FIFO becomes full at 1.2kbps. Read/write operation by the MCU should be made for all data in FIFO at once. ● Wakeup The wakeup mode of the R8A66171 can be set by setting the D2 bit of command4 to “1”. In wakeup mode, a 9th bit is automatically added (the wakeup bit). Only the 9th bit of the first byte is “1”, and the remainder blocks 9th bits are set to “0”. The wakeup is used when one master MCU and multiple local MCU are connected by serial I/O. Examples of wakeup are shown below. ① Initial setting The initial setting should be made by the input of each command. ② Wakeup mode The wakeup mode of the R8A66171 is activated by setting D2 bit of the command4 to “1”. Command5 can be input as the second byte of command4 by setting D2 bit of the command4 to “1” and each address is input. In the wakeup mode, the 9th bit is automatically added. Others remain the same. ③ Wakeup and data transfer (between master MCU and local MCU1) Data is transmitted from the master MCU to each local MCU. The first byte should hold the address of the local MCU. (in this case local MCU1.) Each local R8A66171 checks the data (address) against command5 (each address) when the first byte (address) is received. The R8A66171 which matches the address starts to accept the following data (wakeup). The R8A66171 which does not match the address, only accepts data, where the 9th bit is “1”. When CRC is enabled Address of local MCU1 8-bit data The 9th bit Start bit Block check character Transfer block 8-bit data Stop bit 8-bit data The 9th bit Start bit The 9th bit Start bit Stop bit 8-bit data Stop bit Start bit The 9th bit Stop bit The 9th bit 8-bit data Stop Start bit bit The 9th bit Stop bit When parity is enabled Transfer block Address of local MCU1 8-bit data The 9th bit Stop bit 8-bit data The 9th bit Stop bit 8-bit data Note : The w akeup function is automatically canceled w hen the transfer block data has been read by the MCU. (The w akeup mode continues.) Start bit Parity bit Start bit Parity bit Start bit Parity bit 1 to 1 Master MCU REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 7 of 22 R8A66171 R8A66171 Local MCU 1 R8A66171 R8A66171 Local MCU 2 R8A66171 R8A66171 Local MCU 3 R8A66171DD/SP ● Error detection (1)Parity error When a parity error occurs, D5 bit of status1 information is set. The data is send to the receive data buffer (FIFO). (2)Framing error When a framing error occurs, D3 bit of the status1 information is set. The data is sent to the receive data buffer (FIFO). (3)Overrun error When data is received before all data in the receive data buffer (FIFO) has been read by MCU, D4 bit of the status1 information is set as an overrun error. In this case, the new data in the receive buffer are lost. (4)CRC error When an error occurs after receiving block check character, D6 bit of the status1 information is set. The above error information is maintained until D4 bit of command4 is set. ● Error reset When D4 bit of command4 is 1, D3 bit, D4 bit, D5 bit and D6 bit of status1 are reset. When an error reset pulse occurs, D4 bit of command4 becomes 0. Again, D4 bit of command4 need not be adjusted to 0. ● Internal reset When D5 bit of command4 becomes 1, all command status information is reset, and the signal based on reset command status information is output to each output. When an internal reset pulse occurs, D5 bit of command4 becomes 0. Again, D5 bit of command4 need not be adjusted to 0. SUPPLEMENTARY DESCRIPTION Comparison between parity check and CRC ● Parity check Parity check needs only one additional bit and is highly efficient. The formula is straightforward, and includes even parity and odd parity checks. In both cases, one bit is added. ● CRC The CRC poly-nominal expression is CRC-CCITT X16+X12+X5+1. CRC deals with data characters in transmitted or received blocks. (Start, stop and wakeup bits are excluded.) When the CRC is enabled, the transmit and receive data consists of block length (1~64 bytes) + 2 bytes (block check characters). The following table shows the comparison between parity check and CRC. Parity check CRC Burst error is not detected. (50% of which can be detected.) Burst error can be detected. (Burst error detection rate is more than 99.9%.) REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 8 of 22 R8A66171DD/SP PROGRAMMING The command must be loaded first to the R8A66171 by the MCU before data communication. R8A66171 has 6 command registers. Data transfer is possible when commands have been loaded to these command registers after reset. The flowchart of the initial setting is shown in the following diagram. Reset Command1 Command 3 Command 2 Command 4 Command 6 Command 5 Data transfer Flowchart of the R8A66171 initial setting REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 9 of 22 R8A66171DD/SP COMMAND-INSTRUCTION FORMAT The commands are decoded by D7 and D6. Command1 Stop bit 1 : Even parity 0 : Odd parity Parity enable 1 : Enable 0 : Disable CRC enable 1 : Enable 0 : Disable Prescaler 0 D6 ST D5 EP D4 PEN D3 CRCEN D2 BAUD D1 Note2 Parity check Baud rate setting 0 D7 1 : 2 bits 0 : 1 bit 1 : To command2 （Baud rate setting） 1 : 1/32 division 0 : 1/2 division PS D0 Note 1 : Priority is given to parity enable, if parity enable and CRC enable are both "1" (D3, D2=1). Note 2 : TxD output wave is Stop bit (D5) setup value +1 (always). Command2 (Baud rate setting. The second byte when D1 bit of the command1 is set to "1".） 0 ~ 1 0 ~ 1 0 0 0 ~ ~ ~ 1 1 0 ~ ~ 1 1 0 ~ ~ 1 255 0 ~ 1 0 0 ~ 1 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 n 1 Command3 （Block length setting） 0 0 0 0 1 D7 D6 D5 D4 D3 REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 10 of 22 D2 D1 D0 m 0 ~ ~ ~ ~ ~ 1 1 1 63 R8A66171DD/SP Command4 Internal reset Error reset Transmission carrier control Wakeup mode 1 D7 Command5 0 D6 IR D5 ER D4 RTS D3 WUMODE D2 RXEN D1 1 : Reset 1 : Error flag clear 1 : RTS="L" 0 : RTS="H" 1 : Enable 0 : Disable Receive enable 1 : Enable 0 : Disable Transmit enable 1 : Enable 0 : Disable TXEN D0 (Address setting. The second byte when D2 bit of the command4 is set to “1”.) Command5 （ Address setting. The second byte when D2 bit of the command4 bit is set to "1". ） D7 D6 D5 D4 D3 D2 D1 D0 Command6 1 : FIFO disable 0 : FIFO enable 1 : INT 0 : INT 1 : P1=Packet transmission is complete 0 : P1=P0 1 : P0="H" 0 : P0="L" 1 D7 1 D6 D5 D4 REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 11 of 22 D3 D2 D1 D0 R8A66171DD/SP STATUS INFORMATION ・Status 1 and 2 cannot address setting from external pin. Discrimination of status used to D7 bit. ・Status 1 and 2 has read mutually. (There are not continuity read of same status.) Status1 1 indicates that a CRC error is found in the received data 1 indicates that a parity error is found in the received data 1 indicates that an overrun error is found in the received data 1 indicates that a framing error is found in the received data 1 indicates that the transmission data buffer (FIFO) is empty 1 indicates that the received data buffer (FIFO) is full 1 indicates that the received data buffer (FIFO) is packet end 0 CRCE PE OE FE D7 D6 D5 D4 D3 TxBEMP D2 RxBFULL D1 RxBPE D0 Status2 1 indicates that the transmission* characters are not found in the transmitter 1 indicates that packet transmission* is complete from the transmitter 1 indicates that wakeup is maintained 1 indicates the wakeup mode 1 D7 L D6 L D5 L D4 TxEMP D3 TxPE D2 WUEN D1 WUMODE D0 * Transmitter = Transmit data buffer (FIFO) + Transmit buffer REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 12 of 22 R8A66171DD/SP TRANSMISSION FORMAT Transmit format Parity enabled MCU→R8A66171 Data character ( 8 bits ) Assembled data format Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Parity bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) + 1 Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Parity bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) + 1 Transmitter output TxD mark condition CRC enabled MCU→R8A66171 Data character ( 8 bits ) After assembly Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) + 1 Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) + 1 Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) + 1 + Start bit ( 1 bit ) Block check character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) + 1 + Start bit ( 1 bit ) Block check character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) + 1 Transmitter output TxD mark condition Block length m+1 REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 13 of 22 R8A66171DD/SP TRANSMISSION FORMAT Receive format Parity enabled Receiver input RxD mark condition Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Parity bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Parity bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) Receive format R8A66171→MCU Data character ( 8 bits ) CRC enabled Receiver input Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) + Start bit ( 1 bit ) Block check character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) + Start bit ( 1 bit ) Block check character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) RxD mark condition Block length m+1 Receive format R8A66171→MCU Data character ( 8 bits ) REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 14 of 22 R8A66171DD/SP O ABSOLUTE MAXIMUM RATINGS (Ta=-40~85 C, unless otherwise noted) Symbol VCC VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Storage temperature Conditions Value using the GND pin as reference Actually mounted Ratings -0.5~+7.0 -0.5~VCC+0.5 -0.5~VCC+0.5 500 -65~150 Unit V V V mW o C O RECOMMENDED OPERATING CONDITIONS (Ta=-40~85 C, unless otherwise noted) Symbol Parameter VCC Supply voltage GND Topr Ground Operating temperature Min 4.5 3.0 5.0V 3.3V Limits Typ 5.0 3.3 0 -40 Max 5.5 3.6 85 Unit V V V o C ELECTRICAL CHARACTERISTICS 5.0V version support specifications (Ta=-40~85 OC,Vcc=3.0~3.6V,GND=0V, unless otherwise noted) Symbol Parameter VIH VIL VIH VIL VT+ VTVH High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage Positive threshold voltgage Negative threshold voltage Hysteresis width VOH High-level output voltage VOL Low-level output voltage IIH IIL IOZH IOZL ICC High-level input current Low-level input current Off-state high-level output current Off-state low-level output current Static supply current Test conditions /RD, /WR, C//D, /CS, D0~D7 Min 0.75×VCC Limits Typ Max 0.25×VCC 0.8×VCC X1 RxD, /CTS, /RESET IOH=-8mA /INT, D0~D7 IOH=-24mA TxD, /RTS, P0, P1 IOL=8mA /INT, D0~D7 IOL=24mA TxD, /RTS, P0, P1 VI=Vcc VI=GND VO=Vcc VO=GND VI=Vcc, GND 0.2×VCC 0.8×VCC 0.65×VCC 0.35×VCC 0.2×VCC 0.4 VCC-0.8 Unit V V V V V V V V 0.55 V 1.0 -1.0 5.0 -5.0 40 µA µA µA µA mA 3.3V version support specifications (Ta=-40~85 OC,Vcc=3.0~3.6V,GND=0V, unless otherwise noted) Symbol Parameter VIH VIL VIH VIL VT+ VTVH High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage Positive threshold voltgage Negative threshold voltage Hysteresis width VOH High-level output voltage VOL Low-level output voltage IIH IIL IOZH IOZL ICC High-level input current Low-level input current Off-state high-level output current Off-state low-level output current Static supply current REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 15 of 22 Test conditions /RD, /WR, C//D, /CS, D0~D7 X1 RxD, /CTS, /RESET IOH=-4mA /INT, D0~D7 IOH=-12mA TxD, /RTS, P0, P1 IOL=4mA /INT, D0~D7 IOL=12mA TxD, /RTS, P0, P1 VI=Vcc VI=GND VO=Vcc VO=GND VI=Vcc, GND Min 0.75×VCC Limits Typ Max 0.25×VCC 0.8×VCC 0.35×VCC 0.2×VCC 0.4 0.2×VCC 0.8×VCC 0.65×VCC VCC-0.6 Unit V V V V V V V V 0.4 V 1.0 -1.0 5.0 -5.0 25 µA µA µA µA mA R8A66171DD/SP O TIMING REQUIREMENTS (Ta=-40~85 C,Vcc=4.5~5.5V or Vcc=3.0~3.6V, unless otherwise noted) Symbol Limits for 5.0V Test conditions Min Typ Max Parameter tC1(X1) Clock frequency tWH1(X1) Clock high-level pulse width tWL1(X1) Limits for 3.3V Min Typ Max Unit 62.5 66.6 ns 30 32 ns Clock low-level pulse width 30 32 ns tC2(X1) Clock frequency 80 90 ns tWH2(X1) Clock high-level pulse width 38 42 ns tWL2(X1) Clock low-level pulse width 38 42 ns tr(X1) Clock rise time (Except Wakeup, CRC mode) (Wakeup, CRC mode) 20 tf(X1) Clock fall time tsu(A-/R) Address setup time before read (/CS, C//D) 25 20 0 25 0 ns ns ns th(/R-A) Address hold time after read (/CS, C//D) tW(/R) Read pulse width tsu(A-/W) Address setup time before write (/CS, C//D) th(/W-A) Address hold time after write (/CS, C//D) 0 0 ns tW(/W) Write pulse width 100 110 ns tsu(DQ-/W) Data setup time before write 50 55 ns th(/W-DQ) Data hold time after write 5 6 ns trec(/RESET) Recovery time between write 100 110 ns tW(/RESET) 100 110 ns Reset pulse width 0 0 ns 100 110 ns 0 0 ns O SWITCHING CHARACTERISTICS (Ta=-40~85 C,Vcc=4.5~5.5V or Vcc=3.0~3.6V, unless otherwise noted) Symbol tPZH(/R-DQ) Parameter Limits for 5.0V Test conditions Min Typ Max Limits for 3.3V Min Typ Max Unit 100 110 ns 100 110 ns 85 95 ns 85 95 ns 170 185 ns 170 185 ns 150 165 ns 150 165 ns tPLH(/W-/INT) /INT output propagation time after write command tPHL(/W-/INT) (command 4) 100 110 ns 100 110 ns tPLH(/W-/INT) /INT output propagation time after write command tPHL(/W-/INT) (command 6) 100 110 ns 100 110 ns tPLH(/W-P0) 70 75 ns 70 75 ns 70 75 ns 70 75 ns 70 75 ns 70 75 ns tPZL(/R-DQ) tPHZ(/R-DQ) tPLZ(/R-DQ) tPLH(/R-/INT) tPHL(/R-/INT) tPLH(/W-/INT) tPHL(/W-/INT) tPHL(/W-P0) tPLH(/W-P1) tPHL(/W-P1) tPLH(/W-/RTS) tPHL(/W-/RTS) Data output enable time after read Data output disable time after read /INT output propagation time after read data /INT output propagation time after write data P0 output propagation time after write command P1 output propagation time after write command /RTS output propagation time after write command REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 16 of 22 R8A66171DD/SP TEST CIRCUIT Input Vcc Vcc Output RL=1kΩ SW 1 DUT P.G. Parameter SW 1 tPLH, tPHL Open SW 2 Open tPLZ Closed Open tPHZ Open Closed tPZL tPZH Closed Open Open Closed SW 2 (1) The pulse generator (PG) has the following characteristics (10%~90%) 50Ω CL tr=3ns, tf=3ns GND RL=1kΩ (2) The capacitance CL=150pF includes stray wiring capacitance and the probe input capacitance. TIMING DIAGRAM Input/output waveform at read data and read status VCC RD 50% 50% 0V tPZL(/R-DQ) tPLZ(/R-DQ) VOH D0~D7 50% 10% tPZH(/R-DQ) VOL tPHZ(/R-DQ) VOH 90% D0~D7 50% VOL Clock Timing tC(x1) tWL(X1) tWH(X1) 90% VCC 90% 50% 10% X1 tf 50 10% 50% 0V tr REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 17 of 22 R8A66171DD/SP Write control cycle (MCU→R8A66171) tsu(A-/W) CS th(/W-A) 50% VCC 50% 0V VCC C/D 50% tsu(A-/W) th(/W-A) 50% 0V tW (/W) WR VCC 50% 50% 0V tsu(DQ-/W) th(/W-DQ) VCC D0~D7 50% Valid data 50% 0V tPLH,tPHL(/W-/INT) VOH 50% INT VOL tPLH,tPHL(/W-/RTS,P0,P1) VOH RTS, P0, P1 50% VOL Read control cycle (R8A66171→MCU) tsu(A-/R) CS th(/R-A) 50% VCC 50% 0V VCC C/D 50% tsu(A-/R) th(/R-A) 50% tW (/R) RD 50% 0V VCC 50% 0V tPZL,tPZH(/R-DQ) tPLZ,tPHZ(/R-DQ) VOH D0~D7 Valid data VOL REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 18 of 22 R8A66171DD/SP Write data cycle (MCU→R8A66171) tsu(A-/W) CS th(/W-A) 50% 50% 0V tsu(A-/W) C/D VCC th(/W-A) 50% VCC 50% 0V tW (/W) WR VCC 50% 50% 0V tsu(DQ-/W) th(/W-DQ) VCC D0~D7 50% Valid data 50% 0V tPLH,tPHL(/W-/INT) VOH INT 50% VOL Read data cycle (R8A66171→MCU) tsu(A-/R) CS th(/R-A) 50% VCC 50% 0V tsu(A-/R) C/D th(/R-A) 50% VCC 50% 0V tW (/R) RD VCC 50% 50% 0V tPZL,tPZH(/R-DQ) tPLZ,tPHZ(/R-DQ) VOH D0~D7 Valid data VOL tPLH,tPHL(/R-/INT) VOH INT 50% VOL REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 19 of 22 R8A66171DD/SP Transmitter control and flag timing (1) Block length=1 C/D WR TXEN DATA1 DATA2 CTS INT TXBEMP (Status) TXD DATA1 DATA2 (2) Block length=3 C/D WR TXEN DATA1DATA2 DATA3 DATA4DATA5DATA6 CTS INT TXBEMP (Status) TXD DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 (3) Block length=5 C/D WR TXEN CTS DATA1 DATA3 DATA2 DATA4 DATA5 DATA6 DATA8 DATA7 DATA9 DATA10 INT TXBEMP (Status) TXD ~ DATA1 ~ DATA4 The last stop bit of DATA3 REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 20 of 22 DATA5 DATA6 DATA9 DATA10 R8A66171DD/SP Receiver control and flag timing (1) Block length=1 C/D DATA1 RD WR DATA2 RXEN ER INT RXBPE (Status) OE (Status) DATA3 LOST RxD DATA1 DATA2 DATA4 DATA3 (2) Block length=3 C/D RD DATA1DATA2DATA3 WR DATA4DATA5 DATA6 ER RXEN INT RXBPE (Status) OE (Status) DATA7 LOST RxD DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 (3)Block length=5 C/D RD DATA1 DATA3 DATA2 DATA4 WR DATA6 DATA8 DATA7 DATA9 DATA5 ER RXEN INT RXBFULL (Status) RXBPE (Status) OE (Status) DATA10 LOST RxD ~ ~ DATA1 DATA4 REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 21 of 22 DATA5 DATA6 DATA9 DATA10 R8A66171DD/SP PACKAGE OUTLINE Product Name R8A66171DD R8A66171SP Package 24pin DIP 24pin SOP RENESAS Code PRDP0024AF-A PRSP0024DF-A Previous Code 24P4X-A 24P2X-B All trademarks and registered trademarks are the property of their respective owners. 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