SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD1331 Product Preview 96RGB x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller This document contains information on a product under development. Solomon Systech reserves the right to change or discontinue this product without notice. http://www.solomon-systech.com SSD1331 Rev 0.13 P 1/64 Mar 2006 Copyright ¤ 2006 Solomon Systech Limited CONTENTS CONTENTS ......................................................................................................................................................... 2 1 GERENAL INFORMATION ..................................................................................................................... 6 2 FEATURES .............................................................................................................................................. 6 3 ORDERING INFORMATION ................................................................................................................... 6 4 BLOCK DIAGRAM .................................................................................................................................. 7 5 SSD1331Z GOLD BUMP DIE PAD ASSIGNMENT................................................................................ 8 6 PIN DESCRIPTION................................................................................................................................ 12 7 FUNCTIONAL BLOCK DESCRIPTIONS .............................................................................................. 15 7.1 MCU INTERFACE SELECTION ................................................................................................................. 15 7.1.1 6800-series Parallel Interface ...................................................................................................... 15 7.1.2 8080-series Parallel Interface ...................................................................................................... 16 7.1.3 Serial Interface............................................................................................................................. 17 7.2 COMMAND DECODER .............................................................................................................................18 7.3 OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR ............................................................................ 18 7.3.1 Oscillator ...................................................................................................................................... 18 7.3.2 FR synchronization ...................................................................................................................... 19 7.4 RESET CIRCUIT ..................................................................................................................................... 19 7.5 GRAPHIC DISPLAY DATA RAM (GDDRAM)............................................................................................ 20 7.5.1 GDDRAM structure ...................................................................................................................... 20 7.5.2 Data bus to RAM mapping under different input mode ............................................................... 20 7.5.3 RAM mapping and Different color depth mode............................................................................ 21 7.6 GRAY SCALE DECODER .........................................................................................................................21 7.7 SEG / COM DRIVING BLOCK .................................................................................................................. 23 7.8 COMMON AND SEGMENT DRIVERS .......................................................................................................... 24 7.9 POWER ON AND OFF SEQUENCE ........................................................................................................... 27 8 COMMAND TABLE ............................................................................................................................... 28 8.1 9 DATA READ / WRITE ..............................................................................................................................34 COMMAND DESCRIPTIONS ................................................................................................................ 35 9.1 FUNDAMENTAL COMMAND ......................................................................................................................35 9.1.1 Set Column Address (15h)........................................................................................................... 35 9.1.2 Set Row Address (75h)................................................................................................................ 35 9.1.3 Set Contrast for Color A, B, C (81h, 82h, 83h) ...........................................................................36 9.1.4 Master Current Control (87h) ....................................................................................................... 36 9.1.5 Set Second Pre-charge Speed for Color A, B, C (8Ah)............................................................... 37 9.1.6 Set Re-map & Data Format (A0h) ............................................................................................... 37 9.1.7 Set Display Start Line (A1h)......................................................................................................... 42 9.1.8 Set Display Offset (A2h) .............................................................................................................. 42 9.1.9 Set Display Mode (A4h ~ A7h) .................................................................................................... 45 9.1.10 Set Multiplex Ratio (A8h) ............................................................................................................. 45 9.1.11 Set Master Configuration (ADh)................................................................................................... 45 9.1.12 Set Display On/Off (AEh / AFh) ................................................................................................... 45 9.1.13 Power Save Mode (B0h).............................................................................................................. 45 9.1.14 Phase 1 and 2 Period Adjustment (B1h) ..................................................................................... 45 9.1.15 Set Display Clock Divide Ratio/ Oscillator Frequency (B3h) ....................................................... 46 9.1.16 Set Gray Scale Table (B8h) ......................................................................................................... 46 9.1.17 Enable Linear Gray Scale Table (B9h) ........................................................................................ 47 9.1.18 Set Pre-charge voltage (BBh) ...................................................................................................... 47 9.1.19 Set VCOMH Voltage (BEh)..............................................................................................................47 9.1.20 NOP (BCh, BDh, E3h) ................................................................................................................. 47 9.1.21 Set Command Lock (FDh) ........................................................................................................... 47 9.2 GRAPHIC ACCELERATION COMMAND SET DESCRIPTION.......................................................... 48 9.2.1 Draw Line (21h) ........................................................................................................................... 48 9.2.2 Draw Rectangle (22h) .................................................................................................................. 48 9.2.3 Copy (23h) ................................................................................................................................... 49 Solomon Systech Mar 2006 P 2/64 Rev 0.13 SSD1331 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.2.9 Dim Window (24h) ....................................................................................................................... 49 Clear Window (25h) ..................................................................................................................... 50 Fill Enable/Disable (26h).............................................................................................................. 50 Continuous Horizontal & Vertical Scrolling Setup (27h) .............................................................. 51 Deactivate scrolling (2Eh) ............................................................................................................ 51 Activate scrolling (2Fh) ................................................................................................................ 51 10 MAXIMUM RATINGS............................................................................................................................. 52 11 DC CHARACTERISTICS....................................................................................................................... 53 12 AC CHARACTERISTICS....................................................................................................................... 54 13 APPLICATION EXAMPLE .................................................................................................................... 58 14 PACKAGE OPTIONS ............................................................................................................................ 59 14.1 14.2 14.3 SSD1331Z DIE TRAY INFORMATION ................................................................................................... 59 SSD1331U1R1 COF PACKAGE DIMENSIONS.............................................................................. 60 SSD1331U1R1 COF PACKAGE PIN ASSIGNMENT...................................................................... 62 SSD1331 Rev 0.13 P 3/64 Mar 2006 Solomon Systech TABLES Table 1 - Ordering Information ............................................................................................................................ 6 Table 2 - SSD1331Z Die Pad Coordinates.......................................................................................................... 9 Table 3 - Bus Interface selection ....................................................................................................................... 12 Table 4 - MCU interface assignment under different bus interface mode......................................................... 15 Table 5 - Control pins of 6800 interface ............................................................................................................ 15 Table 6 - Control pins of 8080 interface ............................................................................................................ 16 Table 7 - Control pins of 8080 interface (Alternative form)................................................................................ 17 Table 8 - Control pins of Serial interface ........................................................................................................... 17 Table 9 - Data bus usage under different bus width and color depth mode...................................................... 20 Table 10 - Command Table............................................................................................................................... 28 Table 11 - Address increment table (Automatic) ............................................................................................... 34 Table 12 - Illustration of different COM output settings ..................................................................................... 39 Table 13 - Example of Set Display Offset and Display Start Line with no Remap............................................ 43 Table 14 - Example of Set Display Offset and Display Start Line with Remap ................................................. 44 Table 15 - Result of Change of Brightness by Dim Window Command............................................................ 49 Table 16 - Maximum Ratings............................................................................................................................. 52 Table 17 - DC Characteristics ........................................................................................................................... 53 Table 18 - AC Characteristics............................................................................................................................ 54 Table 19 - 6800-Series MPU Parallel Interface Timing Characteristics ............................................................ 55 Table 20 - 8080-Series MPU Parallel Interface Timing Characteristics ............................................................ 56 Table 21 - Serial Interface Timing Characteristics ............................................................................................ 57 Table 22 - SSD1331U1R1 pin assignment ....................................................................................................... 63 Solomon Systech Mar 2006 P 4/64 Rev 0.13 SSD1331 FIGURES Figure 1 - SSD1331 Block Diagram .................................................................................................................... 7 Figure 2 - SSD1331Z Die Drawing ...................................................................................................................... 8 Figure 3 - SSD1331Z Alignment mark dimensions ........................................................................................... 11 Figure 4 - Display data read back procedure - insertion of dummy read .......................................................... 16 Figure 5 - Display data read back procedure - insertion of dummy read .......................................................... 16 Figure 6 - Write procedure in SPI mode ............................................................................................................ 17 Figure 7 - Oscillator Circuit ................................................................................................................................ 18 Figure 8 - 65k Color Depth Graphic Display Data RAM Structure .................................................................... 20 Figure 9 - 256-color mode mapping .................................................................................................................. 21 Figure 10 - Relation between GDRAM content and gray scale table entry for three colors in 65K color mode21 Figure 11 - Illustration of relation between graphic display RAM value and gray scale control ........................ 22 Figure 12 - IREF Current Setting by Resistor Value ............................................................................................ 23 Figure 13 - ISEG current vs VCC setting at constant IREF, Contrast = FFh ........................................................... 23 Figure 14 - Segment and Common Driver Block Diagram ................................................................................ 24 Figure 15 - Segment and Common Driver Signal Waveform ............................................................................ 25 Figure 16 - Gray Scale Control by PWM in Segment........................................................................................ 26 Figure 17 : The Power ON sequence ................................................................................................................ 27 Figure 18 : The Power OFF sequence .............................................................................................................. 27 Figure 19 - Example of Column and Row Address Pointer Movement............................................................. 35 Figure 20 - Segment Output Current for Different Contrast Control and Master Current Setting ..................... 36 Figure 21 - Effect of setting the second pre-charge under different speeds ..................................................... 37 Figure 22 - Address Pointer Movement of Horizontal Address Increment Mode .............................................. 37 Figure 23 - Address Pointer Movement of Vertical Address Increment Mode .................................................. 37 Figure 24 - Example of Column Address Mapping............................................................................................ 38 Figure 25 - COM Pins Hardware Configuration (MUX ratio: 64) ....................................................................... 40 Figure 26 - Typical Oscillator frequency adjustment by B3 command .............................................................. 46 Figure 27 - Example of gamma correction by gray scale table setting ............................................................. 47 Figure 28 – Typical Pre-charge voltage level setting by command BBh........................................................... 47 Figure 29 - Example of Draw Line Command ................................................................................................... 48 Figure 30 - Example of Draw Rectangle Command.......................................................................................... 48 Figure 31 - Example of Copy Command ........................................................................................................... 49 Figure 32 - Example of Copy + Clear = Move Command ................................................................................ 50 Figure 33 - Examples of Continuous Horizontal and Vertical Scrolling command setup .................................. 51 Figure 34 - 6800-series parallel interface characteristics.................................................................................. 55 Figure 35 - 8080-series parallel interface characteristics.................................................................................. 56 Figure 36 - Serial interface characteristics ........................................................................................................ 57 Figure 37 - Application Example for SSD1331U1R1......................................................................................... 58 Figure 38 - Die Tray Information........................................................................................................................ 59 Figure 39 - SSD1331U1R1 outline drawing ...................................................................................................... 60 Figure 40 - SSD1331U1R1 pin assignment drawing......................................................................................... 62 SSD1331 Rev 0.13 P 5/64 Mar 2006 Solomon Systech 1 GERENAL INFORMATION The SSD1331 is a single chip CMOS OLED/PLED driver with 288 segments and 64 commons output, supporting up to 96RGB x 64 dot matrix display. This chip is designed for Common Cathode type OLED/PLED panel. The SSD1331 had embedded Graphic Display Data RAM (GDDRAM). It supports with 8, 9, 16 bits 8080 / 6800 parallel interface as well as serial peripheral interface. It has 256-step contrast and 65K color control. To facilitate communication between lower operating voltages MCU, it has separate power for I/O interface logic. SSD1331 is suitable for mobile phones, MP3, MP4 and other industrial devices. 2 FEATURES 3 Resolution: 96RGB x 64 dot matrix panel 65k color depth support by embedded 96x64x16 bit GDDRAM display buffer Power supply: for IC logic o VDD = 2.4V to 3.5V o VCC = 8.0V to 16.0V for Panel driving o VDDIO = 1.6V to VDD for MCU interface Segment maximum source current: 200uA Common maximum sink current: 60mA 256 step contrast control for the each color component plus 16 step master current control Pin selectable MCU interface o 8/9/16 bits 6800-series parallel Interface o 8/9/16 bits 8080-series Parallel Interface o Serial Peripheral Interface Color swapping function (RGB <-> BGR) Graphic Accelerating Command (GAC) set with Continuous Horizontal, Vertical and Diagonal Scrolling Programmable Frame Rate Wide range of operating temperature: -40 to 85 °C ORDERING INFORMATION Table 1 - Ordering Information Ordering Part Number SEG COM Package Form Reference SSD1331Z 96x3 64 COG Page 8, 59 SSD1331U1R1 Solomon Systech 96x3 64 COF Page 60 Remark • • • 35mm film, 5 sprocket hole 8 bit or SPI interface Output lead pitch: 0.06mm for SEG, 0.09mm for COM Mar 2006 P 6/64 Rev 0.13 SSD1331 4 BLOCK DIAGRAM SSD1331 Rev 0.13 P 7/64 SEG/COM Driving block VD D B VS S B GDR FB VB R E F Mar 2006 SC95 SB95 SA95 SC94 SB94 SA94 SC93 SB93 SA93 . . . SC2 SB2 SA2 SC1 SB1 SA1 SC0 SB0 SA0 COM0 COM2 COM4 . . . COM58 COM60 COM62 IR E F VC O M H Display Timing Generator FR CL GP1 CLS GP0 Oscillator Command Decoder VDDIO VSS VLSS AVDD Common Drivers (odd) VCC VDD Segment Drivers D[15:0] COM63 COM61 COM59 . . . COM5 COM3 COM1 Common Drivers (Even) BS[3:0] GDDRAM MCU Interface RES# CS# D/C# E(RD#) R/W #(WR#) Gray Scale Decoder Figure 1 - SSD1331 Block Diagram Solomon Systech 5 SSD1331Z GOLD BUMP DIE PAD ASSIGNMENT Figure 2 - SSD1331Z Die Drawing Pad 1 Die size Die height Min I/O pad pitch Min SEG pad pitch Min COM pad pitch Bump height 13.1mm x 1.58mm 457um 76.2 um 40.2 um 41.8 um Nominal 15um Bump size Pad 1-163 Pad164-195, 486-517 Pad 196-485 50um x 72um 72um x 28um 28um x 72um Alignment mark (5446.0, -402.0) (-5446.0, -402.0) + shape + shape SSD1331Z Solomon Systech 75um x 75um 75um x 75um Y X Pad 1,2,3,…->163 Gold Bumps face up Mar 2006 P 8/64 Rev 0.13 SSD1331 Table 2 - SSD1331Z Die Pad Coordinates P a d no . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 P ad N ame NC NC NC NC NC NC VCC VCC VCC VLSS VLSS VLSS VLSS VLSS VLSS VLSS VLSS VLSS VLSS VLSS VLSS VSS VSS VSS B GGND VDD VDD VDD VDDIO VDDIO VDDIO VCC VCC VCC VSSB VSSB VSSB GDR GDR GDR GDR GDR GDR GDR VDDB VDDB VDDB VDDB VDDB VDD VDDIO VDD VDD FB VB REF VSS GP 0 GP 1 VDDIO VCIR VCIR VCIR VCIR VCIR VDD VDD VDD VDD A VDD A VDD VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO B S0 VSS B S1 VDDIO SSD1331 X - A xis -6319.4 -6243.2 -6167.0 -6090.8 -6014.6 -5791.2 -5715.0 -5638.8 -5562.6 -5486.4 -5410.2 -5334.0 -5257.8 -5181.6 -5105.4 -5029.2 -4953.0 -4876.8 -4800.6 -4724.4 -4648.2 -4572.0 -4495.8 -4419.6 -4343.4 -4267.2 -4191.0 -4114.8 -4038.6 -3962.4 -3886.2 -3810.0 -3733.8 -3657.6 -3581.4 -3505.2 -3429.0 -3352.8 -3276.6 -3200.4 -3124.2 -3048.0 -2971.8 -2895.6 -2819.4 -2743.2 -2667.0 -2590.8 -2514.6 -2438.4 -2362.2 -2286.0 -2209.8 -2133.6 -2057.4 -1981.2 -1905.0 -1828.8 -1752.6 -1676.4 -1600.2 -1524.0 -1447.8 -1371.6 -1295.4 -1219.2 -1143.0 -1066.8 -990.6 -914.4 -838.2 -762.0 -685.8 -609.6 -533.4 -457.2 -381.0 -304.8 -228.6 -152.4 Rev 0.13 Y - A xis -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 P 9/64 P a d no . 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Mar 2006 P ad N ame B S2 VSS B S3 VDDIO VDDIO IREF VCC VCC VCC FR CL VSS CLS VDDIO VDDIO VDDIO VDDIO CSB VSS RESB VDDIO VDDIO DC VSS RW E VDDIO VDD VDD VDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS TR11 TR10 TR9 TR8 TR7 TR6 VSS TR5 TR4 TR3 TR2 TR1 TR0 VSS VCOM H VCOM H VCOM H VDD VDD VDDIO VDDIO VCC VCC VCC VCC VCC VCC NC VLSS VLSS NC NC NC X - A xis -76.2 0.0 76.2 152.4 228.6 304.8 381.0 457.2 533.4 609.6 685.8 762.0 838.2 914.4 990.6 1066.8 1143.0 1219.2 1295.4 1371.6 1447.8 1524.0 1600.2 1676.4 1752.6 1828.8 1905.0 1981.2 2057.4 2133.6 2209.8 2286.0 2362.2 2438.4 2514.6 2590.8 2667.0 2743.2 2819.4 2895.6 2971.8 3048.0 3124.2 3200.4 3276.6 3352.8 3429.0 3505.2 3581.4 3657.6 3733.8 3810.0 3886.2 3962.4 4038.6 4114.8 4191.0 4267.2 4343.4 4419.6 4495.8 4572.0 4648.2 4724.4 4800.6 4876.8 4953.0 5029.2 5105.4 5181.6 5257.8 5334.0 5410.2 5486.4 5562.6 5638.8 5715.0 5791.2 6014.6 6090.8 Y - A xis -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 -712.5 P a d no . 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 P ad N ame NC NC NC COM 31 COM 30 COM 29 COM 28 COM 27 COM 26 COM 25 COM 24 COM 23 COM 22 COM 21 COM 20 COM 19 COM 18 COM 17 COM 16 COM 15 COM 14 COM 13 COM 12 COM 11 COM 10 COM 9 COM 8 COM 7 COM 6 COM 5 COM 4 COM 3 COM 2 COM 1 COM 0 VLSS SA 0 SB 0 SC0 SA 1 SB 1 SC1 SA 2 SB 2 SC2 SA 3 SB 3 SC3 SA 4 SB 4 SC4 SA 5 SB 5 SC5 SA 6 SB 6 SC6 SA 7 SB 7 SC7 SA 8 SB 8 SC8 SA 9 SB 9 SC9 SA 10 SB 10 SC10 SA 11 SB 11 SC11 SA 12 SB 12 SC12 SA 13 SB 13 SC13 SA 14 SB 14 X - A xis 6167.0 6243.2 6319.4 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 6420.1 5908.5 5828.1 5787.9 5747.7 5707.5 5667.3 5627.1 5586.9 5546.7 5506.5 5466.3 5426.1 5385.9 5345.7 5305.5 5265.3 5225.1 5184.9 5144.7 5104.5 5064.3 5024.1 4983.9 4943.7 4903.5 4863.3 4823.1 4782.9 4742.7 4702.5 4662.3 4622.1 4581.9 4541.7 4501.5 4461.3 4421.1 4380.9 4340.7 4300.5 4260.3 4220.1 4179.9 4139.7 4099.5 Y - A xis -712.5 -712.5 -712.5 -647.9 -606.1 -564.3 -522.5 -480.7 -438.9 -397.1 -355.3 -313.5 -271.7 -229.9 -188.1 -146.3 -104.5 -62.7 -20.9 20.9 62.7 104.5 146.3 188.1 229.9 271.7 313.5 355.3 397.1 438.9 480.7 522.5 564.3 606.1 647.9 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 Solomon Systech P a d no . 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 P ad N ame SC14 SA 15 SB 15 SC15 SA 16 SB 16 SC16 SA 17 SB 17 SC17 SA 18 SB 18 SC18 SA 19 SB 19 SC19 SA 20 SB 20 SC20 SA 21 SB 21 SC21 SA 22 SB 22 SC22 SA 23 SB 23 SC23 SA 24 SB 24 SC24 SA 25 SB 25 SC25 SA 26 SB 26 SC26 SA 27 SB 27 SC27 SA 28 SB 28 SC28 SA 29 SB 29 SC29 SA 30 SB 30 SC30 SA 31 SB 31 SC31 SA 32 SB 32 SC32 SA 33 SB 33 SC33 SA 34 SB 34 SC34 SA 35 SB 35 SC35 SA 36 SB 36 SC36 SA 37 SB 37 SC37 SA 38 SB 38 SC38 SA 39 SB 39 SC39 SA 40 SB 40 SC40 SA 41 X - A xis 4059.3 4019.1 3978.9 3938.7 3898.5 3858.3 3818.1 3777.9 3737.7 3697.5 3657.3 3617.1 3576.9 3536.7 3496.5 3456.3 3416.1 3375.9 3335.7 3295.5 3255.3 3215.1 3174.9 3134.7 3094.5 3054.3 3014.1 2973.9 2933.7 2893.5 2853.3 2813.1 2772.9 2732.7 2692.5 2652.3 2612.1 2571.9 2531.7 2491.5 2451.3 2411.1 2370.9 2330.7 2290.5 2250.3 2210.1 2169.9 2129.7 2089.5 2049.3 2009.1 1968.9 1928.7 1888.5 1848.3 1808.1 1767.9 1727.7 1687.5 1647.3 1607.1 1566.9 1526.7 1486.5 1446.3 1406.1 1365.9 1325.7 1285.5 1245.3 1205.1 1164.9 1124.7 1084.5 1044.3 1004.1 963.9 923.7 883.5 Solomon Systech Y - A xis 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 P a d no . 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 P ad N ame SB 41 SC41 SA 42 SB 42 SC42 SA 43 SB 43 SC43 SA 44 SB 44 SC44 SA 45 SB 45 SC45 SA 46 SB 46 SC46 SA 47 SB 47 SC47 SA 48 SB 48 SC48 SA 49 SB 49 SC49 SA 50 SB 50 SC50 SA 51 SB 51 SC51 SA 52 SB 52 SC52 SA 53 SB 53 SC53 SA 54 SB 54 SC54 SA 55 SB 55 SC55 SA 56 SB 56 SC56 SA 57 SB 57 SC57 SA 58 SB 58 SC58 SA 59 SB 59 SC59 SA 60 SB 60 SC60 SA 61 SB 61 SC61 SA 62 SB 62 SC62 SA 63 SB 63 SC63 SA 64 SB 64 SC64 SA 65 SB 65 SC65 SA 66 SB 66 SC66 SA 67 SB 67 SC67 X - A xis 843.3 803.1 762.9 722.7 682.5 642.3 602.1 561.9 521.7 481.5 441.3 401.1 360.9 320.7 280.5 240.3 200.1 159.9 119.7 79.5 -81.3 -121.5 -161.7 -201.9 -242.1 -282.3 -322.5 -362.7 -402.9 -443.1 -483.3 -523.5 -563.7 -603.9 -644.1 -684.3 -724.5 -764.7 -804.9 -845.1 -885.3 -925.5 -965.7 -1005.9 -1046.1 -1086.3 -1126.5 -1166.7 -1206.9 -1247.1 -1287.3 -1327.5 -1367.7 -1407.9 -1448.1 -1488.3 -1528.5 -1568.7 -1608.9 -1649.1 -1689.3 -1729.5 -1769.7 -1809.9 -1850.1 -1890.3 -1930.5 -1970.7 -2010.9 -2051.1 -2091.3 -2131.5 -2171.7 -2211.9 -2252.1 -2292.3 -2332.5 -2372.7 -2412.9 -2453.1 Y - A xis 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 P a d no . 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 Mar 2006 P 10/64 P ad N ame SA 68 SB 68 SC68 SA 69 SB 69 SC69 SA 70 SB 70 SC70 SA 71 SB 71 SC71 SA 72 SB 72 SC72 SA 73 SB 73 SC73 SA 74 SB 74 SC74 SA 75 SB 75 SC75 SA 76 SB 76 SC76 SA 77 SB 77 SC77 SA 78 SB 78 SC78 SA 79 SB 79 SC79 SA 80 SB 80 SC80 SA 81 SB 81 SC81 SA 82 SB 82 SC82 SA 83 SB 83 SC83 SA 84 SB 84 SC84 SA 85 SB 85 SC85 SA 86 SB 86 SC86 SA 87 SB 87 SC87 SA 88 SB 88 SC88 SA 89 SB 89 SC89 SA 90 SB 90 SC90 SA 91 SB 91 SC91 SA 92 SB 92 SC92 SA 93 SB 93 SC93 SA 94 SB 94 Rev 0.13 X - A xis -2493.3 -2533.5 -2573.7 -2613.9 -2654.1 -2694.3 -2734.5 -2774.7 -2814.9 -2855.1 -2895.3 -2935.5 -2975.7 -3015.9 -3056.1 -3096.3 -3136.5 -3176.7 -3216.9 -3257.1 -3297.3 -3337.5 -3377.7 -3417.9 -3458.1 -3498.3 -3538.5 -3578.7 -3618.9 -3659.1 -3699.3 -3739.5 -3779.7 -3819.9 -3860.1 -3900.3 -3940.5 -3980.7 -4020.9 -4061.1 -4101.3 -4141.5 -4181.7 -4221.9 -4262.1 -4302.3 -4342.5 -4382.7 -4422.9 -4463.1 -4503.3 -4543.5 -4583.7 -4623.9 -4664.1 -4704.3 -4744.5 -4784.7 -4824.9 -4865.1 -4905.3 -4945.5 -4985.7 -5025.9 -5066.1 -5106.3 -5146.5 -5186.7 -5226.9 -5267.1 -5307.3 -5347.5 -5387.7 -5427.9 -5468.1 -5508.3 -5548.5 -5588.7 -5628.9 -5669.1 Y - A xis 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 643.6 SSD1331 P a d no . 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 P ad N ame SC94 SA 95 SB 95 SC95 VLSS COM 32 COM 33 COM 34 COM 35 COM 36 COM 37 COM 38 COM 39 COM 40 COM 41 COM 42 COM 43 COM 44 COM 45 COM 46 COM 47 COM 48 COM 49 COM 50 COM 51 COM 52 COM 53 COM 54 COM 55 COM 56 COM 57 COM 58 COM 59 COM 60 COM 61 COM 62 COM 63 X - A xis -5709.3 -5749.5 -5789.7 -5829.9 -5910.3 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 -6420.1 Y - A xis 643.6 643.6 643.6 643.6 643.6 647.9 606.1 564.3 522.5 480.7 438.9 397.1 355.3 313.5 271.7 229.9 188.1 146.3 104.5 62.7 20.9 -20.9 -62.7 -104.5 -146.3 -188.1 -229.9 -271.7 -313.5 -355.3 -397.1 -438.9 -480.7 -522.5 -564.3 -606.1 -647.9 Figure 3 - SSD1331Z Alignment mark dimensions + shape Unit in um SSD1331 Rev 0.13 P 11/64 Mar 2006 Solomon Systech 6 PIN DESCRIPTION Pin Name VDD Pin Type Description Power Power supply pin for core VDD AVDD VDDIO Power Power Analog power supply. It must be connected to VDD during operation. Power supply for interface logic level. It should be match with the MCU interface voltage level. VDDIO must always be equal or lower than VDD. VCC Power Power supply for panel driving voltage. This is also the most positive power voltage supply pin. VSS Power Ground pin VLSS Power Analog system ground pin. VCOMH O COM signal deselected voltage level. A capacitor should be connected between this pin and VSS. BGGND Power Connect to Ground VDDB Power Reserved pin. It should be connect to VDD externally. VSSB Power Reserved pin. It should be connected to VSS externally. GDR O Reserved pin. Keep NC (i.e. no connection). FB I Reserved pin. Keep NC (i.e. no connection). VBREF O Reserved pin. Keep NC (i.e. no connection). GP0 I/O Reserved pin. Keep NC (i.e. no connection). GP1 I/O Reserved pin. Keep NC (i.e. no connection). VCIR O Reserved pin. Keep NC (i.e. no connection). BS[3:0] I MCU bus interface selection pins. Table 3 - Bus Interface selection BS[3:0] 0000 0100 0101 0110 0111 1100 1110 IREF I Bus Interface Selection SPI 8-bit 6800 parallel 16-bit 6800 parallel 8-bit 8080 parallel 16-bit 8080 parallel 9-bit 6800 parallel 9-bit 8080 parallel This pin is the segment output current reference pin. A resistor should be connected between this pin and VSS to maintain the IREF current at 10uA. Please refer to Figure 12 for the details formula of resistor value. Solomon Systech Mar 2006 P 12/64 Rev 0.13 SSD1331 Pin Name FR Pin Type Description O This pin outputs RAM write synchronization signal. Proper timing between MCU data writing and frame display timing can be achieve to prevent tearing effect. Keep NC if not used. Refer to section 7.3.2 for details usage. CL I External clock input pin. When internal clock is enable, this pin is not used and should be kept NC. When internal clock is disable, this pin is the external clock source input pin. CLS I Internal clock selection pin. When this pin is pulled high (i.e. connect to VDDIO), internal oscillator is enable (normal operation). When this pin is pulled low, an external clock signal should be connected to CL. CS# I This pin is the chip select input connecting to the MCU. RES# I This pin is reset signal input. When the pin is low, initialization of the chip is executed. Keep this pin high (i.e. connect to VDDIO) during normal operation. D/C# I This pin is Data/Command control pin connecting to the MCU. When the pin is pulled high (i.e. connect to VDDIO), the data at D[15:0]will be interpreted as display data. When the pin is pulled low, the data at D[15:0] will be interpreted as command. R/W# (WR#) I This pin is read / write control input pin connecting to the MCU interface. When interfacing to a 6800-series microprocessor, this pin will be used as Read/Write (R/W#) selection input. Read mode will be carried out when this pin is pulled high (i.e. connect to VDDIO) and write mode when low. When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data write operation is initiated when this pin is pulled low and the chip is selected. When serial interface is selected, this pin R/W#(WR#) must be connected to VSS. E (RD#) I This pin is MCU interface input. When interfacing to a 6800-series microprocessor, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled high (i.e. connect to VDDIO) and the chip is selected. When connecting to an 8080-microprocessor, this pin receives the Read (RD#) signal. Read operation is initiated when this pin is pulled low and the chip is selected. When serial interface is selected, this pin E(RD#) must be connected to VSS. D[15:0] I/O These pins are bi-directional data bus connecting to the MCU data bus. Unused pins are recommended to tie low. (Except for D2 pin in serial mode) Refer to Section 7.1 for different bus interface connection. SA[95:0] SB[95:0] SC[95:0] O These pins provide the OLED segment driving signals. These pins are in high impedance state when display is off by command Set Display Off. These 288 segment pins are divided into 3 groups, SA, SB and SC. Each group can have different color settings for color A, B and C. SSD1331 Rev 0.13 P 13/64 Mar 2006 Solomon Systech Pin Name COM[63:0] Pin Type Description I/O These pins provide the Common switch signals to the OLED panel. These pins are in high impedance state when display is off by command Set Display Off. TR[11:0] NC Solomon Systech I NC Testing reserved pins. These pins should be kept float. Dummy pins. These pins should be kept float and should not be connected to any other signal pins nor any electrical signal. Do not connect NC pins together. Mar 2006 P 14/64 Rev 0.13 SSD1331 7 FUNCTIONAL BLOCK DESCRIPTIONS 7.1 MCU Interface Selection SSD1331 MCU interface consist of 16 data pin and 5 control pins. The pin assignment at different interface mode is summarized in Table 4. Different MCU mode can be set by hardware selection on BS[3:0] pins (refer to Table 3 for BS pins setting) Table 4 - MCU interface assignment under different bus interface mode ʳʳʳʳʳʳʳʳʳʳʳʳʳʳʳʳʳˣ˼́ʳˡ˴̀˸ ˕̈̆ʳ˜́̇˸̅˹˴˶˸ ˋ˵ʳ˂ʳˋ˃ˋ˃ ˋ˵ʳ˂ʳˉˋ˃˃ ˌ˵ʳ˂ʳˋ˃ˋ˃ ˌ˵ʳ˂ʳˉˋ˃˃ ˄ˉ˵ʳ˂ʳˋ˃ˋ˃ ˄ˉ˵ʳ˂ʳˉˋ˃˃ ˦ˣ˜ 7.1.1 ˗˴̇˴ʳ˂ʳ˖̂̀̀˴́˷ʳ˜́̇˸̅˹˴˶˸ ˗˄ˈ ˗˄ˇ ˗˄ˆ ˗˄˅ ˗˄˄ ˗˄˃ ˗ˌ ˗ˋ ˗ˊ ˗ˉ ˗ˈ Tie Low Tie Low Tie Low Tie Low ˗˄ˈˀ˗˃ ˗˄ˈˀ˗˃ Tie Low ˗ˇ ˗ˆ ˗˅ ˗ˊˀ˗˃ ˗ˊˀ˗˃ ˗ˋˀ˗˃ ˗ˋˀ˗˃ ˗˄ ˗˃ ˡ˖ ˦˗˜ˡ SCLK ˖̂́̇̅̂˿ʳ˦˼˺́˴˿ ˘ ˥˂˪ʶ ˖˦ʶ ˗˂˖ʶ ˥˗ʶ ˪˥ʶ ˖˦ʶ ˗˂˖ʶ ˘ ˥˂˪ʶ ˖˦ʶ ˗˂˖ʶ ˥˗ʶ ˪˥ʶ ˖˦ʶ ˗˂˖ʶ ˘ ˥˂˪ʶ ˖˦ʶ ˗˂˖ʶ ˥˗ʶ ˪˥ʶ ˖˦ʶ ˗˂˖ʶ ˘ ˥˂˪ʶ ˖˦ʶ ˗˂˖ʶ ˖˦ʶ ˗˂˖ʶ Tie Low ˥˘˦ʶ ˥˘˦ʶ ˥˘˦ʶ ˥˘˦ʶ ˥˘˦ʶ ˥˘˦ʶ ˥˘˦ʶ ˥˘˦ʶ 6800-series Parallel Interface A low in R/W# indicates WRITE operation and high in R/W# indicates READ operation. A low in D/C# indicates COMMAND read/write and high in D/C# indicates DATA read/write. The E input serves as data latch signal while CS# is low. Data is latched at the falling edge of E signal. Table 5 - Control pins of 6800 interface Function E R/W# CS# D/C# Write command ↓ L L L Read status ↓ H L L Write data ↓ L L H Read data ↓ H L H Note (1) Ļ stands for falling edge of signal (2) H stands for high in signal (3) L stands for low in signal In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 4. SSD1331 Rev 0.13 P 15/64 Mar 2006 Solomon Systech Figure 4 - Display data read back procedure - insertion of dummy read R/W# E N Databus Write column address 7.1.2 Dummy read n n+1 n+2 Read 1st data Read 2nd data Read 3rd data 8080-series Parallel Interface A low in D/C# indicates COMMAND read/write and high in D/C# indicates DATA read/write. A rising edge of RD# input serves as a data READ latch signal while CS# is kept low. A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept low. Table 6 - Control pins of 8080 interface Function Write command Read status Write data Read data RD# H ↑ H ↑ WR# ↑ H ↑ H CS# L L L L D/C# L L H H Note (1) Ĺ stands for rising edge of signal (2) H stands for high in signal (3) L stands for low in signal In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 6. Figure 5 - Display data read back procedure - insertion of dummy read WR# RD# Databus N Write column address Solomon Systech Dummy read n n+1 Read 1st data Read 2nd data Mar 2006 P 16/64 n+2 Rev 0.13 Read 3rd data SSD1331 Alternatively, E(RD#) and R/W#(WR#) can be keep stable while CS# is serve as the data/command latch signal. Table 7 - Control pins of 8080 interface (Alternative form) Function Write command Read status Write data Read data RD# H L H L WR# L H L H CS# ↑ ↑ ↑ ↑ D/C# L L H H Note (1) Ĺ stands for rising edge of signal (2) H stands for high in signal (3) L stands for low in signal 7.1.3 Serial Interface The serial interface consists of serial clock SCLK (D0), serial data SDIN (D1), D/C# and CS#. SCLK is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6… D0. D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or command register in the same clock. Under serial mode, only write operations are allowed. Table 8 - Control pins of Serial interface Function Write command Write data E Tie low Tie low R/W# Tie low Tie low CS# L L D/C# L H Figure 6 - Write procedure in SPI mode CS# D/C# SDIN/ SCLK DB1 DB2 DBn SCLK(D0) SDIN(D1) SSD1331 D7 D6 D5 Rev 0.13 P 17/64 Mar 2006 D4 D3 D2 D1 D0 Solomon Systech 7.2 Command Decoder This module determines whether the input should be interpreted as data or command based upon the input of the D/C# pin. If D/C# pin is high, data is written to Graphic Display Data RAM (GDDRAM). If it is low, the inputs at D0-D15 are interpreted as a Command and it will be decoded and be written to the corresponding command register. 7.3 7.3.1 Oscillator Circuit and Display Time Generator Oscillator Internal Oscillator Fosc CL M U X CLK DCLK Divider Display Clock CLS Figure 7 - Oscillator Circuit This module is an On-Chip low power RC oscillator circuitry (Figure 7). The operation clock (CLK) can be generated either from internal oscillator or external source CL pin by CLS pin. If CLS pin is high, internal oscillator is selected. If CLS pin is low, external clock from CL pin will be used for CLK. The frequency of internal oscillator FOSC can be programmed by command B3h (Set oscillator frequency). The display clock (DCLK) for the Display Timing Generator is derived from CLK. The division factor “D” can be programmed from 1 to 16 by command B3h. DCLK = FOSC / D The frame frequency of display is determined by the following formula. FFRM = Fosc D × K × No. of Mux where • D stands for clock divide ratio. It is set by command B3h A[3:0]. The divide ratio has the range from 1 to 16. • K is the number of display clocks per row. The value is derived by K = Phase 1 period + Phase 2 period + PW63 (longest current drive pulse width) = 4 + 7 + 125 = 136 at power on reset • Number of multiplex ratio is set by command A8h. The power on reset value is 64 • FOSC is the oscillator frequency. It can be adjusted by command B3h A[7:4] If the frame frequency is set too low, display flickering may occur. On the other hand, higher frame frequency leads to higher power consumption on the whole system. In normal application, it’s suggested to set the frame frequency between 100Hz and 110Hz. Solomon Systech Mar 2006 P 18/64 Rev 0.13 SSD1331 7.3.2 FR synchronization FR synchronization signal can be used to prevent tearing effect. One frame FR 100% Memory Access Process 0% Time Fast write MCU Slow write MCU SSD1331 displaying memory updates to OLED screen The starting time to write a new image to OLED driver is depended on the MCU writing speed. If MCU can finish writing a frame image within one frame period, it is classified as fast write MCU. For MCU needs longer writing time to complete(more than one frame but within two frames), it is a slow write one. For fast write MCU: MCU should start to write new frame of ram data just after rising edge of FR pulse and should be finished well before the rising edge of the next FR pulse. For slow write MCU: MCU should start to write new frame ram data after the falling edge of the 1st FR pulse and must be finished before the rising edge of the 3rd FR pulse. 7.4 Reset Circuit When RES# input is pulled low, the chip is initialized with the following status: 1. Display is OFF 2. 64 MUX Display Mode 3. Display start line is set at display RAM address 0 4. Display offset set to 0 5. Normal segment and display data column address and row address mapping (SEG0 mapped to address 00H and COM0 mapped to address 00H) 6. Column address counter is set at 0 7. Master contrast control register is set at 0FH 8. Individual contrast control registers of color A, B, and C are set at 80H 9. Shift register data clear in serial interface 10. Normal display mode (Equivalent to A4 command) SSD1331 Rev 0.13 P 19/64 Mar 2006 Solomon Systech 7.5 Graphic Display Data RAM (GDDRAM) 7.5.1 GDDRAM structure The GDDRAM is a bit mapped static RAM holding the pattern to be displayed. The RAM size is 96 x 64 x 16bits. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software. For vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the RAM data to be mapped to the display. Each pixel has 16-bit data. Three sub-pixels for color A, B and C have 6 bits, 5 bits and 6 bits respectively. The arrangement of data pixel in graphic display data RAM is shown below. Figure 8 - 65k Color Depth Graphic Display Data RAM Structure Column Address Normal 0 1 2 : 93 94 Remap 95 B5 B4 B3 B2 B1 B0 94 B5 B4 B3 B2 B1 B0 93 B5 B4 B3 B2 B1 B0 : 2 B5 B4 B3 B2 B1 B0 1 B5 B4 B3 B2 B1 B0 A4 A3 A2 A1 A0 Data Format Row Address Normal Remap 0 63 1 2 62 61 : : 61 2 62 63 1 0 SEG OUTPUT 7.5.2 C4 C3 C2 C1 C0 A4 A3 A2 A1 A0 C4 C3 C2 C1 C0 A4 A3 A2 A1 A0 C4 C3 C2 C1 C0 A4 A3 A2 A1 A0 : C4 C3 C2 C1 C0 A4 A3 A2 A1 A0 95 C4 C3 C2 C1 C0 A4 A3 A2 A1 A0 0 B5 B4 B3 B2 B1 B0 C4 C3 C2 C1 C0 COM OUTPUT 5 6 5 5 6 5 5 6 5 5 6 5 5 6 5 5 6 5 COM0 : COM1 COM2 : no. of bits of data in this cell COM61 : SA0 SB0 SC0 SA1 SB1 SC1 SA2 SB2 SC2 COM62 COM63 : SA93 SB93 SC93 SA94 SB94 SC94 SA95 SB95 SC95 Data bus to RAM mapping under different input mode Table 9 - Data bus usage under different bus width and color depth mode Data bus Bus width Color Depth Input order D15 D14 D13 D12 D11 D10 8 bits 256 8 bits 65k format 1 8 bits 65k format 2 16 bits 65k 9 bits 65k Solomon Systech 1st D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X C4 C3 C2 B5 B4 B3 A4 A3 X X X X X X X X C4 C3 C2 C1 C0 B5 B4 B3 2nd X X X X X X X X B2 B1 B0 A4 A3 A2 A1 A0 1st X X X X X X X X X X C4 C3 C2 C1 C0 X 2nd X X X X X X X X X X B5 B4 B3 B2 B1 B0 3rd X X X X X X X X X X A4 A3 A2 A1 A0 X C4 C3 C2 C1 C0 B5 B4 B3 B2 B1 B0 A4 A3 A2 A1 A0 1st X X X X X X X C4 C3 C2 C1 C0 X B5 B4 B3 2nd X X X X X X X B2 B1 B0 A4 A3 A2 A1 A0 X Mar 2006 P 20/64 Rev 0.13 SSD1331 7.5.3 RAM mapping and Different color depth mode At 65k color depth mode, color A, B, C are directly mapped to the RAM content. At 256-color mode, the RAM content will be filled up to 65k format. Figure 9 - 256-color mode mapping SCn SBn SAn 65k color C4 C3 C2 C1 C0 B5 B4 B3 B2 B1 B0 A4 A3 A2 A1 A0 256 color C4 C3 C2 *C4 *C4 B5 B4 B3 B5 *B5 *B5 A4 A3 *A4 *A4 *A4 Note: (1) n = 0 ~ 95 (2) bits with * are copied from corresponding bits in order to fill up 65K format. 7.6 Gray Scale Decoder The gray scale effect is generated by controlling the pulse width of segment drivers in current drive phase. The gray scale table stores the corresponding pulse widths of the 63 gray scale levels (GS0~GS63). The wider the pulse width, the brighter the pixel will be. A single gray scale table supports all the three colors A, B and C. The pulse widths can be set by software commands. As shown in Figure 10, color B sub-pixel RAM data has 6 bits, represent the 64 gray scale levels from GS0 to GS63. color A and color C sub-pixel RAM data has only 5 bits, represent 32 gray scale levels from GS0, GS2, …, GS62. Figure 10 - Relation between GDRAM content and gray scale table entry for three colors in 65K color mode Color A, C RAM data (5 bits) 00000 00001 00010 : : : 11110 11111 - Color B RAM data (6 bits) 000000 000001 000010 000011 000100 : : : 111100 111101 111110 111111 Gray Scale GS0 GS1 GS2 GS3 GS4 : : : GS60 GS61 GS62 GS63 Default pulse width of GS[0:63] in terms of DCLK 0 1 3 5 7 : : : 119 121 123 125 The duration of different GS are programmable. SSD1331 Rev 0.13 P 21/64 Mar 2006 Solomon Systech Figure 11 - Illustration of relation between graphic display RAM value and gray scale control Gray scale table Gray Scale GS0 GS1 GS2 : GS62 GS63 Segment Voltage Value/DCLKs 0 1 3 : 123 125 Color B RAM data = 000001 GS1 pulse width = 1 DCLKs Color B RAM data = 111111 GS63 pulse width = 125 DCLKs VP VLSS Time Segment Voltage Color A RAM data = 00001 GS2 pulse width = 3 DCLKs Color A RAM data = 11111 GS62 pulse width = 123 DCLKs VP VLSS Time Solomon Systech Mar 2006 P 22/64 Rev 0.13 SSD1331 7.7 SEG / COM Driving block This block is used to derive the incoming power sources into the different levels of internal use voltage and current. • VCC is the most positive voltage supply. • VCOMH is the Common deselected level. It is internally regulated. • VLSS is the ground path of the analog and panel current. • IREF is a reference current source for segment current drivers ISEG. The relationship between reference current and segment current of a color is: ISEG = Contrast / 256 x IREF x scale factor in which the contrast (0~255) is set by Set Contrast command; and the scale factor (1 ~ 16) is set by Master Current Control command. For example, in order to achieve ISEG = 160uA at maximum contrast 255, IREF is set to around 10uA. This current value is obtained by connecting an appropriate resistor from IREF pin to VSS as shown in Figure 12. Recommended range for IREF = 10uA +/- 2uA SSD1331 IREF (voltage at this pin = VCC – 3) IREF ≈ 10uA R1 VSS Figure 12 - IREF Current Setting by Resistor Value Since the voltage at IREF pin is VCC – 3V, the value of resistor R1 can be found as below. R1 = (Voltage at IREF – VSS) / IREF = (VCC – 3) / 10uA ≈ 1.3MΩ for VCC = 16V. Figure 13 - ISEG current vs VCC setting at constant IREF, Contrast = FFh ISEG (uA) Typical ISEG current vs VCC (IREF = 10uA, Contrast = FFh) 210 200 190 180 170 160 150 140 7 SSD1331 9 Rev 0.13 11 P 23/64 VCC (V) Mar 2006 13 15 17 19 Solomon Systech 7.8 Common and Segment Drivers Segment drivers consist of 288 (96 x 3 colors) current sources to drive OLED panel. The driving current can be adjusted from 0 to 160uA with 256 steps by contrast setting command (81h,82h,83h). Common drivers generate scanning voltage pulse. The block diagrams and waveforms of the segment and common driver are shown as follow. Figure 14 - Segment and Common Driver Block Diagram VCC ISEG VCOMH Current Drive Non-select Row Reset OLED Pixel Selected Row VLSS VLSS Segment Driver Common Driver The commons are scanned sequentially, row by row. If a row is not selected, all the pixels on the row are in reverse bias by driving those commons to voltage VCOMH as shown in Figure 15 In the scanned row, the pixels on the row will be turned ON or OFF by sending the corresponding data signal to the segment pins. If the pixel is turned OFF, the segment current is kept at 0. On the other hand, the segment drives to ISEG when the pixel is turned ON. Solomon Systech Mar 2006 P 24/64 Rev 0.13 SSD1331 Figure 15 - Segment and Common Driver Signal Waveform One Frame Period Non-select Row COM0 VCOMH VLSS Selected Row COM1 VCOMH VLSS COM Voltage This row is selected to turn on VCOMH VLSS Time Segment Voltage Waveform for ON VP Waveform for OFF VLSS Time SSD1331 Rev 0.13 P 25/64 Mar 2006 Solomon Systech There are four phases to driving an OLED a pixel. In phase 1, the pixel is reset by the segment driver to VLSS in order to discharge the previous data charge stored in the parasitic capacitance along the segment electrode. The period of phase 1 can be programmed by command B1h A[3:0] from 1 to 16 DCLK. An OLED panel with larger capacitance requires a longer period for discharging. In phase 2, first pre-charge is performed. The pixel is driven to attain the corresponding voltage level VP from VLSS. The amplitude of VP can be programmed by the command BBh. The period of phase 2 can be programmed in length from 1 to 16 DCLK by command B1h A[7:4]. If the capacitance value of the pixel of OLED panel is larger, a longer period is required to charge up the capacitor to reach the desired voltage. In phase 3, the OLED pixel is driven to the targeted driving voltage through second pre-charge. The second pre-charge can control the speed of the charging process. The period of phase 3 can be programmed by commands 8Ah, 8Bh and 8Ch. Last phase (phase 4) is current drive stage. The current source in the segment driver delivers constant current to the pixel. The driver IC employs Pulse Width Modulation (PWM) method to control the gray scale of each pixel individually. The wider pulse widths in the current drive stage results in brighter pixels and vice versa. This is shown in the following figure. Figure 16 - Gray Scale Control by PWM in Segment Phase2 Phase1 Phase4 Phase3 Segment Voltage VP VLSS Time Wider pulse width drives pixel brighter OLED Panel After finishing phase 4, the driver IC will go back to phase 1 to display the next row image data. This four-step cycle is run continuously to refresh image display on OLED panel. The length of phase 4 is defined by command B8h “Set Gray Scale Table” or B9h “Enable Linear Gray Scale Table”. In the table, the gray scale is defined in incremental way, with reference to the length of previous table entry. Solomon Systech Mar 2006 P 26/64 Rev 0.13 SSD1331 7.9 Power ON and OFF sequence The following figures illustrate the recommended power ON and power OFF sequence of SSD1331 (assume VDD and VDDIO are at the same voltage level). Power ON sequence: 1. Power ON VDD, VDDIO. 2. After VDD, VDDIO become stable, set RES# pin LOW (logic low) for at least 3us (t1) and then HIGH (logic high). 3. After set RES# pin LOW (logic low), wait for at least 3us (t2). Then Power ON VCC.(1) 4. After VCC become stable, send command AFh for display ON. SEG/COM will be ON after 100ms (tAF). Figure 17 : The Power ON sequence ON VDD, VDDIO RES# ON VCC Send AFh command for Display ON VDD, VDDIO GND t1 RES# GND t2 VCC GND tAF ON SEG/COM OFF Power OFF sequence: 1. Send command AEh for display OFF. 2. Wait until panel discharges completely. 3. Power OFF VCC.(1), (2) 4. Wait for 100ms (tOFF). Power OFF VDD, VDDIO. Figure 18 : The Power OFF sequence Send command AEh for display OFFOFF VCC VCC OFF VDD ,VDDIO GND tOFF VDD ,VDDIO GND Note: (1) Since an ESD protection circuit is connected between VDD and VCC, VCC becomes lower than VDD whenever VDD is ON and VCC is OFF as shown in the dotted line of VCC in Figure 18 and Figure 19. (2) VCC should be kept float when it is OFF. SSD1331 Rev 0.13 P 27/64 Mar 2006 Solomon Systech 8 COMMAND TABLE Table 10 - Command Table Fundamental Commands D/C# Hex D7 D6 D5 D4 D3 D2 D1 D0 0 15 0 0 0 0 A[6:0] B[6:0] * * A6 A5 A4 A3 A2 A1 A0 B6 B5 B4 B3 B2 B1 B0 0 1 0 1 0 Command 1 Description Default Setup Column start and end address A[6:0] start address from 00d-95d 00d (00h) B[6:0] end address from 00d-95d 95d (5Fh) Set Column Address 0 0 75 A[5:0] 0 * 1 1 1 0 1 0 1 * A5 A4 A3 A2 A1 A0 Setup Row start and end address A[5:0] start address from 00d-63d 00d (00h) 0 B[5:0] * * B[5:0] end address from 00d-63d 63d (3Fh) Set contrast for all color "A" segment (Pins:SA0 – SA95) A[7:0] valid range: 00d to 255d 128d (80h) Set contrast for all color "B" segment (Pins:SB0 – SB95). A[7:0] valid range: 00d to 255d 128d (80h) Set contrast for all color "C" segment (Pins:SC0 – SC95). A[7:0] valid range: 00d to 255d 128d (80h) B5 B4 B3 B2 B1 B0 Set Row Address 0 0 81 1 0 0 0 0 0 0 1 A[7:0] A7 A6 A5 A4 A3 A2 A1 A0 Set Contrast for Color "A" 0 0 82 1 0 0 0 0 0 1 0 A[7:0] A7 A6 A5 A4 A3 A2 A1 A0 Set Contrast for Color "B" 0 0 83 1 0 0 0 0 0 1 1 A[7:0] A7 A6 A5 A4 A3 A2 A1 A0 Set Contrast for Color "C" 0 87 1 0 0 0 0 A[3:0] 0 0 0 0 A3 A2 A1 A0 0 1 1 Set master current attenuation factor A[3:0] from 00d to 15d corresponding to 1/16, 2/16… to 16/16 attenuation. 1 15d (0Fh) Master Current Control Solomon Systech Mar 2006 P 28/64 Rev 0.13 SSD1331 Fundamental Commands D/C# Hex 0 8A 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 0 1 Command 0 8B 1 0 0 0 1 0 1 A0 1 0 1 0 0 0 0 Default A[7:0] of 81h A[7:0]: Set Second Pre-charge Speed Ranges: 0000000b to 1111111b, a higher value of A[7:0] gives a higher Second A[7:0] of 82h Pre-charge speed. A[7:0] A7 A6 A5 A4 A3 A2 A1 A0 1 A[7:0] A7 A6 A5 A4 A3 A2 A1 A0 8C 1 0 0 0 1 1 0 0 A[7:0] A7 A6 A5 A4 A3 A2 A1 A0 Description A[7:0] of 83h Note (1) The default values of A[7:0] in 8Ah, A[7:0] in 8Bh and A[7:0] in 8Ch are equal to the contrast values for color A, B and C( refer to commands: 81h, 82h, 83h) respectively. Set Second (2) All six bytes (8Ah A[7:0], 8Bh A[7:0] and Pre-charge 8Ch A[7:0]) must be inputted together. For Speed for example: the original value is like that Color “A”, “B” Original value and “C” 8Ah A[7:0]: 80h 8Bh A[7:0]: 80h 8Ch A[7:0]: 80h If it is wanted to change the value of 8Bh A[7:0] to 75h, then all the following 6 bytes must be inputted: 8Ah,80h, 8Bh,75h, 8Ch,80h. 0 Set driver remap and color depth A[7:0] A7 A6 A5 A4 A3 A2 A1 A0 A[0]=0, Horizontal address increment A[0]=0 A[0]=1, Vertical address increment A[1]=0, RAM Column 0 to 95 maps to Pin Seg (SA,SB,SC) 0 to 95 A[1]=1, RAM Column 0 to 95 maps to Pin Seg (SA,SB,SC) 95 to 0 A[1]=0 A[2]=0, normal order SA,SB,SC (e.g. RGB) A[2]=0 A[2]=1, reverse order SC,SB,SA (e.g. BGR) A[3]=0, Disable left-right swapping on COM A[3]=0 Remap & Color A[3]=1, Set left-right swapping on COM Depth setting A[4]=0, Scan from COM 0 to COM [N –1] A[4]=1, Scan from COM [N-1] to COM0. Where N is the multiplex ratio. A[4]=0 A[5]=0, Disable COM Split Odd Even (RESET) A[5]=1, Enable COM Split Odd Even A[5]=0 A[7:6] = 00; 256 color format A[7:6] = 01; 65k color format A[7:6]=01 A[7:6] = 10; 65k color format 2 If 9 / 18 bit mode is selected, color depth will be fixed to 65k regardless of the setting. 0 0 A1 A[5:0] 1 0 0 1 0 0 0 0 1 0 A5 A4 A3 A2 A1 A0 0 A2 1 0 0 A[5:0] 0 0 A5 A4 A3 A2 A1 A0 SSD1331 1 0 Rev 0.13 0 0 P 29/64 1 Set Display Start Line 0 Set display start line register by Row A[5:0]: from 00d to 63d 00d (00h) Set vertical offset by Com Set Display Offset Mar 2006 A[5:0]: from 00d to 63d 00d (00h) Solomon Systech Fundamental Commands D/C# Hex 0 A4 / 0 A5 / 0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 0 Command 1 X1 X0 Set Display Mode A6 / A7 / 0 A8 1 0 0 A[5:0] 0 0 A5 A4 A3 A2 A1 A0 1 0 1 0 0 0 0 AD 1 0 1 0 1 1 0 0 A[7:0] 1 0 0 0 1 1 1 A0 Description Default A4h=Normal Display A4h A5h=Entire Display On, all pixels turn on at GS63 A6h=Entire Display Off, all pixels turn off A7h=Inverse Display Set MUX ratio to N+1 Mux Set Multiplex N = A[5:0] from 15d to 63d Ratio A[5:0] from 00d to 14d are invalid entry A[0]=0b, Select external VCC supply A[0]=1b, Reserved (RESET) 1 Set Master Note Configuration (1) Bit A[0] must be set to 0b after RESET. (2) The setting will be activated after issuing Set Display ON command (AFh) 0 AE 1 0 1 0 1 1 1 A0 0 0 0 0 0 B0 1 0 1 1 0 0 0 0 A[7:0] A7 A6 A5 A4 A3 A2 A1 A0 B1 1 0 1 1 0 0 0 1 A[7:0] A7 A6 A5 A4 A3 A2 A1 A0 B3 1 0 1 1 0 0 1 1 0 A[7:0] A7 A6 A5 A4 A3 A2 A1 A0 0 0 B8 A[6:0] 1 0 1 1 1 0 0 0 * A6 A5 A4 A3 A2 A1 A0 0 B[6:0] * 0 0 C[6:0] * … ... 0 AE[6:0] * 0 AF[6:0] * A[0] = 1 AEh = Display off (sleep mode) Set Display On/Off AF 63d (3Fh) AFh = Display on in normal mode AEh A[7:0]=1Ah, Enable power save mode (RESET) 1Ah Power Save Other setting = TBD Mode A[3:0] Phase 1 period in N DCLK. 1~15 DCLK allowed. Phase 1 and 2 A[7:4] Phase 2 period in N DCLK. 1~15 period adjustment DCLK allowed A[3:0]: Define the divide ratio (D) of the 74h D0h display clocks (DCLK): Display Clock Divide ratio (D) = A[3:0] + 1 (i.e., 1 to 16) Divider / A[7:4] Fosc frequency. Oscillator Frequency Frequency increases as setting value increases These 32 parameters define pulse widths of GS1 to GS63 in terms of DCLK A[6:0]: Pulse width for GS1, RESET=01d B6 B5 B4 B3 B2 B1 B0 B[6:0]: Pulse width for GS3, RESET=05d C6 C5 C4 C3 C2 C1 C0 C[6:0]: Pulse width for GS5, RESET=09d … … … … … … … … AE[6:0]: Pulse width for GS61, RESET=121d AE6 AE5 AE4 AE3 AE2 AE1 AE0 AF[6:0]: Pulse width for GS63, RESET=125d AF6 AF5 AF4 AF3 AF2 AF1 AF0 Set Gray Scale Note: (1) GS0 has no pre-charge and current drive Table stages. (2) GS2, GS4…GS62 are derived by Pn = (Pn-1+Pn+1)/2 (3) Pn will be truncated to integer if it is with decimal point. (4) Pn+1 should always be set to larger than Pn-1 (5) Max pulse width is 125 Solomon Systech Mar 2006 P 30/64 Rev 0.13 SSD1331 Fundamental Commands D/C# Hex 0 B9 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1 0 0 Command 1 Description Default Reset built in gray scale table (Linear) Pulse width for GS1 = 1d; Pulse width for GS2 = 3d; Enable Linear Pulse width for GS3 = 5d; Gray Scale … Table Pulse width for GS61 = 121d; Pulse width for GS62 = 123d; Pulse width for GS63 = 125d. 0 BB 1 0 1 1 1 0 1 1 Set pre-charge voltage level. All three color share the same pre-charge voltage. 0 A[5:1] Hex code pre-charge voltage 0.10 x VCC Set Pre-charge 00000 00h : : : level 11111 3Eh 0.50 x VCC Refer to Figure 28 for the details setting of 0 A[5:0] 0 0 A5 A4 A3 A2 A1 0 BC-BD 1 0 1 1 1 1 0 X0 BE 1 0 1 1 1 1 1 0 A[5:1] 0 0 A5 A4 A3 A2 A1 0 3Eh A[5:1]. NOP 0 Set COM deselect voltage level (V COMH) Set VCOMH 0 E3 1 1 1 0 0 0 1 1 1 0 FD 1 1 1 1 1 0 1 0 A[2] 0 0 0 1 0 A2 1 0 Command for No operation NOP A[5:1] 00000 01000 10000 11000 11111 Hex code 00h 10h 20h 30h 3Eh 3Eh V COMH 0.44 x VCC 0.52 x VCC 0.61 x VCC 0.71 x VCC 0.83 x VCC Command for No operation A[2]: MCU protection status A[2] = 0b, Unlock OLED driver IC MCU interface from entering command [reset] 12h A[2] = 1b, Lock OLED driver IC MCU Set Command interface from entering command Lock Note (1) The locked OLED driver IC MCU interface prohibits all commands and memory access except the FDh command. SSD1331 Rev 0.13 P 31/64 Mar 2006 Solomon Systech Graphic Acceleration Commands D/C# Hex D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 Command 1 Description 0 21 0 0 0 A[6:0] * A6 A5 A4 A3 A2 A1 A0 B[5:0]: Row Address of Start 0 B[5:0] * * C[6:0]: Column Address of End 0 C[6:0] * C6 C5 C4 C3 C2 C1 C0 0 D[5:0] * * D5 D4 D3 D2 D1 D0 0 E[5:1] * * E5 E4 E3 E2 E1 * F[5:0]: Color B of the line 0 F[5:0] * * F 5 F4 F3 F2 F1 F0 G[5:1]: Color A of the line 0 G[5:1] * * G 5 G4 G3 G2 G1 * A[6:0]: Column Address of Start B5 B4 B3 B2 B1 B0 0 22 0 0 0 A[6:0] * A6 A5 A4 A3 A2 A1 A0 0 B[5:0] * 0 C[6:0] * 0 D[5:0] * * 1 0 0 0 1 Draw Line 0 A[6:0]: Column Address of Start B[5:0]: Row Address of Start B5 B4 B3 B2 B1 B0 C[6:0]: Column Address of End D[5:0]: Row Address of End D5 D4 D3 D2 D1 D0 E[5:1]: Color C of the line Drawing Rectangle 0 E[5:1] * * E5 E4 E3 E2 E1 0 F[5:0] * * F 5 F4 F3 F2 F1 F0 0 G[5:1] * * G 5 G4 G3 G2 G1 * H[5:1]: Color C of the fill area 0 H[5:1] * * H5 H4 H3 H2 H1 * I[5:0]: Color B of the fill area J[5:1]: Color A of the fill area 0 I[5:0] * * I5 I1 I0 0 J[5:1] * * J5 J4 J3 J2 J1 * 0 23 0 0 1 1 A6 A5 A4 A3 A2 A1 A0 0 A[6:0] * 0 B[5:0] * * I4 0 I3 0 I2 * D[5:0]: Row Address of End E[5:1]: Color C of the line C6 C5 C4 C3 C2 C1 C0 * 0 1 C[6:0] * 0 D[5:0] * 0 E[6:0] * 0 F[5:0] * * F 5 F4 F3 F2 F1 F0 0 24 0 0 1 A6 A5 A4 A3 A2 A1 A0 0 A[6:0] * 0 B[5:0] * 0 C[6:0] * 0 D[5:0] * C6 C5 C4 C3 C2 C1 C0 A[6:0]: Column Address of Start B[5:0]: Row Address of Start C[6:0]: Column Address of End Copy D5 D4 D3 D2 D1 D0 * 0 1 0 F[5:0]: Row Address of New Start 0 A[6:0]: Column Address of Start B[5:0]: Row Address of Start B5 B4 B3 B2 B1 B0 C[6:0]: Column Address of End C6 C5 C4 C3 C2 C1 C0 * D5 D4 D3 D2 D1 D0 D[5:0]: Row Address of End E[6:0]: Column Address of New Start E6 E5 E4 E3 E2 E1 E0 0 F[5:0]: Color B of the line G[5:1]: Color A of the line B5 B4 B3 B2 B1 B0 0 * Default D[5:0]: Row Address of End Dim Window The effect of dim window: GS15~GS0 no change GS19~GS16 become GS4 GS23~GS20 become GS5 ... GS63~GS60 become GS15 0 25 0 0 A6 A5 A4 A3 A2 A1 A0 0 A[6:0] * 0 B[5:0] * * 1 0 0 1 0 1 A[6:0]: Column Address of Start B[5:0]: Row Address of Start B5 B4 B3 B2 B1 B0 Clear Window C[6:0]: Column Address of End 0 C[6:0] * 0 D[5:0] * C6 C5 C4 C3 C2 C1 C0 * D5 D4 D3 D2 D1 D0 0 26 0 0 1 0 0 1 1 0 A[4:0] * * * A4 0 0 0 A0 D[5:0]: Row Address of End 0 Fill Enable / Disable A0 0 : Disable Fill for Draw Rectangle Command (RESET) 1 : Enable Fill for Draw Rectangle Command A[3:1] 000: Reserved values A4 0 : Disable reverse copy (RESET) 1 : Enable reverse during copy command. Solomon Systech Mar 2006 P 32/64 Rev 0.13 SSD1331 Graphic Acceleration Commands D/C# Hex 0 27 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 A[6:0] * A6 A5 A4 A3 A2 A1 A0 0 B[5:0] * 0 C[6:0] * 0 D[5:0] * * 0 E[1:0] * * * 1 0 0 1 1 Command 1 Description Default A[6:0]: Set number of column as horizontal scroll offset Range: 0d-95d ( no horizontal scroll if equals to 0) B[5:0]: Define start row address B5 B4 B3 B2 B1 B0 C6 C5 C4 C3 C2 C1 C0 D5 D4 D3 D2 D1 * * * * E1 C[6:0]: Set number of rows to be horizontal scrolled B[5:0]+C[6:0] <=64 D0 D[5:0]: Set number of row as vertical scroll Continuous offset Horizontal & Range: 0d-63d ( no vertical scroll if Vertical equals to 0) Scrolling Setup E[1:0]: Set time interval between each scroll E0 step 00b 6 frames 01b 10 frames 10b 100 frames 11b 200 frames Note: Vertical scroll is run with 64MUX setting only Stop scrolling (1) 0 2E 0 0 1 0 1 1 1 0 0 2F 0 0 1 0 1 1 1 1 SSD1331 Rev 0.13 P 33/64 Mar 2006 Deactivate scrolling Activate scrolling Start scrolling Solomon Systech 8.1 Data Read / Write To read data from the GDDRAM, input HIGH to R/W#(WR#)# pin and D/C# pin for 6800-series parallel mode, LOW to E (RD#) pin and HIGH to D/C# pin for 8080-series parallel mode. No data read is provided in serial mode operation. In normal data read mode, GDDRAM column address pointer will be increased by one automatically after each data read. Also, a dummy read is required before the first data read. To write data to the GDDRAM, input LOW to R/W#(WR#) pin and HIGH to D/C# pin for 6800-series parallel mode AND 8080-series parallel mode. For serial interface mode, it is always in write mode. GDDRAM column address pointer will be increased by one automatically after each data write. Table 11 - Address increment table (Automatic) D/C# R/W#(WR#) Comment Address Increment 0 0 1 1 0 1 0 1 Write Command Read Status Write Data Read Data No No Yes Yes Solomon Systech Mar 2006 P 34/64 Rev 0.13 SSD1331 9 9.1 COMMAND DESCRIPTIONS Fundamental Command 9.1.1 Set Column Address (15h) This command specifies column start address and end address of the display data RAM. This command also sets the column address pointer to column start address. This pointer is used to define the current read/write column address in graphic display data RAM. If horizontal address increment mode is enabled by command A0h, after finishing read/write one column data, it is incremented automatically to the next column address. Whenever the column address pointer finishes accessing the end column address, it is reset back to start column address. 9.1.2 Set Row Address (75h) This command specifies row start address and end address of the display data RAM. This command also sets the row address pointer to row start address. This pointer is used to define the current read/write row address in graphic display data RAM. If vertical address increment mode is enabled by command A0h, after finishing read/write one row data, it is incremented automatically to the next row address. Whenever the row address pointer finishes accessing the end row address, it is reset back to start row address. The figure below shows the way of column and row address pointer movement through the example: column start address is set to 2 and column end address is set to 93, row start address is set to 1 and row end address is set to 62. Horizontal address increment mode is enabled by command A0h. In this case, the graphic display data RAM column accessible range is from column 2 to column 93 and from row 1 to row 62 only. In addition, the column address pointer is set to 2 and row address pointer is set to 1. After finishing read/write one pixel of data, the column address is increased automatically by 1 to access the next RAM location for next read/write operation (solid line in Figure 19). Whenever the column address pointer finishes accessing the end column 93, it is reset back to column 2 and row address is automatically increased by 1 (solid line in Figure 19). While the end row 62 and end column 93 RAM location is accessed, the row address is reset back to 1 (dotted line in Figure 19). Col 0 Col 1 Col 2 ….. ……. Col 93 Col 94 Col 95 Row 0 Row 1 Row 2 : : : : : : Row 61 Row 62 Row 63 Figure 19 - Example of Column and Row Address Pointer Movement SSD1331 Rev 0.13 P 35/64 Mar 2006 Solomon Systech 9.1.3 Set Contrast for Color A, B, C (81h, 82h, 83h) This command is to set Contrast Setting of each color A, B and C. The chip has three contrast control circuits for color A, B and C. Each contrast circuit has 256 contrast steps from 00h to FFh. The segment output current ISEG increases linearly with the contrast step, which results in brighter of the color. This relation is shown in Figure 20. 9.1.4 Master Current Control (87h) This command is to control the segment output current by a scaling factor. This factor is common to color A, B and C. The chip has 16 master control steps. The factor is ranged from 1 [0000b] to 16 [1111b]. RESET is 16 [1111b]. The smaller the master current value, the dimmer the OLED panel display is set. For example, if original segment output current of a color is 160uA at scale factor = 16, setting scale factor to 8 to reduce the current to 80uA. Please see Figure 20. Segment output current 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 Change contrast control moves along the contrast curve with constant slope ˃˃ ˃˙ ˄˙ ˅˙ ˆ˙ ˇ˙ ˈ˙ ˉ˙ ˊ˙ ˋ˙ ˌ˙ ˔˙ ˕˙ ˖˙ ˗˙ ˘˙ Change master current selects different l ˢ̈̇̃̈̇ʳ˶̈̅̅˸́̇ʳ˜̆˸˺ʳʻ̈˔ʼ Master current setting ˙˙ ˖̂́̇̅˴̆̇ʳ̆˸̇̇˼́˺ Figure 20 - Segment Output Current for Different Contrast Control and Master Current Setting Solomon Systech Mar 2006 P 36/64 Rev 0.13 SSD1331 9.1.5 Set Second Pre-charge Speed for Color A, B, C (8Ah) The value set should match with the contrast of the color A, B, C. An initial trial should be the value same as the contrast A, B, C. When faster speed is needed, higher value can be set and vice versa. Figure 21 shows the effect of setting second pre-charge under different speeds through using command 8Ah, 8Bh and 8Ch. Figure 21 - Effect of setting the second pre-charge under different speeds Second Pre-charge speed = 255 Different settings in Second Pre-charge speed Phase2 Phase4 Phase1 Second Pre-charge speed = 1 ... Phase3 Segment Voltage VP VLSS Time 9.1.6 Set Re-map & Data Format (A0h) This command has multiple configurations and each bit setting is described as follows. • Address increment mode (A[0]) When it is set to 0, the driver is set as horizontal address increment mode. After the display RAM is read/written, the column address pointer is increased automatically by 1. If the column address pointer reaches column end address, the column address pointer is reset to column start address and row address pointer is increased by 1. The sequence of movement of the row and column address point for horizontal address increment mode is shown in Figure 22. Figure 22 - Address Pointer Movement of Horizontal Address Increment Mode Row 0 Row 1 : Row 62 Row 63 Col 0 Col 1 ….. Col 94 Col 95 : : : : : When A[0] is set to 1, the driver is set to vertical address increment mode. After the display RAM is read/written, the row address pointer is increased automatically by 1. If the row address pointer reaches the row end address, the row address pointer is reset to row start address and column address pointer is increased by 1. The sequence of movement of the row and column address point for vertical address increment mode is shown in Figure 23. Figure 23 - Address Pointer Movement of Vertical Address Increment Mode Col 0 Row 0 Row 1 : Row 62 Row 63 SSD1331 Rev 0.13 P 37/64 Mar 2006 Col 1 ….. ….. ….. : ….. ….. Col 94 Col 95 Solomon Systech • Column Address Mapping (A[1]) This command bit is made for flexible layout of segment signals in OLED module with segment arranged from left to right or vice versa. The display direction is either mapping display data RAM column 0 to SEG0 pin (A[1] = 0), or mapping display data RAM column 95 to SEG0 pin (A[1] = 1). The effects of both are shown in Figure 24. Figure 24 - Example of Column Address Mapping ……………… SA0 SB0 SC0 SSD1331 ……………… SA95 SB95 SC95 Column 0 maps to SEG0 pin SA0 SB0 SC0 SSD1331 SA95 SB95 SC95 Column 95 maps to SEG0 pin • RGB Mapping (A[2]) This command bit is made for flexible layout of segment signals in OLED module to match filter design. • COM Left / Right Remap (A[3]) This command bit is made for flexible layout of common signals in OLED module with COM0 arranged on either left or right side. Details of pin arrangement can be found in Table 12 and Figure 25. • COM Scan Direction Remap (A[4]) This bit determines the scanning direction of the common for flexible layout of common signals in OLED module either from up to down or vice versa. Details of pin arrangement can be found in Table 12 and Figure 25. • Odd Even Split of COM pins (A[5]) This bit can set the odd even arrangement of COM pins. A[5] = 0: Disable COM split odd even, pin assignment of common is in sequential as COM63 COM62 .... COM 33 COM32..SC95..SA0..COM0 COM1.... COM30 COM31 A[5] = 1: Enable COM split odd even, pin assignment of common is in odd even split as COM63 COM61.... COM3 COM1..SC95..SA0..COM0 COM2.... COM60 COM62 Details of pin arrangement can be found in Table 12 and Figure 25. • Display color mode (A[7:6]) Select either 65k or 256 color mode. The display RAM data format in different mode is described in section 7.5 Solomon Systech Mar 2006 P 38/64 Rev 0.13 SSD1331 Table 12 - Illustration of different COM output settings Case A Case B Case C Case D Case E Case F Case G Case H A[5:3]=000 A[5:3]=001 A[5:3]=010 A[5:3]=011 A[5:3]=100 A[5:3]=101 A[5:3]=110 A[5:3]=111 IC Pad no. Pin name Output signal 195 COM0 Row0 Row32 Row63 Row31 Row0 Row1 Row63 Row62 194 COM1 Row1 Row33 Row62 Row30 Row2 Row3 Row61 Row60 193 COM2 Row2 Row34 Row61 Row29 Row4 Row5 Row59 Row58 192 COM3 Row3 Row35 Row60 Row28 Row6 Row7 Row57 Row56 191 COM4 Row4 Row36 Row59 Row27 Row8 Row9 Row55 Row54 190 COM5 Row5 Row37 Row58 Row26 Row10 Row11 Row53 Row52 … … … … … … … … … … 169 COM26 Row26 Row58 Row37 Row5 Row52 Row53 Row11 Row10 168 COM27 Row27 Row59 Row36 Row4 Row54 Row55 Row9 Row8 167 COM28 Row28 Row60 Row35 Row3 Row56 Row57 Row7 Row6 166 COM29 Row29 Row61 Row34 Row2 Row58 Row59 Row5 Row4 165 COM30 Row30 Row62 Row33 Row1 Row60 Row61 Row3 Row2 164 COM31 Row31 Row63 Row32 Row0 Row62 Row63 Row1 Row0 488 COM32 Row32 Row0 Row31 Row63 Row1 Row0 Row62 Row63 489 COM33 Row33 Row1 Row30 Row62 Row3 Row2 Row60 Row61 490 COM34 Row34 Row2 Row29 Row61 Row5 Row4 Row58 Row59 491 COM35 Row35 Row3 Row28 Row60 Row7 Row6 Row56 Row57 492 COM36 Row36 Row4 Row27 Row59 Row9 Row8 Row54 Row55 493 COM37 Row37 Row5 Row26 Row58 Row11 Row10 Row52 Row53 … … … … … … … … … … 514 COM58 Row58 Row26 Row5 Row37 Row53 Row52 Row10 Row11 515 COM59 Row59 Row27 Row4 Row36 Row55 Row54 Row8 Row9 516 COM60 Row60 Row28 Row3 Row35 Row57 Row56 Row6 Row7 517 COM61 Row61 Row29 Row2 Row34 Row59 Row58 Row4 Row5 518 COM62 Row62 Row30 Row1 Row33 Row61 Row60 Row2 Row3 519 COM63 Row63 Row31 Row0 Row32 Row63 Row62 Row0 Row1 SSD1331 Rev 0.13 P 39/64 Mar 2006 Solomon Systech Figure 25 - COM Pins Hardware Configuration (MUX ratio: 64) Case and Conditions COM pins Configurations ROW63 A A[5] =0 A[4]=0 A[3]=0 Disable Odd COM Scan Disable COM Left ROW32 Even Split of Direction: from / Right Remap 96 x 64 COM pins COM0 to COM63 ROW31 ROW0 COM32 COM0 SSD1331Z COM63 COM31 Pad 1,2,3,…->163 Gold Bumps face up B ROW63 A[5] =0 Disable Odd Even Split of COM pins A[4]=0 A[3]=1 COM Scan Enable COM Left Direction: from / Right Remap COM0 to COM63 ROW31 ROW32 96 x 64 ROW0 COM0 COM32 SSD1331Z COM31 COM63 Pad 1,2,3,…->163 Gold Bumps face up ROW0 C A[5] =0 Disable Odd Even Split of COM pins A[4]=1 A[3]=0 COM Scan Disable COM Left Direction: from / Right Remap COM63 to COM0 ROW32 ROW31 96 x 64 ROW63 COM32 COM0 SSD1331Z COM63 COM31 Pad 1,2,3,…->163 Gold Bumps face up Solomon Systech Mar 2006 P 40/64 Rev 0.13 SSD1331 Case and Conditions COM pins Configurations D A[5] =0 A[4]=1 A[3]=1 Disable Odd COM Scan Enable COM Left ROW32 Even Split of Direction: from / Right Remap 96 x 64 COM pins COM63 to COM0 ROW0 ROW31 ROW63 COM0 COM32 SSD1331Z COM31 COM63 Pad 1,2,3,…->163 Gold Bumps face up E A[5] =1 A[4]=0 A[3]=0 Enable Odd Even COM Scan Disable COM Left Split of COM pins Direction: from / Right Remap COM0 to COM63 ROW63 ROW62 ROW61 96 x 64 ROW2 ROW1 ROW0 COM32 COM0 SSD1331Z COM62 COM1 COM31 COM63 Pad 1,2,3,…->163 Gold Bumps face up F ROW63 ROW62 A[5] =1 A[4]=0 A[3]=1 Enable Odd Even COM Scan Enable COM Left Split of COM pins Direction: from / Right Remap COM0 to COM63 ROW61 96 x 64 ROW2 ROW1 ROW0 COM32 COM33 COM0 SSD1331Z COM30 COM31 COM63 Pad 1,2,3,…->163 Gold Bumps face up SSD1331 Rev 0.13 P 41/64 Mar 2006 Solomon Systech Case and Conditions COM pins Configurations ROW0 G A[5] =1 A[4]=1 A[3]=0 ROW2 Enable Odd Even COM Scan Disable COM Left Split of COM pins Direction: from / Right Remap 96 x 64 COM63 to COM0 ROW1 ROW61 ROW62 ROW63 COM32 COM0 SSD1331Z COM62 COM1 COM31 COM63 Pad 1,2,3,…->163 Gold Bumps face up H ROW0 ROW1 A[5] =1 A[4]=1 A[3]=1 Enable Odd Even COM Scan Enable COM Left Split of COM pins Direction: from / Right Remap COM63 to COM0 ROW2 96 x 64 ROW61 ROW62 ROW63 COM32 COM33 COM0 SSD1331Z COM30 COM31 COM63 Pad 1,2,3,…->163 Gold Bumps face up 9.1.7 Set Display Start Line (A1h) This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 63. Table 13 and Table 14 show examples of this command. In there, “Row” means the graphic display data RAM row. 9.1.8 Set Display Offset (A2h) This command specifies the mapping of display start line (it is assumed that COM0 is the display start line, display start line register equals to 0) to one of COM0-63. For example, to move the COM16 towards the COM0 direction for 16 lines, the 6-bit data in the second command should be given by 0010000b. Table 13 and Table 14 show examples of this command. In there, “Row” means the graphic display data RAM row. Solomon Systech Mar 2006 P 42/64 Rev 0.13 SSD1331 Table 13 - Example of Set Display Offset and Display Start Line with no Remap Output Hardware pin name COM0 64 64 64 56 56 56 Set MUX ratio(A8h) 0 0 0 0 0 0 COM Scan Direction Remap (A0h A[4]) 0 8 0 0 8 0 Display offset (A2h) 0 0 8 0 0 8 Row0 RAM0 Row8 RAM8 Row0 RAM8 Row0 RAM0 Row8 RAM8 Row0 Display start line (A1h) RAM8 COM1 Row1 RAM1 Row9 RAM9 Row1 RAM9 Row1 RAM1 Row9 RAM9 Row1 RAM9 COM2 Row2 RAM2 Row10 RAM10 Row2 RAM10 Row2 RAM2 Row10 RAM10 Row2 RAM10 COM3 Row3 RAM3 Row11 RAM11 Row3 RAM11 Row3 RAM3 Row11 RAM11 Row3 RAM11 COM4 Row4 RAM4 Row12 RAM12 Row4 RAM12 Row4 RAM4 Row12 RAM12 Row4 RAM12 COM5 Row5 RAM5 Row13 RAM13 Row5 RAM13 Row5 RAM5 Row13 RAM13 Row5 RAM13 COM6 Row6 RAM6 Row14 RAM14 Row6 RAM14 Row6 RAM6 Row14 RAM14 Row6 RAM14 COM7 Row7 RAM7 Row15 RAM15 Row7 RAM15 Row7 RAM7 Row15 RAM15 Row7 RAM15 COM8 Row8 RAM8 Row16 RAM16 Row8 RAM16 Row8 RAM8 Row16 RAM16 Row8 COM9 Row9 RAM9 Row17 RAM17 Row9 RAM17 Row9 RAM9 Row17 RAM17 Row9 RAM17 COM10 Row10 RAM10 Row18 RAM18 Row10 RAM18 Row10 RAM10 Row18 RAM18 Row10 RAM18 COM11 Row11 RAM11 Row19 RAM19 Row11 RAM19 Row11 RAM11 Row19 RAM19 Row11 RAM19 COM12 Row12 RAM12 Row20 RAM20 Row12 RAM20 Row12 RAM12 Row20 RAM20 Row12 RAM20 COM13 Row13 RAM13 Row21 RAM21 Row13 RAM21 Row13 RAM13 Row21 RAM21 Row13 RAM21 COM14 Row14 RAM14 Row22 RAM22 Row14 RAM22 Row14 RAM14 Row22 RAM22 Row14 RAM22 COM15 Row15 RAM15 Row23 RAM23 Row15 RAM23 Row15 RAM15 Row23 RAM23 Row15 RAM23 COM16 Row16 RAM16 Row24 RAM24 Row16 RAM24 Row16 RAM16 Row24 RAM24 Row16 RAM24 COM17 Row17 RAM17 Row25 RAM25 Row17 RAM25 Row17 RAM17 Row25 RAM25 Row17 RAM25 COM18 Row18 RAM18 Row26 RAM26 Row18 RAM26 Row18 RAM18 Row26 RAM26 Row18 RAM26 COM19 Row19 RAM19 Row27 RAM27 Row19 RAM27 Row19 RAM19 Row27 RAM27 Row19 RAM27 COM20 Row20 RAM20 Row28 RAM28 Row20 RAM28 Row20 RAM20 Row28 RAM28 Row20 RAM28 COM21 Row21 RAM21 Row29 RAM29 Row21 RAM29 Row21 RAM21 Row29 RAM29 Row21 RAM29 COM22 Row22 RAM22 Row30 RAM30 Row22 RAM30 Row22 RAM22 Row30 RAM30 Row22 RAM30 COM23 Row23 RAM23 Row31 RAM31 Row23 RAM31 Row23 RAM23 Row31 RAM31 Row23 RAM31 COM24 Row24 RAM24 Row32 RAM32 Row24 RAM32 Row24 RAM24 Row32 RAM32 Row24 RAM32 COM25 Row25 RAM25 Row33 RAM33 Row25 RAM33 Row25 RAM25 Row33 RAM33 Row25 RAM33 COM26 Row26 RAM26 Row34 RAM34 Row26 RAM34 Row26 RAM26 Row34 RAM34 Row26 RAM34 COM27 Row27 RAM27 Row35 RAM35 Row27 RAM35 Row27 RAM27 Row35 RAM35 Row27 RAM35 COM28 Row28 RAM28 Row36 RAM36 Row28 RAM36 Row28 RAM28 Row36 RAM36 Row28 RAM36 COM29 Row29 RAM29 Row37 RAM37 Row29 RAM37 Row29 RAM29 Row37 RAM37 Row29 RAM37 COM30 Row30 RAM30 Row38 RAM38 Row30 RAM38 Row30 RAM30 Row38 RAM38 Row30 RAM38 COM31 Row31 RAM31 Row39 RAM39 Row31 RAM39 Row31 RAM31 Row39 RAM39 Row31 RAM39 COM32 Row32 RAM32 Row40 RAM40 Row32 RAM40 Row32 RAM32 Row40 RAM40 Row32 COM33 Row33 RAM33 Row41 RAM41 Row33 RAM41 Row33 RAM33 Row41 RAM41 Row33 RAM41 COM34 Row34 RAM34 Row42 RAM42 Row34 RAM42 Row34 RAM34 Row42 RAM42 Row34 RAM42 COM35 Row35 RAM35 Row43 RAM43 Row35 RAM43 Row35 RAM35 Row43 RAM43 Row35 RAM43 COM36 Row36 RAM36 Row44 RAM44 Row36 RAM44 Row36 RAM36 Row44 RAM44 Row36 RAM44 COM37 Row37 RAM37 Row45 RAM45 Row37 RAM45 Row37 RAM37 Row45 RAM45 Row37 RAM45 COM38 Row38 RAM38 Row46 RAM46 Row38 RAM46 Row38 RAM38 Row46 RAM46 Row38 RAM46 COM39 Row39 RAM39 Row47 RAM47 Row39 RAM47 Row39 RAM39 Row47 RAM47 Row39 RAM47 COM40 Row40 RAM40 Row48 RAM48 Row40 RAM48 Row40 RAM40 Row48 RAM48 Row40 RAM48 COM41 Row41 RAM41 Row49 RAM49 Row41 RAM49 Row41 RAM41 Row49 RAM49 Row41 RAM49 COM42 Row42 RAM42 Row50 RAM50 Row42 RAM50 Row42 RAM42 Row50 RAM50 Row42 RAM50 COM43 Row43 RAM51 RAM16 RAM40 Row43 RAM43 Row51 RAM51 Row43 RAM51 Row43 RAM43 Row51 RAM51 COM44 Row44 RAM44 Row52 RAM52 Row44 RAM52 Row44 RAM44 Row52 RAM52 Row44 RAM52 COM45 Row45 RAM45 Row53 RAM53 Row45 RAM53 Row45 RAM45 Row53 RAM53 Row45 RAM53 COM46 Row46 RAM46 Row54 RAM54 Row46 RAM54 Row46 RAM46 Row54 RAM54 Row46 RAM54 COM47 Row47 RAM47 Row55 RAM55 Row47 RAM55 Row47 RAM47 Row55 RAM55 Row47 RAM55 COM48 Row48 RAM48 Row56 RAM56 Row48 RAM56 Row48 RAM48 - - Row48 RAM56 COM49 Row49 RAM49 Row57 RAM57 Row49 RAM57 Row49 RAM49 - - Row49 RAM57 COM50 Row50 RAM50 Row58 RAM58 Row50 RAM58 Row50 RAM50 - - Row50 RAM58 COM51 Row51 RAM51 Row59 RAM59 Row51 RAM59 Row51 RAM51 - - Row51 RAM59 COM52 Row52 RAM52 Row60 RAM60 Row52 RAM60 Row52 RAM52 - - Row52 RAM60 COM53 Row53 RAM53 Row61 RAM61 Row53 RAM61 Row53 RAM53 - - Row53 RAM61 COM54 Row54 RAM54 Row62 RAM62 Row54 RAM62 Row54 RAM54 - - Row54 RAM62 COM55 Row55 RAM55 Row63 RAM63 Row55 RAM63 Row55 RAM55 - - Row55 RAM63 COM56 Row56 RAM56 Row0 RAM0 Row56 RAM0 - - Row0 RAM0 - - COM57 Row57 RAM57 Row1 RAM1 Row57 RAM1 - - Row1 RAM1 - - COM58 Row58 RAM58 Row2 RAM2 Row58 RAM2 - - Row2 RAM2 - - COM59 Row59 RAM59 Row3 RAM3 Row59 RAM3 - - Row3 RAM3 - - COM60 Row60 RAM60 Row4 RAM4 Row60 RAM4 - - Row4 RAM4 - - COM61 Row61 RAM61 Row5 RAM5 Row61 RAM5 - - Row5 RAM5 - - COM62 Row62 RAM62 Row6 RAM6 Row62 RAM6 - - Row6 RAM6 - - COM63 Row63 RAM63 Row7 RAM7 Row63 RAM7 - - Row7 RAM7 - - Display examples refer to figures: SSD1331 (a) (b) (c) (a) (b) (e) (f) Rev 0.13 P 43/64 Mar 2006 (d) (e) (c) (f) (d) (RAM) Solomon Systech Table 14 - Example of Set Display Offset and Display Start Line with Remap Output Hardw are pin name 64 64 64 48 48 48 48 1 1 1 1 1 1 1 COM Scan Direction Remap (A0h A[4]) 0 8 0 0 8 0 8 Display offset (A2h) 0 0 8 0 0 8 16 Set MUX ratio(A8h) Display start line (A1h) COM0 Row 63 RAM63 Row 7 RAM7 Row 63 RAM7 Row 47 RAM47 - - Row 47 RAM7 - - COM1 Row 62 RAM62 Row 6 RAM6 Row 62 RAM6 Row 46 RAM46 - - Row 46 RAM6 - - COM2 Row 61 RAM61 Row 5 RAM5 Row 61 RAM5 Row 45 RAM45 - - Row 45 RAM5 - - COM3 Row 60 RAM60 Row 4 RAM4 Row 60 RAM4 Row 44 RAM44 - - Row 44 RAM4 - - COM4 Row 59 RAM59 Row 3 RAM3 Row 59 RAM3 Row 43 RAM43 - - Row 43 RAM3 - - COM5 Row 58 RAM58 Row 2 RAM2 Row 58 RAM2 Row 42 RAM42 - - Row 42 RAM2 - - COM6 Row 57 RAM57 Row 1 RAM1 Row 57 RAM1 Row 41 RAM41 - - Row 41 RAM1 - - COM7 Row 56 RAM56 Row 0 RAM0 Row 56 RAM0 Row 40 RAM40 - - Row 40 RAM0 - - COM8 Row 55 RAM55 Row 63 RAM63 Row 55 RAM63 Row 39 RAM39 Row 47 RAM47 Row 39 RAM47 Row 47 RAM63 COM9 Row 54 RAM54 Row 62 RAM62 Row 54 RAM62 Row 38 RAM38 Row 46 RAM46 Row 38 RAM46 Row 46 RAM62 COM10 Row 53 RAM53 Row 61 RAM61 Row 53 RAM61 Row 37 RAM37 Row 45 RAM45 Row 37 RAM45 Row 45 RAM61 COM11 Row 52 RAM52 Row 60 RAM60 Row 52 RAM60 Row 36 RAM36 Row 44 RAM44 Row 36 RAM44 Row 44 RAM60 COM12 Row 51 RAM51 Row 59 RAM59 Row 51 RAM59 Row 35 RAM35 Row 43 RAM43 Row 35 RAM43 Row 43 RAM59 COM13 Row 50 RAM50 Row 58 RAM58 Row 50 RAM58 Row 34 RAM34 Row 42 RAM42 Row 34 RAM42 Row 42 RAM58 COM14 Row 49 RAM49 Row 57 RAM57 Row 49 RAM57 Row 33 RAM33 Row 41 RAM41 Row 33 RAM41 Row 41 RAM57 COM15 Row 48 RAM48 Row 56 RAM56 Row 48 RAM56 Row 32 RAM32 Row 40 RAM40 Row 32 RAM40 Row 40 RAM56 COM16 Row 47 RAM47 Row 55 RAM55 Row 47 RAM55 Row 31 RAM31 Row 39 RAM39 Row 31 RAM39 Row 39 RAM55 COM17 Row 46 RAM46 Row 54 RAM54 Row 46 RAM54 Row 30 RAM30 Row 38 RAM38 Row 30 RAM38 Row 38 RAM54 COM18 Row 45 RAM45 Row 53 RAM53 Row 45 RAM53 Row 29 RAM29 Row 37 RAM37 Row 29 RAM37 Row 37 RAM53 COM19 Row 44 RAM44 Row 52 RAM52 Row 44 RAM52 Row 28 RAM28 Row 36 RAM36 Row 28 RAM36 Row 36 RAM52 COM20 Row 43 RAM43 Row 51 RAM51 Row 43 RAM51 Row 27 RAM27 Row 35 RAM35 Row 27 RAM35 Row 35 RAM51 COM21 Row 42 RAM42 Row 50 RAM50 Row 42 RAM50 Row 26 RAM26 Row 34 RAM34 Row 26 RAM34 Row 34 RAM50 COM22 Row 41 RAM41 Row 49 RAM49 Row 41 RAM49 Row 25 RAM25 Row 33 RAM33 Row 25 RAM33 Row 33 RAM49 COM23 Row 40 RAM40 Row 48 RAM48 Row 40 RAM48 Row 24 RAM24 Row 32 RAM32 Row 24 RAM32 Row 32 RAM48 COM24 Row 39 RAM39 Row 47 RAM47 Row 39 RAM47 Row 23 RAM23 Row 31 RAM31 Row 23 RAM31 Row 31 RAM47 COM25 Row 38 RAM38 Row 46 RAM46 Row 38 RAM46 Row 22 RAM22 Row 30 RAM30 Row 22 RAM30 Row 30 RAM46 COM26 Row 37 RAM37 Row 45 RAM45 Row 37 RAM45 Row 21 RAM21 Row 29 RAM29 Row 21 RAM29 Row 29 RAM45 COM27 Row 36 RAM36 Row 44 RAM44 Row 36 RAM44 Row 20 RAM20 Row 28 RAM28 Row 20 RAM28 Row 28 RAM44 COM28 Row 35 RAM35 Row 43 RAM43 Row 35 RAM43 Row 19 RAM19 Row 27 RAM27 Row 19 RAM27 Row 27 RAM43 COM29 Row 34 RAM34 Row 42 RAM42 Row 34 RAM42 Row 18 RAM18 Row 26 RAM26 Row 18 RAM26 Row 26 RAM42 COM30 Row 33 RAM33 Row 41 RAM41 Row 33 RAM41 Row 17 RAM17 Row 25 RAM25 Row 17 RAM25 Row 25 RAM41 COM31 Row 32 RAM32 Row 40 RAM40 Row 32 RAM40 Row 16 RAM16 Row 24 RAM24 Row 16 RAM24 Row 24 RAM40 COM32 Row 31 RAM31 Row 39 RAM39 Row 31 RAM39 Row 15 RAM15 Row 23 RAM23 Row 15 RAM23 Row 23 RAM39 COM33 Row 30 RAM30 Row 38 RAM38 Row 30 RAM38 Row 14 RAM14 Row 22 RAM22 Row 14 RAM22 Row 22 RAM38 COM34 Row 29 RAM29 Row 37 RAM37 Row 29 RAM37 Row 13 RAM13 Row 21 RAM21 Row 13 RAM21 Row 21 RAM37 COM35 Row 28 RAM28 Row 36 RAM36 Row 28 RAM36 Row 12 RAM12 Row 20 RAM20 Row 12 RAM20 Row 20 RAM36 COM36 Row 27 RAM27 Row 35 RAM35 Row 27 RAM35 Row 11 RAM11 Row 19 RAM19 Row 11 RAM19 Row 19 RAM35 COM37 Row 26 RAM26 Row 34 RAM34 Row 26 RAM34 Row 10 RAM10 Row 18 RAM18 Row 10 RAM18 Row 18 RAM34 COM38 Row 25 RAM25 Row 33 RAM33 Row 25 RAM33 Row 9 RAM9 Row 17 RAM17 Row 9 RAM17 Row 17 RAM33 COM39 Row 24 RAM24 Row 32 RAM32 Row 24 RAM32 Row 8 RAM8 Row 16 RAM16 Row 8 RAM16 Row 16 RAM32 COM40 Row 23 RAM23 Row 31 RAM31 Row 23 RAM31 Row 7 RAM7 Row 15 RAM15 Row 7 RAM15 Row 15 RAM31 COM41 Row 22 RAM22 Row 30 RAM30 Row 22 RAM30 Row 6 RAM6 Row 14 RAM14 Row 6 RAM14 Row 14 RAM30 COM42 Row 21 RAM21 Row 29 RAM29 Row 21 RAM29 Row 5 RAM5 Row 13 RAM13 Row 5 RAM13 Row 13 RAM29 RAM28 COM43 Row 20 RAM20 Row 28 RAM28 Row 20 RAM28 Row 4 RAM4 Row 12 RAM12 Row 4 RAM12 Row 12 COM44 Row 19 RAM19 Row 27 RAM27 Row 19 RAM27 Row 3 RAM3 Row 11 RAM11 Row 3 RAM11 Row 11 RAM27 COM45 Row 18 RAM18 Row 26 RAM26 Row 18 RAM26 Row 2 RAM2 Row 10 RAM10 Row 2 RAM10 Row 10 RAM26 COM46 Row 17 RAM17 Row 25 RAM25 Row 17 RAM25 Row 1 RAM1 Row 9 RAM9 Row 1 RAM9 Row 9 RAM25 COM47 Row 16 RAM16 Row 24 RAM24 Row 16 RAM24 Row 0 RAM0 Row 8 RAM8 Row 0 RAM8 Row 8 RAM24 COM48 Row 15 RAM15 Row 23 RAM23 Row 15 RAM23 - - Row 7 RAM7 - - Row 7 RAM23 COM49 Row 14 RAM14 Row 22 RAM22 Row 14 RAM22 - - Row 6 RAM6 - - Row 6 RAM22 COM50 Row 13 RAM13 Row 21 RAM21 Row 13 RAM21 - - Row 5 RAM5 - - Row 5 RAM21 COM51 Row 12 RAM12 Row 20 RAM20 Row 12 RAM20 - - Row 4 RAM4 - - Row 4 RAM20 COM52 Row 11 RAM11 Row 19 RAM19 Row 11 RAM19 - - Row 3 RAM3 - - Row 3 RAM19 COM53 Row 10 RAM10 Row 18 RAM18 Row 10 RAM18 - - Row 2 RAM2 - - Row 2 RAM18 COM54 Row 9 RAM9 Row 17 RAM17 Row 9 RAM17 - - Row 1 RAM1 - - Row 1 RAM17 COM55 Row 8 RAM8 Row 16 RAM16 Row 8 RAM16 - - Row 0 RAM0 - - Row 0 RAM16 COM56 Row 7 RAM7 Row 15 RAM15 Row 7 RAM15 - - - - - - - - COM57 Row 6 RAM6 Row 14 RAM14 Row 6 RAM14 - - - - - - - - COM58 Row 5 RAM5 Row 13 RAM13 Row 5 RAM13 - - - - - - - - COM59 Row 4 RAM4 Row 12 RAM12 Row 4 RAM12 - - - - - - - - COM60 Row 3 RAM3 Row 11 RAM11 Row 3 RAM11 - - - - - - - - COM61 Row 2 RAM2 Row 10 RAM10 Row 2 RAM10 - - - - - - - - COM62 Row 1 RAM1 Row 9 RAM9 Row 1 RAM9 - - - - - - - - COM63 Row 0 RAM0 Row 8 RAM8 Row 0 RAM8 - - - - - - - - Display examples refer to figures: (a) (b) (a) (e) Solomon Systech (c) (d) (e) (b) (c) (f) (g) (f) (g) (d) (RAM) Mar 2006 P 44/64 Rev 0.13 SSD1331 9.1.9 Set Display Mode (A4h ~ A7h) These are single byte command and they are used to set Normal Display, Entire Display On, Entire Display Off and Inverse Display. • Normal Display (A4h) Reset the above effect and turn the data to ON at the corresponding gray level. • Set Entire Display On (A5h) Forces the entire display to be at “GS63” regardless of the contents of the display data RAM. • Set Entire Display Off (A6h) Forces the entire display to be at gray level “GS0” regardless of the contents of the display data RAM. • Inverse Display (A7h) The gray level of display data are swapped such that “GS0” <-> “GS63”, “GS1” <-> “GS62”, …. 9.1.10 Set Multiplex Ratio (A8h) This command switches default 1:64 multiplex mode to any multiplex mode from 16 to 64. For example, when multiplex ratio is set to 16, only 16 common pins are enabled. The starting and the ending of the enabled common pins are depended on the setting of “Display Offset” register programmed by command A2h. 9.1.11 Set Master Configuration (ADh) This command selects the external VCC power supply. External VCC power should be connected to the VCC pin. A[0] bit must be set to 0b after RESET. This command will be activated after issuing Set Display ON command (AFh) 9.1.12 Set Display On/Off (AEh / AFh) These single byte commands are used to turn the OLED panel display on or off. When the display is on, the selected circuits by Set Master Configuration command will be turned on. When the display is off, those circuits will be turned off and the segment and common output are in high impedance state. These commands set the display to one of the two states: o AEh: Display Off o AFh: Display On 9.1.13 Power Save Mode (B0h) This command is used in enabling the power saving mode. 9.1.14 Phase 1 and 2 Period Adjustment (B1h) This command sets the length of phase 1 and 2 of segment waveform of the driver. • Phase 1 (A[3:0]): Set the period from 1 to 15 in the unit of DCLKs. A larger capacitance of the OLED pixel may require longer period to discharge the previous data charge completely. • Phase 2 (A[7:4]): Set the period from 1 to 15 in the unit of DCLKs. A longer period is needed to charge up a larger capacitance of the OLED pixel to the target voltage VP for color A, B and C. SSD1331 Rev 0.13 P 45/64 Mar 2006 Solomon Systech 9.1.15 Set Display Clock Divide Ratio/ Oscillator Frequency (B3h) This command consists of two functions: • Display Clock Divide Ratio (A[3:0]) Set the divide ratio to generate DCLK (Display Clock) from CLK. The divide ratio is from 1 to 16, with power on reset value = 1. Please refer to section 7.3.1 for the details relationship of DCLK and CLK. • Oscillator Frequency (A[7:4]) Program the oscillator frequency Fosc that is the source of CLK if CLS pin is pulled high. The 4-bit value results in 16 different frequency setting available as shown below. The default setting is 1101b Figure 26 - Typical Oscillator frequency adjustment by B3 command ˄˃˃˃ ˢ̆˶˼˿˿˴̇̂̅ʳ˙̅˸̄̈˸́˶̌ʳ̉̆ʳ˕ˆʳ˶̂̀̀˴́˷ʳ̆˸̇̇˼́˺ ˙̅˸̄̈˸́˶̌ʳʻ˾˛̍ʼ ˌ˃˃ ˋ˃˃ ˊ˃˃ ˉ˃˃ ˈ˃˃ ˔ˮˊˍˇ˰ʳ˼́ʳ˷˸˶˼̀˴˿ ˇ˃˃ ˃ ˅ ˇ ˉ ˋ ˄˃ ˄˅ ˄ˇ ˄ˉ 9.1.16 Set Gray Scale Table (B8h) This command is used to set the gray scale table for the display. Except gray scale entry 0, which is zero as it has no pre-charge and current drive, each odd entry gray scale level is programmed in the length of current drive stage pulse width with unit of DCLK. The longer the length of the pulse width, the brighter is the OLED pixel when it’s turned on. Please refer to section 7.6 for more detailed explanation of relation of display data RAM, gray scale table and the pixel brightness. Following the command B8h, the user has to set the pulse width for GS1, GS3, GS5, …, GS59, GS61, and GS63 one by one in sequence and complies the following conditions. GS1 > 0; GS3 > GS1 + 1; GS5 > GS3 + 1; …… Afterwards, the driver automatically derives the pulse width of even entry of gray scale table GS2, GS4, …, GS62 with the formula like below. GSn = (GSn-1 + GSn+1) / 2 For example, if GS1 = 3 DCLKs and GS3 = 7 DCLKs, GS2 = (3+7)/2 = 5 DCLKs The setting of gray scale table entry can perform gamma correction on OLED panel display. Normally, it is desired that the brightness response of the panel is linearly proportional to the image data value in display data RAM. However, the OLED panel is somehow responded in non-linear way. Appropriate gray scale table setting like example below can compensate this effect. Solomon Systech Mar 2006 P 46/64 Rev 0.13 SSD1331 Figure 27 - Example of gamma correction by gray scale table setting Brightness Pulse Width Brightness Gray scale table setting Panel response Gray Scale Result in linear response Gray Scale Pulse width 9.1.17 Enable Linear Gray Scale Table (B9h) This command reloads the preset linear gray scale table as GS1 = 1, GS2 = 3, GS3 = 5, …., GS62 = 123, GS63 = 125 DCLKs. 9.1.18 Set Pre-charge voltage (BBh) This command sets the pre-charge voltage level of segment pins. The level of VP is programmed with reference to VCC. Figure 28 shows the details of setting Pre-charge voltage level by command BBh A[5:1]. Figure 28 – Typical Pre-charge voltage level setting by command BBh. VP ratio VP ratio vs BBh A[5:1] setting 0.6 0.5 0.4 0.3 0.2 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 0 00000 0.1 BBh A[5:1] Setting Note (!) VP ratio = 0.1 refers to VP voltage = 0.1 x VCC. 9.1.19 Set VCOMH Voltage (BEh) This command sets the high voltage level of common pins. The level of VCOMH is programmed with reference to VCC. 9.1.20 NOP (BCh, BDh, E3h) These are command for no operation. 9.1.21 Set Command Lock (FDh) This command is used to lock the OLED driver IC from accepting any command except itself. After entering FDh 16h (A[2]=1b), the OLED driver IC will not respond to any newly entered command (except FDh 12h A[2]=0b) and there will be no memory access. This is call “Lock” state. That means the OLED driver IC ignore all the commands (except FDh 12h A[2]=0b) during the “Lock” state. Entering FDh 12h (A[2]=0b) can unlock the OLED driver IC. That means the driver IC resume from the “Lock” state. And the driver IC will then respond to the command and memory access. SSD1331 Rev 0.13 P 47/64 Mar 2006 Solomon Systech 9.2 GRAPHIC ACCELERATION COMMAND SET DESCRIPTION 9.2.1 Draw Line (21h) This command draws a line by the given start, end column and row coordinates and the color of the line. Line Color Row 2, Column 2 Row 1, Column 1 Figure 29 - Example of Draw Line Command For example, the line above can be drawn by the following command sequence. 1. Enter into draw line mode by command 21h 2. Send column start address of line, column1, for example = 1h 3. Send row start address of line, row 1, for example = 10h 4. Send column end address of line, column 2, for example = 28h 5. Send row end address of line, row 2, for example = 4h 6. Send color C, B and A of line, for example = 35d, 0d, 0d for blue color 9.2.2 Draw Rectangle (22h) Given the starting point (Row 1, Column 1) and the ending point (Row 2, Column 2), specify the outline and fill area colors, a rectangle that will be drawn with the color specified. Remarks: If fill color option is disabled, the enclosed area will not be filled. Figure 30 - Example of Draw Rectangle Command Row 1, Column 1 Filled Color Outline Color Row 2, Column 2 The following example illustrates the rectangle drawing command sequence. 1. Enter the “draw rectangle mode” by execute the command 22h 2. Set the starting column coordinates, Column 1. e.g., 03h. 3. Set the starting row coordinates, Row 1. e.g., 02h. 4. Set the finishing column coordinates, Column 2. e.g., 12h 5. Set the finishing row coordinates, Row 2. e.g., 15h 6. Set the outline color C, B and A. e.g., (28d, 0d, 0d) for blue color 7. Set the filled color C, B and A. e.g., (0d, 0d, 40d) for red color Solomon Systech Mar 2006 P 48/64 Rev 0.13 SSD1331 9.2.3 Copy (23h) Copy the rectangular region defined by the starting point (Row 1, Column 1) and the ending point (Row 2, Column 2) to location (Row 3, Column 3). If the new coordinates are smaller than the ending points, the new image will overlap the original one. The following example illustrates the copy procedure. 1. Enter the “copy mode” by execute the command 23h 2. Set the starting column coordinates, Column 1. E.g., 00h. 3. Set the starting row coordinates, Row 1. E.g., 00h. 4. Set the finishing column coordinates, Column 2. E.g., 05h 5. Set the finishing row coordinates, Row 2. E.g., 05h 6. Set the new column coordinates, Column 3. E.g., 03h 7. Set the new row coordinates, Row 3. E.g., 03h Figure 31 - Example of Copy Command Original Image Row 1, Column 1 Row 3, Column 3 New Copied Image Row 3 + Row 2, Column 3 + Column 2 9.2.4 Dim Window (24h) This command will dim the window area specify by starting point (Row 1, Column 1) and the ending point (Row 2, Column 2). After the execution of this command, the selected window area will become darker as follow. Table 15 - Result of Change of Brightness by Dim Window Command Original gray scale GS0 ~ GS15 GS16 ~ GS19 GS20 ~ GS23 : GS60 ~ GS63 New gray scale after dim window command No change GS4 GS5 : GS15 Additional execution of this command over the same window area will not change the data content. SSD1331 Rev 0.13 P 49/64 Mar 2006 Solomon Systech 9.2.5 Clear Window (25h) This command sets the window area specify by starting point (Row 1, Column 1) and the ending point (Row 2, Column 2) to clear the window display. The graphic display data RAM content of the specified window area will be set to zero. This command can be combined with Copy command to make as a “move” result. The following example illustrates the copy plus clear procedure and results in moving the window object. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Enter the “copy mode” by execute the command 23h Set the starting column coordinates, Column 1. E.g., 00h. Set the starting row coordinates, Row 1. E.g., 00h. Set the finishing column coordinates, Column 2. E.g., 05h Set the finishing row coordinates, Row 2. E.g., 05h Set the new column coordinates, Column 3. E.g., 06h Set the new row coordinates, Row 3. E.g., 06h Enter the “clear mode” by execute the command 24h Set the starting column coordinates, Column 1. E.g., 00h. Set the starting row coordinates, Row 1. E.g., 00h. Set the finishing column coordinates, Column 2. E.g., 05h Set the finishing row coordinates, Row 2. E.g., 05h Clear Command Figure 32 - Example of Copy + Clear = Move Command 9.2.6 Fill Enable/Disable (26h) This command has two functions. • Enable/Disable fill (A[0]) 0 = Disable filling of color into rectangle in draw rectangle command. (RESET) 1 = Enable filling of color into rectangle in draw rectangle command. • Enable/Disable reverse copy (A[4]) 0 = Disable reverse copy (RESET) 1 = During copy command, the new image colors are swapped such that “GS0” <-> “GS63”, “GS1” <> “GS62”, …. Solomon Systech Mar 2006 P 50/64 Rev 0.13 SSD1331 9.2.7 Continuous Horizontal & Vertical Scrolling Setup (27h) This command setup the parameters required for horizontal and vertical scrolling. Figure 33 - Examples of Continuous Horizontal and Vertical Scrolling command setup Display snap shot after scrolling start Display before scrolling start Example 1 : Partial screen horizontal left side scrolling with 1 column shift in every 6 frames Sample code 27h // Continuous horizontal scroll 01h // Horizontal scroll by 1 column 28h // Define row 40 as start row address 18h // Scrolling 24 rows 00h // No vertical scroll 00h // Set time interval between each scroll step as 6 frames 2Fh // Activate scrolling Start row address No of scrolling rows Display snap shot after scrolling start Display before scrolling start Example 2 : Full screen vertical scrolling with 1 row up in every 6 frames. Sample code 27h // Continuous vertical scroll 00h // No horizontal scroll 00h // Start row address for vertical scrolling 40h // Number of scrolling rows for vertical scrolling 01h // Set vertical scrolling offset as 1 row 00h // Set time interval between each scroll step as 6 frames 2Fh // Activate scrolling Display snap shot after scrolling start Display before scrolling start Start row address No of scrolling rows Example 3 : Full screen diagonal scrolling (horizontal left side scrolling with 1 column shift plus vertical scrolling with 1 row up) in every 10 frames. Sample code 27h // Continuous diagonal scroll 01h // Horizontal scroll by 1 column 00h // Define row 0 as start row address 40h // Scrolling 64 rows 01h // Set vertical scrolling offset as 1 row 01h // Set time interval between each scroll step as 10 frames 2Fh // Activate scrolling 9.2.8 Deactivate scrolling (2Eh) This command deactivates the scrolling action. 9.2.9 Activate scrolling (2Fh) This command activates the scrolling function according to the setting done by Continuous Horizontal & Vertical Scrolling Setup command 27h. SSD1331 Rev 0.13 P 51/64 Mar 2006 Solomon Systech 10 MAXIMUM RATINGS Table 16 - Maximum Ratings (Voltage Reference to VSS) Symbol VDD VDDIO VCC VSEG / VCOM ISEG Vin TA Tstg Parameter Supply Voltage SEG/COM output voltage SEG output current Input voltage Operating Temperature Storage Temperature Range Value -0.3 to +4 -0.3 to VDD+0.5 0 to 17.0 0 to 17.0 0 to 220 VSS -0.3 to VDD +0.3 -40 to +85 -65 to +150 Unit V V V V uA V ºC ºC *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description. Solomon Systech Mar 2006 P 52/64 Rev 0.13 SSD1331 11 DC CHARACTERISTICS Table 17 - DC Characteristics Conditions (unless specified): Voltage referenced to VSS VDD = 2.7, VDDIO = 1.8V, VCC = 11.0V, IREF = 10uA, at TA = 25°C. Symbol VCC VDD VDDIO VOH VOL VIH VIL Parameter Operating Voltage Logic Supply Voltage Power Supply for I/O pins High Logic Output Level Low Logic Output Level High Logic Input Level Low Logic Input Level Test Condition IOUT = 100uA, 3.3MHz IOUT = 100uA, 3.3MHz - IDD_SLEEP Sleep mode VDD Current IDDIO SLEEP Min Typ Max Unit 8 11 16 V 2.4 2.7 3.5 V 1.6 1.8 VDD V 0.9 x VDDIO VDDIO V 0 0.1 x VDDIO V 0.8 x VDDIO VDDIO V 0 0.2 x VDDIO V Display OFF, No panel attached - 0 10 uA Sleep mode VDDIO Current Display OFF, No panel attached - 0 10 uA - 0 10 uA - 700 1200 uA - 170 500 Contrast = FFh 142 155 168 uA Contrast = 7Fh - 78 - uA Contrast = 3Fh - 39 - uA Contrast = FFh -3 - +3 % Contrast = FFh -2 - +2 % COM[0:63], I = 20mA - 25 30 Ω ICC_SLEEP Sleep mode VCC Current ICC VCC Supply Current IDD VDD Supply Current Display OFF, No panel attached Display ON, Contrast = FFh, No panel attached Display ON, Contrast = FFh, No panel attached Segment Output Current: VCC = 8V, Display ON, All 1’s pattern. ISEG (Segment pin under test is connected with a 20K ȍ resistive load to VSS) Segment Output Current Uniformity: Dev = (ISEG – IMID) / IMID Dev IMID = (IMAX + IMIN) / 2 ISEG [0:287] = Segment current at contrast settings VCC =12V Adjacent pin output current uniformity: Adj. Dev Adj Dev = (I[n] - I[n+1]) / (I[n]+I[n+1]) RCOM_ON COM pin output resistance SSD1331 Rev 0.13 P 53/64 Mar 2006 uA Solomon Systech 12 AC CHARACTERISTICS Table 18 - AC Characteristics Conditions (Unless otherwise specified): Voltage referenced to VSS VDD = VDDIO = 2.4V to 3.5V VCC = 9.0V to 16.0V TA = 25°C Symbol FOSC Parameter Oscillation Frequency of Display Timing Generator FFRM Frame Frequency RES# Reset low pulse width Reset completion time Test Condition VDD = 2.7V Display ON, Internal Oscillator Enabled - Min Typ Max Unit 774 860 946 KHz - FOSC x 1 / (D x K x N) - Hz 3 - - 2 us us Note (1) Fosc stands for the frequency value of the internal oscillator (2) D stands for divide ratio (3) K stands for total number of display clocks per row. (RESET=136, i.e. phase1 DCLK+phase2 DCLK + phase3 DCLK =4+7+125) (4) N stands for number of MUX selected by command A8h Solomon Systech Mar 2006 P 54/64 Rev 0.13 SSD1331 Table 19 - 6800-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4V to 3.5V, VDDIO = 2.4V to VDD, TA = -40 to +85°C) Symbol tcycle PWCSL PWCSH tcycle PWCSL PWCSH tAS tAH tDSW tDHW tACC tOH tR tF Parameter Clock Cycle Time (write cycle) Control Pulse Low Width (write cycle) Control Pulse High Width (write cycle) Clock Cycle Time (read cycle) Control Pulse Low Width (read cycle) Control Pulse High Width (read cycle) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Data Access Time Output Hold time Min 130 60 60 200 100 100 0 10 40 10 - Typ - Max 140 70 Unit ns ns ns ns ns ns ns ns ns ns ns ns - - 15 15 ns ns Rise Time Fall Time D/C# tAS tAH R/W# CS# tR tF tcycle PWCSH PWCSL E tDHW tDSW D[15:0] (WRITE) Valid Data tACC D[15:0] (READ) tDHR Valid Data tOH Figure 34 - 6800-series parallel interface characteristics SSD1331 Rev 0.13 P 55/64 Mar 2006 Solomon Systech Table 20 - 8080-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4V to 3.5V, VDDIO = 2.4V to VDD, TA = -40 to 85°C) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PWCSL PWCSH tR tF Parameter Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min Typ Max Unit 130 0 10 40 10 20 100 60 60 60 - - 70 140 - ns ns ns ns ns ns ns ns ns - - ns - 15 15 ns ns D/C# tAS t AH CS# tF tcycle tR PW CSL PW CSH RD# WR# tDSW tDHW D[15:0] Valid Data (Write data to driver) D[15:0] tDHR tACC (Read data from driver) Valid Data tOH Figure 35 - 8080-series parallel interface characteristics Solomon Systech Mar 2006 P 56/64 Rev 0.13 SSD1331 Table 21 - Serial Interface Timing Characteristics (VDD - VSS = 2.4V to 3.5V, VDDIO = 2.4V to VDD, TA = -40 to 85°C) Symbol tcycle tAS tAH tCSS tCSH tDSW tDHW tCLKL tCLKH Parameter Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time tR tF Min Typ Max Unit 150 40 40 75 60 40 40 75 75 - - 15 15 ns ns ns ns ns ns ns ns ns ns ns D/C# tAS tAH tCSS CS# tCSH tcycle tCLKL tCLKH SCLK(D0) tF tR tDHW tDSW SDIN(D1) Valid Data CS# SCLK(D0) D7 SDIN(D1) D6 D5 D4 D3 D2 D1 D0 Figure 36 - Serial interface characteristics SSD1331 Rev 0.13 P 57/64 Mar 2006 Solomon Systech 13 APPLICATION EXAMPLE The configuration for 6800-parallel interface mode, externally VCC is shown in the following diagram: (VDD = 3.0V, external VCC = 12V, IREF = 10uA) COM1 . . COM63 SA0 SB0 SC0 . . . . . . . . . . SA95 SB95 SC95 COM62 . . COM0 Color OLED Panel 96RGB x 64 SSD1331U1 NC VCC VCOMH NC D7~D0 E R/W# D/C# RES# CS# IREF BS2 BS1 VDD VBREF FB VDDB GDR VSS NC C1 R1 C2 C3 D7~D0 E VSS [GND] R/W# D/C# RES# CS# Pin connected to MCU interface: D0~D7, E, R/W#, D/C#, RES#, CS# Pin internally connected to VDDIO: CLS, Pin internally connected to VSS: VSSB, B00, BS3 Pin internally connected to VDD: AVDD C1~C3: 4.7uF Voltage at IREF = VCC – 3V R1 = (Voltage at IREF - VSS) / IREF = 910KΩ for 12V VCC Figure 37 - Application Example for SSD1331U1R1 Solomon Systech Mar 2006 P 58/64 Rev 0.13 SSD1331 14 PACKAGE OPTIONS 14.1 SSD1331Z Die Tray Information Figure 38 - Die Tray Information Spec mm (mil) 76.00 ± 0.10 (2992) W1 68.00 ± 0.10 (2677) W2 4.20± 0.10 (165) H 13.66±0.10 (538) Dx 48.78±0.10 (1920) TPx 7.55±0.10 (297) Dy 61.00±0.10 (2402) TPy 16.26 ± 0.05 (640) Px 3.05 ± 0.05 (120) Py 13.25 ± 0.01 (522) X 1.73 ± 0.01 (68) Y 0.62 ± 0.05 (24) Z N 84 (Pocket number) SSD1331 Rev 0.13 P 59/64 Mar 2006 Solomon Systech 14.2 SSD1331U1R1 COF PACKAGE DIMENSIONS Figure 39 - SSD1331U1R1 outline drawing Solomon Systech Mar 2006 P 60/64 Rev 0.13 SSD1331 SSD1331 Rev 0.13 P 61/64 Mar 2006 Solomon Systech 14.3 SSD1331U1R1 COF PACKAGE PIN ASSIGNMENT Figure 40 - SSD1331U1R1 pin assignment drawing Solomon Systech Mar 2006 P 62/64 Rev 0.13 SSD1331 Table 22 - SSD1331U1R1 pin assignment Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin name NC VCC VCOMH NC D7 D6 D5 D4 D3 D2 D1 D0 E R/W# D/C# RES# CS# IREF BS2 BS1 VDD NC NC NC VBREF NC FB VDDB GDR VSS NC NC NC NC COM63 COM61 COM59 COM57 COM55 COM53 COM51 COM49 COM47 COM45 COM43 COM41 COM39 COM37 COM35 COM33 COM31 COM29 COM27 COM25 COM23 COM21 COM19 COM17 COM15 COM13 COM11 COM9 COM7 COM5 COM3 COM1 NC NC NC NC NC NC NC NC NC NC NC NC NC SC95 SSD1331 Pin no. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Rev 0.13 Pin name SB95 SA95 SC94 SB94 SA94 SC93 SB93 SA93 SC92 SB92 SA92 SC91 SB91 SA91 SC90 SB90 SA90 SC89 SB89 SA89 SC88 SB88 SA88 SC87 SB87 SA87 SC86 SB86 SA86 SC85 SB85 SA85 SC84 SB84 SA84 SC83 SB83 SA83 SC82 SB82 SA82 SC81 SB81 SA81 SC80 SB80 SA80 SC79 SB79 SA79 SC78 SB78 SA78 SC77 SB77 SA77 SC76 SB76 SA76 SC75 SB75 SA75 SC74 SB74 SA74 SC73 SB73 SA73 SC72 SB72 SA72 SC71 SB71 SA71 SC70 SB70 SA70 SC69 SB69 SA69 P 63/64 Pin no. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Mar 2006 Pin name SC68 SB68 SA68 SC67 SB67 SA67 SC66 SB66 SA66 SC65 SB65 SA65 SC64 SB64 SA64 SC63 SB63 SA63 SC62 SB62 SA62 SC61 SB61 SA61 SC60 SB60 SA60 SC59 SB59 SA59 SC58 SB58 SA58 SC57 SB57 SA57 SC56 SB56 SA56 SC55 SB55 SA55 SC54 SB54 SA54 SC53 SB53 SA53 SC52 SB52 SA52 SC51 SB51 SA51 SC50 SB50 SA50 SC49 SB49 SA49 SC48 SB48 SA48 SC47 SB47 SA47 SC46 SB46 SA46 SC45 SB45 SA45 SC44 SB44 SA44 SC43 SB43 SA43 SC42 SB42 Pin no. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 Pin name SA42 SC41 SB41 SA41 SC40 SB40 SA40 SC39 SB39 SA39 SC38 SB38 SA38 SC37 SB37 SA37 SC36 SB36 SA36 SC35 SB35 SA35 SC34 SB34 SA34 SC33 SB33 SA33 SC32 SB32 SA32 SC31 SB31 SA31 SC30 SB30 SA30 SC29 SB29 SA29 SC28 SB28 SA28 SC27 SB27 SA27 SC26 SB26 SA26 SC25 SB25 SA25 SC24 SB24 SA24 SC23 SB23 SA23 SC22 SB22 SA22 SC21 SB21 SA21 SC20 SB20 SA20 SC19 SB19 SA19 SC18 SB18 SA18 SC17 SB17 SA17 SC16 SB16 SA16 SC15 Pin no. 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 Pin name SB15 SA15 SC14 SB14 SA14 SC13 SB13 SA13 SC12 SB12 SA12 SC11 SB11 SA11 SC10 SB10 SA10 SC9 SB9 SA9 SC8 SB8 SA8 SC7 SB7 SA7 SC6 SB6 SA6 SC5 SB5 SA5 SC4 SB4 SA4 SC3 SB3 SA3 SC2 SB2 SA2 SC1 SB1 SA1 SC0 SB0 SA0 NC NC NC NC NC NC NC NC NC NC NC NC NC COM0 COM2 COM4 COM6 COM8 COM10 COM12 COM14 COM16 COM18 COM20 COM22 COM24 COM26 COM28 COM30 COM32 COM34 COM36 COM38 Pin no. 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 Pin name COM40 COM42 COM44 COM46 COM48 COM50 COM52 COM54 COM56 COM58 COM60 COM62 NC NC NC Solomon Systech Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part http://www.solomon-systech.com Solomon Systech Mar 2006 P 64/64 Rev 0.13 SSD1331