Amendment history of SSD1322 Specification

SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1322
Advance Information
480 x 128, Dot Matrix High Power OLED/PLED
Segment/Common Driver with Controller
This document contains information on a new product. Specifications and information herein are subject to change without
notice.
http://www.solomon-systech.com
SSD1322
Rev 1.2
P 1/60
Jul 2010
Copyright © 2010 Solomon Systech Limited
Appendix: IC Revision history of SSD1322 Specification
Version
1.0
1.
2.
3.
4.
5.
6.
1.1
1.
2.
3.
1.2
1.
2.
3.
4.
5.
6.
7.
8.
9.
SSD1322
Change Items
Changed to Advance Information
Revised the typo errors on commands BBh and BEh (Section 9)
Amended the default OSCFREQ[3:0] of command B3h from 1100b to 0101b
(Section 9)
Updated the DC Characteristics table (Section 12)
Updated the AC Characteristics table (Section 13)
Revise Table 13-5 & Figure 13-4 (3 wire SPI)
Effective Date
23-Jul-08
Updated the ordering P/N from SSD1322Z to SSD1322Z2 (P.7) and
corresponding information (Section 5)
Updated the application examples (P.55, 56)
Added SSD1322Z2 die tray information (Section 15.2)
10-Sep-08
Revise typo in Section 3 : No. of SPH from 4 to 5 (P.7)
Revise die thickness tolerance from ±25um to ±15um on Table 3-1 (P.7) &
Fig 5-1(P.9)
Added +/- 0.05mm tolerance for Die Size (after sawing) and revise bump
size typo in Section 5 ( P.9 )
Update Table 3-2: SSD1322Z2 Bump Die Pad Coordinates (p.10)
Update Power On sequence (P.30)
Updated P/N from SSD1322Z to SSD1322Z2 in Fig 10-6 &10-7 (P.41)
Revised a typo on the command description of command ABh (P.45)
Add alignment mark detail of SSD1322UR1 in Fig 15-1 (P.57)
Revised declaimer (P.60)
13-Jul-10
Rev 1.2
P 2/60
Jul 2010
Solomon Systech
CONTENTS
1
GENERAL DESCRIPTION .................................................................................................. 7
2
FEATURES ............................................................................................................................. 7
3
ORDERING INFORMATION.............................................................................................. 7
4
BLOCK DIAGRAM ............................................................................................................... 8
5
DIE PAD FLOOR PLAN ....................................................................................................... 9
6
PIN ARRANGEMENT ........................................................................................................ 13
6.1
SSD1322UR1 PIN ASSIGNMENT ............................................................................................................................13
7
PIN DESCRIPTIONS........................................................................................................... 15
8
FUNCTIONAL BLOCK DESCRIPTIONS ....................................................................... 18
8.1 MCU INTERFACE ..................................................................................................................................................18
8.1.1 MCU Parallel 6800-series Interface ...............................................................................................................18
8.1.2 MCU Parallel 8080-series Interface ...............................................................................................................19
8.1.3 MCU Serial Interface (4-wire SPI)..................................................................................................................20
8.1.4 MCU Serial Interface (3-wire SPI)..................................................................................................................21
8.2 RESET CIRCUIT......................................................................................................................................................22
8.3 GDDRAM ............................................................................................................................................................22
8.3.1 GDDRAM structure in Gray Scale mode.........................................................................................................22
8.3.2 Data bus to RAM mapping ..............................................................................................................................22
8.4 COMMAND DECODER ............................................................................................................................................23
8.5 OSCILLATOR & TIMING GENERATOR ....................................................................................................................23
8.6 SEG/COM DRIVING BLOCK .................................................................................................................................24
8.7 SEG / COM DRIVER .............................................................................................................................................25
8.8 GRAY SCALE DECODER.........................................................................................................................................29
8.9 POWER ON AND OFF SEQUENCE...........................................................................................................................30
8.10
VDD REGULATOR ..............................................................................................................................................31
9
COMMAND TABLE............................................................................................................ 32
10
COMMAND .......................................................................................................................... 37
10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
10.1.6
10.1.7
10.1.8
10.1.9
10.1.10
10.1.11
10.1.12
10.1.13
10.1.14
10.1.15
10.1.16
10.1.17
10.1.18
10.1.19
10.1.20
10.1.21
10.1.22
10.1.23
SSD1322
Enable Gray Scale Table (00h)...................................................................................................................37
Set Column Address (15h) ..........................................................................................................................37
Write RAM Command (5Ch).......................................................................................................................37
Read RAM Command (5Dh) .......................................................................................................................37
Set Row Address (75h) ................................................................................................................................38
Set Re-map & Dual COM Line Mode (A0h) ...............................................................................................39
Set Display Start Line (A1h) .......................................................................................................................42
Set Display Offset (A2h)..............................................................................................................................43
Set Display Mode (A4h ~ A7h)....................................................................................................................44
Enable Partial Display (A8h) .....................................................................................................................45
Exit Partial Display (A9h) ..........................................................................................................................45
Set Function selection (ABh).......................................................................................................................45
Set Display ON/OFF (AEh / AFh) ..............................................................................................................45
Set Phase Length (B1h)...............................................................................................................................45
Set Front Clock Divider / Oscillator Frequency (B3h)...............................................................................45
Display Enhancement A (B4h)....................................................................................................................46
Set GPIO (B5h) ...........................................................................................................................................46
Set Second Pre-charge period (B6h)...........................................................................................................46
Set Gray Scale Table (B8h).........................................................................................................................46
Select Default Linear Gray Scale Table (B9h)............................................................................................46
Set Pre-charge voltage (BBh) .....................................................................................................................46
Set VCOMH Voltage (BEh).............................................................................................................................47
Set Contrast Current (C1h).........................................................................................................................47
Rev 1.2
P 3/60
Jul 2010
Solomon Systech
10.1.24
10.1.25
10.1.26
10.1.27
Master Current Control (C7h)....................................................................................................................47
Set Multiplex Ratio (CAh)...........................................................................................................................47
Display Enhancement B (D1h) ...................................................................................................................47
Set Command Lock (FDh)...........................................................................................................................47
11
MAXIMUM RATINGS........................................................................................................ 48
12
DC CHARACTERISTICS................................................................................................... 49
13
AC CHARACTERISTICS................................................................................................... 50
14
APPLICATION EXAMPLES ............................................................................................. 55
15
PACKAGE INFORMATION.............................................................................................. 57
15.1
15.2
SSD1322
SSD1322UR1 DETAIL DIMENSION ...................................................................................................................57
SSD1322Z2 DIE TRAY INFORMATION..............................................................................................................58
Rev 1.2
P 4/60
Jul 2010
Solomon Systech
TABLES
4. UPDATE TABLE 3-1: SSD1322Z2 BUMP DIE PAD COORDINATES (P.10)........................................................................II
4. UPDATE TABLE 3-2: SSD1322Z2 BUMP DIE PAD COORDINATES (P.10)........................................................................2
TABLE 3-1 : ORDERING INFORMATION ..................................................................................................................................7
TABLE 5-1: SSD1322Z2 BUMP DIE PAD COORDINATES......................................................................................................10
TABLE 6-1: SSD1322UR1 PIN ASSIGNMENT TABLE ...........................................................................................................14
TABLE 7-1: SSD1322 PIN DESCRIPTION ..............................................................................................................................15
TABLE 7-2 : BUS INTERFACE SELECTION .............................................................................................................................15
TABLE 8-1 : MCU INTERFACE ASSIGNMENT UNDER DIFFERENT BUS INTERFACE MODE .......................................................18
TABLE 8-2 : CONTROL PINS OF 6800 INTERFACE..................................................................................................................18
TABLE 8-3 : CONTROL PINS OF 8080 INTERFACE..................................................................................................................20
TABLE 8-4 : CONTROL PINS OF 4-WIRE SERIAL INTERFACE ..................................................................................................20
TABLE 8-5: CONTROL PINS OF 3-WIRE SERIAL INTERFACE...................................................................................................21
TABLE 8-6 : GDDRAM IN GRAY SCALE MODE (RESET) ...................................................................................................22
TABLE 8-7 : DATA BUS USAGE .............................................................................................................................................22
TABLE 9-1 : COMMAND TABLE ............................................................................................................................................32
TABLE 11-1 : MAXIMUM RATINGS ......................................................................................................................................48
TABLE 12-1 : DC CHARACTERISTICS ...................................................................................................................................49
TABLE 13-1 : AC CHARACTERISTICS ...................................................................................................................................50
TABLE 13-2 : 6800-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS..........................................................51
TABLE 13-3 : 8080-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS..........................................................52
TABLE 13-4 : SERIAL INTERFACE TIMING CHARACTERISTICS (4-WIRE SPI) ........................................................................53
TABLE 13-5: SERIAL INTERFACE TIMING CHARACTERISTICS (3-WIRE SPI) .........................................................................54
TABLE 15-1: SSD1322Z2 DIE TRAY DIMENSIONS ..............................................................................................................59
SSD1322
Rev 1.2
P 5/60
Jul 2010
Solomon Systech
FIGURES
FIGURE 4-1 : SSD1322 BLOCK DIAGRAM..............................................................................................................................8
FIGURE 5-1: SSD1322Z2 DIE DRAWING ...............................................................................................................................9
FIGURE 5-2: SSD1322Z2 ALIGNMENT MARK DIMENSION ......................................................................................................9
FIGURE 6-1: SSD1322UR1 PIN ASSIGNMENT .....................................................................................................................13
FIGURE 8-1 : DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ ........................................................................19
FIGURE 8-2 : EXAMPLE OF WRITE PROCEDURE IN 8080 PARALLEL INTERFACE MODE..........................................................19
FIGURE 8-3 : EXAMPLE OF READ PROCEDURE IN 8080 PARALLEL INTERFACE MODE ...........................................................19
FIGURE 8-4 : DISPLAY DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ ..........................................................20
FIGURE 8-5 : WRITE PROCEDURE IN 4-WIRE SERIAL INTERFACE MODE ................................................................................21
FIGURE 8-6: WRITE PROCEDURE IN 3-WIRE SERIAL INTERFACE MODE .................................................................................21
FIGURE 8-7 : OSCILLATOR CIRCUIT .....................................................................................................................................23
FIGURE 8-8 : IREF CURRENT SETTING BY RESISTOR VALUE .................................................................................................24
FIGURE 8-9 : SEGMENT AND COMMON DRIVER BLOCK DIAGRAM – SINGLE COM MODE ...................................................25
FIGURE 8-10 : SEGMENT AND COMMON DRIVER BLOCK DIAGRAM – DUAL COM MODE....................................................26
FIGURE 8-11 : SEGMENT AND COMMON DRIVER SIGNAL WAVEFORM ................................................................................27
FIGURE 8-12 : GRAY SCALE CONTROL BY PWM IN SEGMENT ............................................................................................28
FIGURE 8-13 : RELATION BETWEEN GDDRAM CONTENT AND GRAY SCALE TABLE ENTRY (UNDER COMMAND B9H
ENABLE LINEAR GRAY SCALE TABLE)........................................................................................................................29
FIGURE 8-14 : THE POWER ON SEQUENCE...........................................................................................................................30
FIGURE 8-15 : THE POWER OFF SEQUENCE .........................................................................................................................30
FIGURE 8-16 VCI > 2.6V, VDD REGULATOR ENABLE PIN CONNECTION SCHEME....................................................................31
FIGURE 8-17 VDD REGULATOR DISABLE PIN CONNECTION SCHEME .....................................................................................31
FIGURE 10-110-2 : EXAMPLE OF COLUMN AND ROW ADDRESS POINTER MOVEMENT (GRAY SCALE MODE) .....................38
FIGURE 10-3 : ADDRESS POINTER MOVEMENT OF HORIZONTAL ADDRESS INCREMENT MODE ...........................................39
FIGURE 10-4: ADDRESS POINTER MOVEMENT OF VERTICAL ADDRESS INCREMENT MODE.................................................39
FIGURE 10-5: GDDRAM IN GRAY SCALE MODE WITH OR WITHOUT COLUMN ADDRESS (A[1]) & NIBBLE REMAPPING (A[2])
....................................................................................................................................................................................40
FIGURE 10-6 : COM PINS HARDWARE CONFIGURATION – 1 (MUX RATIO: 128).................................................................41
FIGURE 10-7 : COM PINS HARDWARE CONFIGURATION – 2 (MUX RATIO: 64)...................................................................41
FIGURE 10-8 : EXAMPLE OF SET DISPLAY START LINE WITH NO REMAP .............................................................................42
FIGURE 10-9 : EXAMPLE OF SET DISPLAY OFFSET WITH NO REMAP ...................................................................................43
FIGURE 10-10 : EXAMPLE OF NORMAL DISPLAY .................................................................................................................44
FIGURE 10-11 : EXAMPLE OF ENTIRE DISPLAY ON .............................................................................................................44
FIGURE 10-12 : EXAMPLE OF ENTIRE DISPLAY OFF............................................................................................................44
FIGURE 10-13 : EXAMPLE OF INVERSE DISPLAY ..................................................................................................................44
FIGURE 10-14 : EXAMPLE OF PARTIAL MODE DISPLAY .......................................................................................................45
FIGURE 10-15 : EXAMPLE OF GAMMA CORRECTION BY GAMMA LOOK UP TABLE SETTING.................................................46
FIGURE 13-1 : 6800-SERIES MCU PARALLEL INTERFACE CHARACTERISTICS .......................................................................51
FIGURE 13-2 : 8080-SERIES MCU PARALLEL INTERFACE CHARACTERISTICS .......................................................................52
FIGURE 13-3 : SERIAL INTERFACE CHARACTERISTICS (4-WIRE SPI).....................................................................................53
FIGURE 13-4: SERIAL INTERFACE CHARACTERISTICS (3-WIRE SPI) .....................................................................................54
FIGURE 14-1 : SSD1322 APPLICATION EXAMPLE FOR 8-BIT 6800-PARALLEL INTERFACE MODE (INTERNAL REGULATED VDD)
....................................................................................................................................................................................55
FIGURE 14-2 : SSD1322 APPLICATION EXAMPLE FOR 8-BIT 6800-PARALLEL INTERFACE, DUAL COM MODE (INTERNAL VDD)
....................................................................................................................................................................................56
FIGURE 15-1: SSD1322UR1 DETAIL DIMENSION ...............................................................................................................57
FIGURE 15-2: SSD1322Z2 DIE TRAY DRAWING .................................................................................................................58
SSD1322
Rev 1.2
P 6/60
Jul 2010
Solomon Systech
1
GENERAL DESCRIPTION
SSD1322 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light emitting diode
dot-matrix graphic display system. It consists of 480 segments and 128 commons. This IC is designed for
Common Cathode type OLED/PLED panel.
SSD1322 displays data directly from its internal 480 x 128 x 4 bits Graphic Display Data RAM (GDDRAM).
Data/Commands are sent from general MCU through the hardware selectable 6800-/8080-series compatible
Parallel Interface or Serial Peripheral Interface. This driver IC has a 256 steps contrast control and can be
widely used in many applications such as automotive and industrial control panel.
2
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
3
Resolution: 480 x 128 dot matrix panel
Power supply
o VDD = 2.4V – 2.6V
(Core VDD power supply, can be regulated from VCI)
o VDDIO = 1.65V – VCI
(MCU interface logic level)
(Low voltage power supply)
o VCI = 2.4V - 3.5V
o VCC = 10.0V – 20.0V
(Panel driving power supply)
When VCI is lower than 2.6V, VDD should be supplied by external power source
For matrix display
o Segment maximum source current: 300uA
o Common maximum sink current: 80mA
o 256 step contrast brightness current control, 16 step master current control
16 gray scale levels supported by embedded 480 x 128 x 4 bit SRAM display buffer
Selectable MCU Interfaces:
o 8-bit 6800/8080-series parallel interface
o 3/4-wire Serial Peripheral Interface
Selectable Common current sinking mode:
o Dual COM mode
o Single COM mode
8-bit programmable Gray Scale Look Up Table
High Power Protection
Programmable Frame Rate and Multiplexing Ratio
Row re-mapping and Column re-mapping
Sleep mode current <10uA with ram data kept
Operating temperature range -40°C to 85°C.
ORDERING INFORMATION
Table 3-1 : Ordering Information
Ordering
Part Number
SEG
COM
Package
Form
SSD1322Z2
480
128
Gold
bump Die
SSD1322UR1
256
64
(dual
COM)
COF
SSD1322
Rev 1.2
P 7/60
Jul 2010
Reference
Remark
•
•
•
•
•
Page 13, 57 •
•
Page 9
Min SEG pitch: 25um
Min COM pitch: 35um
Die thickness: 300 +/- 15um
70mm film, 5 SPH
8-bit 80/68/SPI interfaces
SEG, COM lead pitch 0.12mm x 0.999 = 0.11988mm
Also support 128 MUX (single COM)
• Die thickness: 457 +/- 25um
Solomon Systech
4
BLOCK DIAGRAM
Figure 4-1 : SSD1322 Block Diagram
VCI
GDDRAM
MCU
Interface
BS0
BS1
SSD1322
Rev 1.2
P 8/60
(even)
(odd)
.
.
.
.
.
.
.
.
.
.
.
COM126
COM124
|
|
COM2
COM0
SEG0
SEG1
|
|
SEG478
SEG479
COM1
COM3
|
|
COM125
COM127
IREF
SEG/COM Driving
Block
VCOMH
M/S#
Display
Timing
Generator
Jul 2010
FR
DOF#
CL
CLS
Command
Decoder
GPIO0
GPIO1
Oscillator
VDDIO
VCC
VCI
VDD1
VSS
VLSS
VSL
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Segment Drivers
D7
D6
D5
D4
D3
D2
D1
D0
Gray Scale Decoder
RES#
CS#
D/C#
R/W# (WR#)
E(RD#)
Common Drivers
VDD Regulator
Common Drivers
BGGND
VDD
Solomon Systech
5
DIE PAD FLOOR PLAN
Figure 5-1: SSD1322Z2 Die Drawing
Die size
Die thickness
Min I/O pad pitch
Min SEG pad pitch
Min COM pad pitch
Bump height
12.4 mm ± 0.05mm x 1.53 mm ± 0.05mm
300 +/- 15um
70um
25um
35um
Nominal 15um
Bump size
Pad#
1-48, 146-193
195-216, 706-727
49-145
194, 728
217, 705
218, 704
219-703
Alignment
mark
+ shape
+ shape
SSL Logo
X[um]
26
60
45
60
50
50
16
Y[um]
60
26
90
50
50
96
96
Position
Size
(5583.95,200.78)
(-5634.61,-309.88)
(-5682.11,-258.98)
75um x 75um
75um x 75um
-
(For details dimension please see Figure 5-2)
Y
X
SSD1322Z2
Pad 1,2,3,…->728
Gold Bumps face up
Figure 5-2: SSD1322Z2 alignment mark dimension
25 25
25 25 25
15
15 10
10
25
15
15
Center:
Size:
SSD1322
Rev 1.2
P 9/60
Jul 2010
(-5364.61, -309.88)
75 x 75 μm2
Center:
Size:
(5583.95, 200.78)
75 x 75 μm2
Solomon Systech
Table 5-1: SSD1322Z2 Bump Die Pad Coordinates
Pad no.
Pin name
X-pos
Y-pos
Pad no.
Pin name
X-pos
Y-pos
Pad no.
Pin name
X-pos
Y-pos
Pad no.
Pin name
X-pos
Y-pos
1
VLSS
-5833.06
-664.06
81
RES#
-1381.06
-654.15
161
COM50
4708.06
-664.06
241
SEG22
5500
687.81
2
VLSS
-5798.06
-664.06
82
CS#
-1311.06
-654.15
162
COM49
4743.06
-664.06
242
SEG23
5475
687.81
3
COM84
-5758.06
-664.06
83
D/C#
-1241.06
-654.15
163
COM48
4778.06
-664.06
243
SEG24
5450
687.81
4
COM85
-5723.06
-664.06
84
VSS
-1171.06
-654.15
164
COM47
4813.06
-664.06
244
SEG25
5425
687.81
5
COM86
-5688.06
-664.06
85
BS1
-1101.06
-654.15
165
COM46
4848.06
-664.06
245
SEG26
5400
687.81
6
COM87
-5653.06
-664.06
86
VDDIO
-1031.06
-654.15
166
COM45
4883.06
-664.06
246
SEG27
5375
687.81
7
COM88
-5618.06
-664.06
87
BS0
-961.06
-654.15
167
COM44
4918.06
-664.06
247
SEG28
5350
687.81
8
COM89
-5583.06
-664.06
88
VSS
-891.06
-654.15
168
COM43
4953.06
-664.06
248
SEG29
5325
687.81
9
COM90
-5548.06
-664.06
89
R/W#(WR#)
-821.06
-654.15
169
COM42
4988.06
-664.06
249
SEG30
5300
687.81
10
COM91
-5513.06
-664.06
90
E(RD#)
-751.06
-654.15
170
COM41
5023.06
-664.06
250
SEG31
5275
687.81
11
COM92
-5478.06
-664.06
91
VDDIO
-681.06
-654.15
171
COM40
5058.06
-664.06
251
SEG32
5250
687.81
12
COM93
-5443.06
-664.06
92
VDD1
-528.06
-654.15
172
COM39
5093.06
-664.06
252
SEG33
5225
687.81
13
COM94
-5408.06
-664.06
93
VDD1
-458.06
-654.15
173
COM38
5128.06
-664.06
253
SEG34
5200
687.81
14
COM95
-5373.06
-664.06
94
VDD1
-388.06
-654.15
174
COM37
5163.06
-664.06
254
SEG35
5175
687.81
15
COM96
-5338.06
-664.06
95
VDD
-290.06
-654.15
175
COM36
5198.06
-664.06
255
SEG36
5150
687.81
16
COM97
-5303.06
-664.06
96
VDD
-220.06
-654.15
176
COM35
5233.06
-664.06
256
SEG37
5125
687.81
17
COM98
-5268.06
-664.06
97
VDD
-150.06
-654.15
177
COM34
5268.06
-664.06
257
SEG38
5100
687.81
18
COM99
-5233.06
-664.06
98
NC
-36.06
-654.15
178
COM33
5303.06
-664.06
258
SEG39
5075
687.81
19
COM100
-5198.06
-664.06
99
NC
33.94
-654.15
179
COM32
5338.06
-664.06
259
SEG40
5050
687.81
20
COM101
-5163.06
-664.06
100
NC
103.94
-654.15
180
COM31
5373.06
-664.06
260
SEG41
5025
687.81
21
COM102
-5128.06
-664.06
101
VCI
217.94
-654.15
181
COM30
5408.06
-664.06
261
SEG42
5000
687.81
22
COM103
-5093.06
-664.06
102
D0
309.94
-654.15
182
COM29
5443.06
-664.06
262
SEG43
4975
687.81
23
COM104
-5058.06
-664.06
103
D1
395.94
-654.15
183
COM28
5478.06
-664.06
263
SEG44
4950
687.81
24
COM105
-5023.06
-664.06
104
D2
505.94
-654.15
184
COM27
5513.06
-664.06
264
SEG45
4925
687.81
25
COM106
-4988.06
-664.06
105
D3
591.94
-654.15
185
COM26
5548.06
-664.06
265
SEG46
4900
687.81
26
COM107
-4953.06
-664.06
106
D4
701.94
-654.15
186
COM25
5583.06
-664.06
266
SEG47
4875
687.81
27
COM108
-4918.06
-664.06
107
D5
787.94
-654.15
187
COM24
5618.06
-664.06
267
SEG48
4850
687.81
28
COM109
-4883.06
-664.06
108
D6
897.94
-654.15
188
COM23
5653.06
-664.06
268
SEG49
4825
687.81
29
COM110
-4848.06
-664.06
109
D7
983.94
-654.15
189
COM22
5688.06
-664.06
269
SEG50
4800
687.81
30
COM111
-4813.06
-664.06
110
DN0
1093.94
-654.15
190
COM21
5723.06
-664.06
270
SEG51
4775
687.81
31
COM112
-4778.06
-664.06
111
DN1
1179.94
-654.15
191
COM20
5758.06
-664.06
271
SEG52
4750
687.81
32
COM113
-4743.06
-664.06
112
DN2
1289.94
-654.15
192
VLSS
5793.06
-664.06
272
SEG53
4725
687.81
33
COM114
-4708.06
-664.06
113
DN3
1375.94
-654.15
193
VLSS
5828.06
-664.06
273
SEG54
4700
687.81
34
COM115
-4673.06
-664.06
114
DN4
1485.94
-654.15
194
VLSS
6087.34
-674.56
274
SEG55
4675
687.81
35
COM116
-4638.06
-664.06
115
DN5
1571.94
-654.15
195
COM19
6087.34
-627.06
275
SEG56
4650
687.81
36
COM117
-4603.06
-664.06
116
DN6
1681.94
-654.15
196
COM18
6087.34
-592.06
276
SEG57
4625
687.81
37
COM118
-4568.06
-664.06
117
DN7
1767.94
-654.15
197
COM17
6087.34
-557.06
277
SEG58
4600
687.81
38
COM119
-4533.06
-664.06
118
DN8
1877.94
-654.15
198
COM16
6087.34
-522.06
278
SEG59
4575
687.81
39
COM120
-4498.06
-664.06
119
DN9
1963.94
-654.15
199
COM15
6087.34
-487.06
279
SEG60
4550
687.81
40
COM121
-4463.06
-664.06
120
VSS
2055.94
-654.15
200
COM14
6087.34
-452.06
280
SEG61
4525
687.81
41
COM122
-4428.06
-664.06
121
BGGND
2125.94
-654.15
201
COM13
6087.34
-417.06
281
SEG62
4500
687.81
42
COM123
-4393.06
-664.06
122
MS
2195.94
-654.15
202
COM12
6087.34
-382.06
282
SEG63
4475
687.81
43
COM124
-4358.06
-664.06
123
CLS
2265.94
-654.15
203
COM11
6087.34
-347.06
283
SEG64
4450
687.81
44
COM125
-4323.06
-664.06
124
VSL
2335.94
-654.15
204
COM10
6087.34
-312.06
284
SEG65
4425
687.81
45
COM126
-4288.06
-664.06
125
VSL
2405.94
-654.15
205
COM9
6087.34
-277.06
285
SEG66
4400
687.81
46
COM127
-4253.06
-664.06
126
VCI
2475.94
-654.15
206
COM8
6087.34
-242.06
286
SEG67
4375
687.81
47
VLSS
-4218.06
-664.06
127
VDDIO
2628.94
-654.15
207
COM7
6087.34
-207.06
287
SEG68
4350
687.81
48
VLSS
-4183.06
-664.06
128
VDDIO
2698.94
-654.15
208
COM6
6087.34
-172.06
288
SEG69
4325
687.81
49
VSS
-4033.06
-654.15
129
VDD
2768.94
-654.15
209
COM5
6087.34
-137.06
289
SEG70
4300
687.81
50
VSS
-3963.06
-654.15
130
NC
2878.94
-654.15
210
COM4
6087.34
-102.06
290
SEG71
4275
687.81
51
VCC
-3874.06
-654.15
131
VSS
2948.94
-654.15
211
COM3
6087.34
-67.06
291
SEG72
4250
687.81
52
VCC
-3804.06
-654.15
132
VSS
3018.94
-654.15
212
COM2
6087.34
-32.06
292
SEG73
4225
687.81
53
VCOMH
-3697.06
-654.15
133
VLSS
3088.94
-654.15
213
COM1
6087.34
2.94
293
SEG74
4200
687.81
54
VCOMH
-3627.06
-654.15
134
VLSS
3158.94
-654.15
214
COM0
6087.34
37.94
294
SEG75
4175
687.81
687.81
55
VLSS
-3557.06
-654.15
135
VCOMH
3228.94
-654.15
215
VLSS
6087.34
72.94
295
SEG76
4150
56
VLSS
-3487.06
-654.15
136
VCOMH
3298.94
-654.15
216
VLSS
6087.34
107.94
296
SEG77
4125
687.81
57
VSS
-3417.06
-654.15
137
VCC
3405.94
-654.15
217
VSL
6097.34
311.09
297
SEG78
4100
687.81
58
VSS
-3347.06
-654.15
138
VCC
3475.94
-654.15
218
VCC
6097.34
687.81
298
SEG79
4075
687.81
59
VSL
-3277.06
-654.15
139
VSS
3572.94
-654.15
219
SEG0
6050
687.81
299
SEG80
4050
687.81
60
VSL
-3207.06
-654.15
140
VSS
3642.94
-654.15
220
SEG1
6025
687.81
300
SEG81
4025
687.81
61
VCI
-3137.06
-654.15
141
VSS
3712.94
-654.15
221
SEG2
6000
687.81
301
SEG82
4000
687.81
62
VCI
-3067.06
-654.15
142
VSS
3782.94
-654.15
222
SEG3
5975
687.81
302
SEG83
3975
687.81
63
VDD1
-2914.06
-654.15
143
VSS
3852.94
-654.15
223
SEG4
5950
687.81
303
SEG84
3950
687.81
64
VDD1
-2844.06
-654.15
144
VSS
3922.94
-654.15
224
SEG5
5925
687.81
304
SEG85
3925
687.81
65
VDD
-2746.06
-654.15
145
VSS
3992.94
-654.15
225
SEG6
5900
687.81
305
SEG86
3900
687.81
66
VDD
-2676.06
-654.15
146
VLSS
4183.06
-664.06
226
SEG7
5875
687.81
306
SEG87
3875
687.81
67
VDD
-2606.06
-654.15
147
VLSS
4218.06
-664.06
227
SEG8
5850
687.81
307
SEG88
3850
687.81
68
VDDIO
-2453.06
-654.15
148
COM63
4253.06
-664.06
228
SEG9
5825
687.81
308
SEG89
3825
687.81
69
VDDIO
-2383.06
-654.15
149
COM62
4288.06
-664.06
229
SEG10
5800
687.81
309
SEG90
3800
687.81
70
VDD
-2313.06
-654.15
150
COM61
4323.06
-664.06
230
SEG11
5775
687.81
310
SEG91
3775
687.81
71
VLSS
-2243.06
-654.15
151
COM60
4358.06
-664.06
231
SEG12
5750
687.81
311
SEG92
3750
687.81
72
GPIO0
-2151.06
-654.15
152
COM59
4393.06
-664.06
232
SEG13
5725
687.81
312
SEG93
3725
687.81
73
GPIO1
-2065.06
-654.15
153
COM58
4428.06
-664.06
233
SEG14
5700
687.81
313
SEG94
3700
687.81
74
IREF
-1973.06
-654.15
154
COM57
4463.06
-664.06
234
SEG15
5675
687.81
314
SEG95
3675
687.81
75
FR
-1881.06
-654.15
155
COM56
4498.06
-664.06
235
SEG16
5650
687.81
315
SEG96
3650
687.81
76
CL
-1795.06
-654.15
156
COM55
4533.06
-664.06
236
SEG17
5625
687.81
316
SEG97
3625
687.81
77
VSS
-1703.06
-654.15
157
COM54
4568.06
-664.06
237
SEG18
5600
687.81
317
SEG98
3600
687.81
78
DOF#
-1611.06
-654.15
158
COM53
4603.06
-664.06
238
SEG19
5575
687.81
318
SEG99
3575
687.81
79
NC
-1521.06
-654.15
159
COM52
4638.06
-664.06
239
SEG20
5550
687.81
319
SEG100
3550
687.81
80
VSS
-1451.06
-654.15
160
COM51
4673.06
-664.06
240
SEG21
5525
687.81
320
SEG101
3525
687.81
SSD1322
Rev 1.2
P 10/60 Jul 2010
Solomon Systech
Pad no.
Pin name
X-pos
Y-pos
Pad no.
Pin name
X-pos
Y-pos
Pad no.
Pin name
X-pos
Y-pos
Pad no.
Pin name
X-pos
Y-pos
321
SEG102
3500
687.81
401
SEG182
1500
687.81
481
SEG257
-500
687.81
561
SEG337
-2500
687.81
322
SEG103
3475
687.81
402
SEG183
1475
687.81
482
SEG258
-525
687.81
562
SEG338
-2525
687.81
323
SEG104
3450
687.81
403
SEG184
1450
687.81
483
SEG259
-550
687.81
563
SEG339
-2550
687.81
324
SEG105
3425
687.81
404
SEG185
1425
687.81
484
SEG260
-575
687.81
564
SEG340
-2575
687.81
325
SEG106
3400
687.81
405
SEG186
1400
687.81
485
SEG261
-600
687.81
565
SEG341
-2600
687.81
326
SEG107
3375
687.81
406
SEG187
1375
687.81
486
SEG262
-625
687.81
566
SEG342
-2625
687.81
327
SEG108
3350
687.81
407
SEG188
1350
687.81
487
SEG263
-650
687.81
567
SEG343
-2650
687.81
328
SEG109
3325
687.81
408
SEG189
1325
687.81
488
SEG264
-675
687.81
568
SEG344
-2675
687.81
329
SEG110
3300
687.81
409
SEG190
1300
687.81
489
SEG265
-700
687.81
569
SEG345
-2700
687.81
330
SEG111
3275
687.81
410
SEG191
1275
687.81
490
SEG266
-725
687.81
570
SEG346
-2725
687.81
331
SEG112
3250
687.81
411
SEG192
1250
687.81
491
SEG267
-750
687.81
571
SEG347
-2750
687.81
332
SEG113
3225
687.81
412
SEG193
1225
687.81
492
SEG268
-775
687.81
572
SEG348
-2775
687.81
333
SEG114
3200
687.81
413
SEG194
1200
687.81
493
SEG269
-800
687.81
573
SEG349
-2800
687.81
334
SEG115
3175
687.81
414
SEG195
1175
687.81
494
SEG270
-825
687.81
574
SEG350
-2825
687.81
335
SEG116
3150
687.81
415
SEG196
1150
687.81
495
SEG271
-850
687.81
575
SEG351
-2850
687.81
336
SEG117
3125
687.81
416
SEG197
1125
687.81
496
SEG272
-875
687.81
576
SEG352
-2875
687.81
337
SEG118
3100
687.81
417
SEG198
1100
687.81
497
SEG273
-900
687.81
577
SEG353
-2900
687.81
338
SEG119
3075
687.81
418
SEG199
1075
687.81
498
SEG274
-925
687.81
578
SEG354
-2925
687.81
339
SEG120
3050
687.81
419
SEG200
1050
687.81
499
SEG275
-950
687.81
579
SEG355
-2950
687.81
340
SEG121
3025
687.81
420
SEG201
1025
687.81
500
SEG276
-975
687.81
580
SEG356
-2975
687.81
341
SEG122
3000
687.81
421
SEG202
1000
687.81
501
SEG277
-1000
687.81
581
SEG357
-3000
687.81
342
SEG123
2975
687.81
422
SEG203
975
687.81
502
SEG278
-1025
687.81
582
SEG358
-3025
687.81
343
SEG124
2950
687.81
423
SEG204
950
687.81
503
SEG279
-1050
687.81
583
SEG359
-3050
687.81
344
SEG125
2925
687.81
424
SEG205
925
687.81
504
SEG280
-1075
687.81
584
SEG360
-3075
687.81
345
SEG126
2900
687.81
425
SEG206
900
687.81
505
SEG281
-1100
687.81
585
SEG361
-3100
687.81
346
SEG127
2875
687.81
426
SEG207
875
687.81
506
SEG282
-1125
687.81
586
SEG362
-3125
687.81
347
SEG128
2850
687.81
427
SEG208
850
687.81
507
SEG283
-1150
687.81
587
SEG363
-3150
687.81
348
SEG129
2825
687.81
428
SEG209
825
687.81
508
SEG284
-1175
687.81
588
SEG364
-3175
687.81
349
SEG130
2800
687.81
429
SEG210
800
687.81
509
SEG285
-1200
687.81
589
SEG365
-3200
687.81
350
SEG131
2775
687.81
430
SEG211
775
687.81
510
SEG286
-1225
687.81
590
SEG366
-3225
687.81
351
SEG132
2750
687.81
431
SEG212
750
687.81
511
SEG287
-1250
687.81
591
SEG367
-3250
687.81
352
SEG133
2725
687.81
432
SEG213
725
687.81
512
SEG288
-1275
687.81
592
SEG368
-3275
687.81
353
SEG134
2700
687.81
433
SEG214
700
687.81
513
SEG289
-1300
687.81
593
SEG369
-3300
687.81
354
SEG135
2675
687.81
434
SEG215
675
687.81
514
SEG290
-1325
687.81
594
SEG370
-3325
687.81
355
SEG136
2650
687.81
435
SEG216
650
687.81
515
SEG291
-1350
687.81
595
SEG371
-3350
687.81
356
SEG137
2625
687.81
436
SEG217
625
687.81
516
SEG292
-1375
687.81
596
SEG372
-3375
687.81
357
SEG138
2600
687.81
437
SEG218
600
687.81
517
SEG293
-1400
687.81
597
SEG373
-3400
687.81
358
SEG139
2575
687.81
438
SEG219
575
687.81
518
SEG294
-1425
687.81
598
SEG374
-3425
687.81
359
SEG140
2550
687.81
439
SEG220
550
687.81
519
SEG295
-1450
687.81
599
SEG375
-3450
687.81
360
SEG141
2525
687.81
440
SEG221
525
687.81
520
SEG296
-1475
687.81
600
SEG376
-3475
687.81
361
SEG142
2500
687.81
441
SEG222
500
687.81
521
SEG297
-1500
687.81
601
SEG377
-3500
687.81
362
SEG143
2475
687.81
442
SEG223
475
687.81
522
SEG298
-1525
687.81
602
SEG378
-3525
687.81
363
SEG144
2450
687.81
443
SEG224
450
687.81
523
SEG299
-1550
687.81
603
SEG379
-3550
687.81
364
SEG145
2425
687.81
444
SEG225
425
687.81
524
SEG300
-1575
687.81
604
SEG380
-3575
687.81
365
SEG146
2400
687.81
445
SEG226
400
687.81
525
SEG301
-1600
687.81
605
SEG381
-3600
687.81
366
SEG147
2375
687.81
446
SEG227
375
687.81
526
SEG302
-1625
687.81
606
SEG382
-3625
687.81
367
SEG148
2350
687.81
447
SEG228
350
687.81
527
SEG303
-1650
687.81
607
SEG383
-3650
687.81
368
SEG149
2325
687.81
448
SEG229
325
687.81
528
SEG304
-1675
687.81
608
SEG384
-3675
687.81
369
SEG150
2300
687.81
449
SEG230
300
687.81
529
SEG305
-1700
687.81
609
SEG385
-3700
687.81
370
SEG151
2275
687.81
450
SEG231
275
687.81
530
SEG306
-1725
687.81
610
SEG386
-3725
687.81
371
SEG152
2250
687.81
451
SEG232
250
687.81
531
SEG307
-1750
687.81
611
SEG387
-3750
687.81
372
SEG153
2225
687.81
452
SEG233
225
687.81
532
SEG308
-1775
687.81
612
SEG388
-3775
687.81
373
SEG154
2200
687.81
453
SEG234
200
687.81
533
SEG309
-1800
687.81
613
SEG389
-3800
687.81
374
SEG155
2175
687.81
454
SEG235
175
687.81
534
SEG310
-1825
687.81
614
SEG390
-3825
687.81
375
SEG156
2150
687.81
455
SEG236
150
687.81
535
SEG311
-1850
687.81
615
SEG391
-3850
687.81
376
SEG157
2125
687.81
456
SEG237
125
687.81
536
SEG312
-1875
687.81
616
SEG392
-3875
687.81
377
SEG158
2100
687.81
457
SEG238
100
687.81
537
SEG313
-1900
687.81
617
SEG393
-3900
687.81
378
SEG159
2075
687.81
458
SEG239
75
687.81
538
SEG314
-1925
687.81
618
SEG394
-3925
687.81
379
SEG160
2050
687.81
459
VCC
50
687.81
539
SEG315
-1950
687.81
619
SEG395
-3950
687.81
380
SEG161
2025
687.81
460
VCC
25
687.81
540
SEG316
-1975
687.81
620
SEG396
-3975
687.81
381
SEG162
2000
687.81
461
VCC
0
687.81
541
SEG317
-2000
687.81
621
SEG397
-4000
687.81
382
SEG163
1975
687.81
462
VCC
-25
687.81
542
SEG318
-2025
687.81
622
SEG398
-4025
687.81
383
SEG164
1950
687.81
463
VCC
-50
687.81
543
SEG319
-2050
687.81
623
SEG399
-4050
687.81
384
SEG165
1925
687.81
464
SEG240
-75
687.81
544
SEG320
-2075
687.81
624
SEG400
-4075
687.81
385
SEG166
1900
687.81
465
SEG241
-100
687.81
545
SEG321
-2100
687.81
625
SEG401
-4100
687.81
386
SEG167
1875
687.81
466
SEG242
-125
687.81
546
SEG322
-2125
687.81
626
SEG402
-4125
687.81
387
SEG168
1850
687.81
467
SEG243
-150
687.81
547
SEG323
-2150
687.81
627
SEG403
-4150
687.81
388
SEG169
1825
687.81
468
SEG244
-175
687.81
548
SEG324
-2175
687.81
628
SEG404
-4175
687.81
389
SEG170
1800
687.81
469
SEG245
-200
687.81
549
SEG325
-2200
687.81
629
SEG405
-4200
687.81
390
SEG171
1775
687.81
470
SEG246
-225
687.81
550
SEG326
-2225
687.81
630
SEG406
-4225
687.81
391
SEG172
1750
687.81
471
SEG247
-250
687.81
551
SEG327
-2250
687.81
631
SEG407
-4250
687.81
392
SEG173
1725
687.81
472
SEG248
-275
687.81
552
SEG328
-2275
687.81
632
SEG408
-4275
687.81
393
SEG174
1700
687.81
473
SEG249
-300
687.81
553
SEG329
-2300
687.81
633
SEG409
-4300
687.81
394
SEG175
1675
687.81
474
SEG250
-325
687.81
554
SEG330
-2325
687.81
634
SEG410
-4325
687.81
395
SEG176
1650
687.81
475
SEG251
-350
687.81
555
SEG331
-2350
687.81
635
SEG411
-4350
687.81
396
SEG177
1625
687.81
476
SEG252
-375
687.81
556
SEG332
-2375
687.81
636
SEG412
-4375
687.81
397
SEG178
1600
687.81
477
SEG253
-400
687.81
557
SEG333
-2400
687.81
637
SEG413
-4400
687.81
398
SEG179
1575
687.81
478
SEG254
-425
687.81
558
SEG334
-2425
687.81
638
SEG414
-4425
687.81
399
SEG180
1550
687.81
479
SEG255
-450
687.81
559
SEG335
-2450
687.81
639
SEG415
-4450
687.81
400
SEG181
1525
687.81
480
SEG256
-475
687.81
560
SEG336
-2475
687.81
640
SEG416
-4475
687.81
SSD1322
Rev 1.2
P 11/60 Jul 2010
Solomon Systech
Pad no.
Pin name
X-pos
Y-pos
Pad no.
Pin name
X-pos
Y-pos
641
SEG417
-4500
687.81
721
COM77
-6087.34
-417.06
642
SEG418
-4525
687.81
722
COM78
-6087.34
-452.06
643
SEG419
-4550
687.81
723
COM79
-6087.34
-487.06
644
SEG420
-4575
687.81
724
COM80
-6087.34
-522.06
645
SEG421
-4600
687.81
725
COM81
-6087.34
-557.06
646
SEG422
-4625
687.81
726
COM82
-6087.34
-592.06
647
SEG423
-4650
687.81
727
COM83
-6087.34
-627.06
648
SEG424
-4675
687.81
728
VLSS
-6087.34
-674.56
649
SEG425
-4700
687.81
650
SEG426
-4725
687.81
651
SEG427
-4750
687.81
652
SEG428
-4775
687.81
653
SEG429
-4800
687.81
654
SEG430
-4825
687.81
655
SEG431
-4850
687.81
656
SEG432
-4875
687.81
657
SEG433
-4900
687.81
658
SEG434
-4925
687.81
659
SEG435
-4950
687.81
660
SEG436
-4975
687.81
661
SEG437
-5000
687.81
662
SEG438
-5025
687.81
663
SEG439
-5050
687.81
664
SEG440
-5075
687.81
665
SEG441
-5100
687.81
666
SEG442
-5125
687.81
667
SEG443
-5150
687.81
668
SEG444
-5175
687.81
669
SEG445
-5200
687.81
670
SEG446
-5225
687.81
671
SEG447
-5250
687.81
672
SEG448
-5275
687.81
673
SEG449
-5300
687.81
674
SEG450
-5325
687.81
675
SEG451
-5350
687.81
676
SEG452
-5375
687.81
677
SEG453
-5400
687.81
678
SEG454
-5425
687.81
679
SEG455
-5450
687.81
680
SEG456
-5475
687.81
681
SEG457
-5500
687.81
682
SEG458
-5525
687.81
683
SEG459
-5550
687.81
684
SEG460
-5575
687.81
685
SEG461
-5600
687.81
686
SEG462
-5625
687.81
687
SEG463
-5650
687.81
688
SEG464
-5675
687.81
689
SEG465
-5700
687.81
690
SEG466
-5725
687.81
691
SEG467
-5750
687.81
692
SEG468
-5775
687.81
693
SEG469
-5800
687.81
694
SEG470
-5825
687.81
695
SEG471
-5850
687.81
696
SEG472
-5875
687.81
697
SEG473
-5900
687.81
698
SEG474
-5925
687.81
699
SEG475
-5950
687.81
700
SEG476
-5975
687.81
701
SEG477
-6000
687.81
702
SEG478
-6025
687.81
703
SEG479
-6050
687.81
704
VCC
-6097.34
687.81
705
VSL
-6097.34
311.09
706
VLSS
-6087.34
107.94
707
VLSS
-6087.34
72.94
708
COM64
-6087.34
37.94
709
COM65
-6087.34
2.94
710
COM66
-6087.34
-32.06
711
COM67
-6087.34
-67.06
712
COM68
-6087.34
-102.06
713
COM69
-6087.34
-137.06
714
COM70
-6087.34
-172.06
715
COM71
-6087.34
-207.06
716
COM72
-6087.34
-242.06
717
COM73
-6087.34
-277.06
718
COM74
-6087.34
-312.06
719
COM75
-6087.34
-347.06
720
COM76
-6087.34
-382.06
SSD1322
Rev 1.2
P 12/60 Jul 2010
Solomon Systech
6
6.1
PIN ARRANGEMENT
SSD1322UR1 pin assignment
Figure 6-1: SSD1322UR1 Pin Assignment
Note:
(1)
COM sequence is listed in terms of dual COM mode; refer to Table 9-1 for details.
SSD1322
Rev 1.2
P 13/60 Jul 2010
Solomon Systech
Table 6-1: SSD1322UR1 Pin Assignment Table
Pad no.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SSD1322
Pin name
NC
VSS
VCC
VCOMH
VLSS
D7
D6
D5
D4
D3
D2
D1
D0
E/RD#
RW#
BS0
BS1
DC#
CS#
RES#
FR
IREF
NC
VDDIO
VDD
VCI
VSL
VLSS
VCC
NC
NC
NC
COMB63
COMB62
COMB61
COMB60
COMB59
COMB58
COMB57
COMB56
COMB55
COMB54
COMB53
COMB52
COMB51
COMB50
COMB49
COMB48
COMB47
COMB46
COMB45
COMB44
COMB43
COMB42
COMB41
COMB40
COMB39
COMB38
COMB37
COMB36
COMB35
COMB34
COMB33
COMB32
COMB31
COMB30
COMB29
COMB28
COMB27
COMB26
COMB25
COMB24
COMB23
COMB22
COMB21
COMB20
COMB19
COMB18
COMB17
COMB16
Pad no.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Rev 1.2
Pin name
COMB15
COMB14
COMB13
COMB12
COMB11
COMB10
COMB9
COMB8
COMB7
COMB6
COMB5
COMB4
COMB3
COMB2
COMB1
COMB0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SEG255
SEG254
SEG253
SEG252
SEG251
SEG250
SEG249
SEG248
SEG247
SEG246
SEG245
SEG244
SEG243
SEG242
SEG241
SEG240
SEG239
SEG238
SEG237
SEG236
SEG235
SEG234
SEG233
SEG232
SEG231
SEG230
SEG229
SEG228
SEG227
SEG226
SEG225
SEG224
SEG223
SEG222
SEG221
SEG220
SEG219
SEG218
SEG217
SEG216
SEG215
SEG214
SEG213
SEG212
SEG211
SEG210
SEG209
SEG208
SEG207
Pad no.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
P 14/60 Jul 2010
Pin name
SEG206
SEG205
SEG204
SEG203
SEG202
SEG201
SEG200
SEG199
SEG198
SEG197
SEG196
SEG195
SEG194
SEG193
SEG192
SEG191
SEG190
SEG189
SEG188
SEG187
SEG186
SEG185
SEG184
SEG183
SEG182
SEG181
SEG180
SEG179
SEG178
SEG177
SEG176
SEG175
SEG174
SEG173
SEG172
SEG171
SEG170
SEG169
SEG168
SEG167
SEG166
SEG165
SEG164
SEG163
SEG162
SEG161
SEG160
SEG159
SEG158
SEG157
SEG156
SEG155
SEG154
SEG153
SEG152
SEG151
SEG150
SEG149
SEG148
SEG147
SEG146
SEG145
SEG144
SEG143
SEG142
SEG141
SEG140
SEG139
SEG138
SEG137
SEG136
SEG135
SEG134
SEG133
SEG132
SEG131
SEG130
SEG129
SEG128
NC
Pad no.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
Pin name
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SEG127
SEG126
SEG125
SEG124
SEG123
SEG122
SEG121
SEG120
SEG119
SEG118
SEG117
SEG116
SEG115
SEG114
SEG113
SEG112
SEG111
SEG110
SEG109
SEG108
SEG107
SEG106
SEG105
SEG104
SEG103
SEG102
SEG101
SEG100
SEG99
SEG98
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
Pad no.
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
Pin name
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Pad no.
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
Pin name
COMA0
COMA1
COMA2
COMA3
COMA4
COMA5
COMA6
COMA7
COMA8
COMA9
COMA10
COMA11
COMA12
COMA13
COMA14
COMA15
COMA16
COMA17
COMA18
COMA19
COMA20
COMA21
COMA22
COMA23
COMA24
COMA25
COMA26
COMA27
COMA28
COMA29
COMA30
COMA31
COMA32
COMA33
COMA34
COMA35
COMA36
COMA37
COMA38
COMA39
COMA40
COMA41
COMA42
COMA43
COMA44
COMA45
COMA46
COMA47
COMA48
COMA49
COMA50
COMA51
COMA52
COMA53
COMA54
COMA55
COMA56
COMA57
COMA58
COMA59
COMA60
COMA61
COMA62
COMA63
NC
NC
Solomon Systech
7
PIN DESCRIPTIONS
Key:
I = Input
NC = Not Connected
O =Output
Pull LOW= connect to Ground
IO = Bi-directional (input/output) Pull HIGH= connect to VDDIO
P = Power pin
Table 7-1: SSD1322 Pin Description
Pin Name
VDD
Pin Type Description
P
Power supply pin for core logic operation. A capacitor is required to connect between
this pin and VSS.
Refer to Section 8.10 for details.
VDDIO
P
Power supply for interface logic level. It should be matched with the MCU interface
voltage level.
Refer to Section 8.10 for details.
VCI
P
Low voltage power supply.
VCI must always be equal to or higher than VDD and VDDIO.
Refer to Section 8.10 for details.
VCC
P
Power supply for panel driving voltage. This is also the most positive power voltage
supply pin.
VDD1
P
Power supply and it should be connected to VDD.
VSS
P
Ground pin.
VLSS
P
Analog system ground pin.
VCOMH
P
COM signal deselected voltage level.
A capacitor should be connected between this pin and VSS.
BGGND
P
It should be connected to ground.
GPIO0
IO
This is a reserved pin. It should be kept NC.
GPIO1
IO
This is a reserved pin. It should be kept NC.
VSL
P
This is segment voltage reference pin.
When external VSL is used, connect with resistor and diode to ground (details depend
on application).
BS[1:0]
I
MCU bus interface selection pins. Select appropriate logic setting as described in the
following table.
Table 7-2 : Bus Interface selection
BS[1:0]
00
01
10
11
Bus Interface Selection
4 line SPI
3 line SPI
8-bit 8080 parallel
8-bit 6800 parallel
Note
0 is connected to VSS
(2)
1 is connected to VDDIO
(1)
SSD1322
Rev 1.2
P 15/60 Jul 2010
Solomon Systech
Pin Name
IREF
M/S#
CL
Pin Type Description
I
This pin is the segment output current reference pin.
A resistor should be connected between this pin and VSS to maintain the current
around 10uA. Please refer to section 8.6 for the formula of resistor value from IREF.
I
IO
This pin must be connected to VDDIO to enable the chip.
External clock input pin.
When internal clock is enable (i.e. pull HIGH in CLS pin), this pin is not used and
should be connected to Ground.
When internal clock is disable (i.e. pull LOW is CLS pin), this pin is the external
clock source input pin.
CLS
I
Internal clock selection pin.
When this pin is pulled HIGH, internal oscillator is enabled (normal operation).
When this pin is pulled LOW, an external clock signal should be connected to CL.
CS#
I
This pin is the chip select input connecting to the MCU. The chip is enabled for MCU
communication only when CS# is pulled LOW.
RES#
I
This pin is reset signal input.
When the pin is pulled LOW, initialization of the chip is executed.
Keep this pin pull HIGH during normal operation.
D/C#
I
This pin is Data/Command control pin connecting to the MCU.
When the pin is pulled HIGH, the content at D[7:0] will be interpreted as data.
When the pin is pulled LOW, the content at D[7:0] will be interpreted as command.
R/W# (WR#)
I
This pin is read / write control input pin connecting to the MCU interface.
When interfacing to a 6800-series microprocessor, this pin will be used as
Read/Write (R/W#) selection input. Read mode will be carried out when this pin is
pulled HIGH and write mode when LOW.
When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data
write operation is initiated when this pin is pulled LOW and the chip is selected.
When serial interface is selected, this pin R/W (WR#) must be connected to VSS.
E (RD#)
I
This pin is MCU interface input.
When interfacing to a 6800-series microprocessor, this pin will be used as the Enable
(E) signal. Read/write operation is initiated when this pin is pulled HIGH and the
chip is selected.
When connecting to an 8080-microprocessor, this pin receives the Read (RD#)
signal. Read operation is initiated when this pin is pulled LOW and the chip is
selected.
When serial interface is selected, this pin E(RD#) must be connected to VSS.
D[7:0]
IO
These pins are bi-directional data bus connecting to the MCU data bus.
Unused pins are recommended to tie LOW. (Except for D2 pin in SPI mode)
Refer to Section 8.1 for different bus interface connection.
DN[9:0]
SSD1322
IO
Rev 1.2
These are reserved pins and should be connected to VSS.
P 16/60 Jul 2010
Solomon Systech
Pin Name
FR
Pin Type Description
O
This pin is No Connection pins. Nothing should be connected to this pin. This pin
should be left open individually.
DOF#
O
This pin is No Connection pins. Nothing should be connected to this pin. This pin
should be left open individually.
SEG[479:0]
O
These pins provide the OLED segment driving signals. These pins are VSS state when
display is OFF.
COM[127:0]
O
These pins provide the Common switch signals to the OLED panel. These pins are in
high impedance state when display is OFF.
SSD1322
Rev 1.2
P 17/60 Jul 2010
Solomon Systech
8
FUNCTIONAL BLOCK DESCRIPTIONS
8.1
MCU Interface
SSD1322 MCU interface consist of 8 data pin and 5 control pins. The pin assignment at different interface
mode is summarized in Table 8-1. Different MCU mode can be set by hardware selection on BS[1:0] pins
(refer to Table 7-2 for BS[1:0] pins setting)
Table 8-1 : MCU interface assignment under different bus interface mode
Pin Name
Bus
Interface
8-bit 8080
8-bit 6800
3-wire SPI
4-wire SPI
8.1.1
Data/Command Interface
D7
D6
D5
D4
Control Signal
D3
D[7:0]
D[7:0]
Tie LOW
Tie LOW
D2
NC
NC
D1
D0
E
R/W#
RD# WR#
E
R/W#
SDIN SCLK Tie LOW
SDIN SCLK Tie LOW
CS#
CS#
CS#
CS#
CS#
D/C#
D/C#
D/C#
Tie LOW
D/C#
RES#
RES#
RES#
RES#
RES#
MCU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D[7:0]), R/W#, D/C#, E and CS#.
A LOW in R/W# indicates WRITE operation and HIGH in R/W# indicates READ operation.
A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.
The E input serves as data latch signal while CS# is LOW. Data is latched at the falling edge of E signal.
Table 8-2 : Control pins of 6800 interface
Function
E
R/W#
CS#
D/C#
Write command
↓
L
L
L
Read status
↓
H
L
L
Write data
↓
L
L
H
Read data
↓
H
L
H
Note
(1)
↓ stands for falling edge of signal
(2)
H stands for HIGH in signal
(3)
L stands for LOW in signal
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual display
data read. This is shown in Figure 8-1.
SSD1322
Rev 1.2
P 18/60 Jul 2010
Solomon Systech
Figure 8-1 : Data read back procedure - insertion of dummy read
R/W#
E
N
Databus
Write column
address
8.1.2
Dummy read
n
n+1
Read 1st data
Read 2nd data
n+2
Read 3rd data
MCU Parallel 8080-series Interface
The parallel interface consists of 8 bi-directional data pins (D[7:0]), RD#, WR#, D/C# and CS#.
A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.
A rising edge of RD# input serves as a data READ latch signal while CS# is kept LOW.
A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept LOW.
Figure 8-2 : Example of Write procedure in 8080 parallel interface mode
CS#
WR#
D[7:0]
D/C#
RD#
high
low
Figure 8-3 : Example of Read procedure in 8080 parallel interface mode
CS#
RD#
D[7:0]
D/C#
WR#
high
low
SSD1322
Rev 1.2
P 19/60 Jul 2010
Solomon Systech
Table 8-3 : Control pins of 8080 interface
Function
Write command
Read status
Write data
Read data
RD#
H
↑
H
↑
WR#
↑
H
↑
H
CS#
L
L
L
L
D/C#
L
L
H
H
Note
(1)
↑ stands for rising edge of signal
(2)
H stands for HIGH in signal
(3)
L stands for LOW in signal
(4)
Refer to
Figure 13-2 for Form 1 8080-Series MPU Parallel Interface Timing Characteristics
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual display
data read. This is shown in Figure 8-4.
Figure 8-4 : Display data read back procedure - insertion of dummy read
WR#
RD#
Databus
N
Write column
address
8.1.3
Dummy read
n
n+1
n+2
Read 1st data
Read 2nd data
Read 3rd data
MCU Serial Interface (4-wire SPI)
The serial interface consists of serial clock SCLK, serial data SDIN, D/C#, CS#. In SPI mode, D0 acts as
SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. The pins from D3 to D7, E and
R/W# can be connected to an external ground.
Table 8-4 : Control pins of 4-wire Serial interface
Function
Write command
Write data
E(RD#)
Tie LOW
Tie LOW
R/W#(WR#)
Tie LOW
Tie LOW
CS#
L
L
D/C#
L
H
D0
↑
↑
Note
(1)
H stands for HIGH in signal
(2)
L stands for LOW in signal
SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C#
is sampled on every eighth clock and the data byte in the shift register is written to the Graphic Display Data
RAM (GDDRAM) or command register in the same clock.
SSD1322
Rev 1.2
P 20/60 Jul 2010
Solomon Systech
Under serial mode, only write operations are allowed.
Figure 8-5 : Write procedure in 4-wire Serial interface mode
CS#
D/C#
SDIN/
SCLK
DB1
DB2
DBn
SCLK(D0)
SDIN(D1)
8.1.4
D7
D6
D5
D4
D3
D2
D1
D0
MCU Serial Interface (3-wire SPI)
The 3-wire serial interface consists of serial clock SCLK, serial data SDIN and CS#.
In 3-wire SPI mode, D0 acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open.
The pins from D3 to D7, R/W# (WR#), E(RD#) and D/C# can be connected to an external ground.
The operation is similar to 4-wire serial interface while D/C# pin is not used. There are altogether 9-bits will
be shifted into the shift register on every ninth clock in sequence: D/C# bit, D7 to D0 bit. The D/C# bit (first
bit of the sequential data) will determine the following data byte in the shift register is written to the Display
Data RAM (D/C# bit = 1) or the command register (D/C# bit = 0). Under serial mode, only write operations
are allowed.
Table 8-5: Control pins of 3-wire Serial interface
Function
Write command
Write data
E(RD#)
Tie LOW
Tie LOW
R/W#(WR#)
Tie LOW
Tie LOW
CS#
L
L
D/C#
Tie LOW
Tie LOW
D0
↑
↑
Note
L stands for LOW in signal
(1)
Figure 8-6: Write procedure in 3-wire Serial interface mode
CS#
SDIN/
SCLK
DB1
DB2
DBn
SCLK
(D0)
SDIN(D1)
SSD1322
D/C#
Rev 1.2
D7
D6
P 21/60 Jul 2010
D5
D4
D3
D2
D1
D0
Solomon Systech
8.2
Reset Circuit
When RES# input is pulled LOW, the chip is initialized with the following status:
1. Display is OFF
2. 128 MUX Display Mode
3. Normal segment and display data column address and row address mapping (SEG0 mapped to
address 00h and COM0 mapped to address 00h)
4. Display start line is set at display RAM address 0
5. Column address counter is set at 0
6. Normal scan direction of the COM outputs
7. Contrast control register is set at 7Fh
8.3
GDDRAM
8.3.1
GDDRAM structure in Gray Scale mode
The GDDRAM address map in Table 8-6 shows the GDDRAM in Gray Scale mode. Since in Gray Scale
mode, there are 16 gray levels. Therefore four bits (one nibble) are allocated for each pixel. For example
D30480[3:0] in Table 8-6 corresponds to the pixel located in (COM127, SEG2). So the lower nibble and
higher nibble of D0, D1, D2, …, D30717, D30718, D30719 in Table 8-6 represent the 480x128 data nibbles
in the GDDRAM.
Table 8-6 : GDDRAM in Gray Scale mode (RESET)
SEG0
SEG1
SEG2
00
COM0
COM1
00
01
|
|
D1[3:0]
D241[3:0]
SEG3
SEG476
00
D1[7:4]
D241[7:4]
D0[3:0]
D240[3:0]
SEG477
SEG478
SEG479
77
D0[7:4]
D240[7:4]
D239[3:0]
D479[3:0]
77
D239[7:4]
D479[7:4]
D238[3:0]
D478[3:0]
SEG
Outputs
RAM
Column
address
(HEX)
D238[7:4]
D478[7:4]
|
COM126
COM127
7E D30241[3:0] D30241[7:4] D30240[3:0] D30240[7:4] D30479[3:0]D30479[7:4]D30478[3:0] D30478[7:4]
7F D30481[3:0] D30481[7:4] D30480[3:0] D30480[7:4] D30719[3:0]D30719[7:4]D30718[3:0] D30718[7:4]
RAM
COM
Row
Corresponding to one pixel
Outputs Address
(HEX)
8.3.2
Data bus to RAM mapping
Table 8-7 : Data bus usage
Read / Write Data
Bus width
Data bus D[7:0]
Input order
D7
D6
D5
D4
D3
D2
D1
D0
1st
3
3
3
3
2
2
2
2
2nd
1
1
1
1
0
0
0
0
8 bits
Corresponding to one pixel
SSD1322
Rev 1.2
P 22/60 Jul 2010
Solomon Systech
8.4
Command Decoder
This module determines whether the input should be interpreted as data or command based upon the input of
the D/C# pin.
If D/C# pin is HIGH, data is written to Graphic Display Data RAM (GDDRAM). If it is LOW, the inputs at
D0-D7 are interpreted as a Command and it will be decoded and be written to the corresponding command
register.
8.5
Oscillator & Timing Generator
Figure 8-7 : Oscillator Circuit
Internal
Oscillator
Fosc
M
U
X
CL
CLK
Divider
DCLK
Display
Clock
CLS
This module is an On-Chip low power RC oscillator circuitry (Figure 8-7). The operation clock (CLK) can be
generated either from internal oscillator or external source CL pin by CLS pin. If CLS pin is HIGH, internal
oscillator is selected. If CLS pin is LOW, external clock from CL pin will be used for CLK. The frequency of
internal oscillator FOSC can be programmed by command B3h.
The display clock (DCLK) for the Display Timing Generator is derived from CLK. The division factor “D”
can be programmed from 1 to 1024 by command B3h.
DCLK = FOSC / D
The frame frequency of display is determined by the following formula:
FFRM =
Fosc
D × K × No. of Mux
where
• D stands for clock divide ratio. It is set by command B3h A[3:0]. The divide ratio has the range from 1 to
1024.
• K is the number of display clocks per row. The value is derived by
K = Phase 1 period + Phase 2 period + X
X = DCLKs in current drive period. Default X = constant + GS15 = 10 +112 = 122
Default K is 9 + 7 + 122 = 138
• Number of multiplex ratio is set by command A8h. The reset value is 127 (i.e. 128MUX).
• Fosc is the oscillator frequency. It can be changed by command B3h A[7:4]. The higher the register setting
results in higher frequency.
If the frame frequency is set too low, flickering may occur. On the other hand, higher frame frequency leads
to higher power consumption on the whole system.
SSD1322
Rev 1.2
P 23/60 Jul 2010
Solomon Systech
8.6
SEG/COM Driving Block
This block is used to derive the incoming power sources into the different levels of internal use voltage and
current.
• VCC is the most positive voltage supply.
• VCOMH is the Common deselected level. It is internally regulated.
• VLSS is the ground path of the analog and panel current.
• IREF is a reference current source for segment current drivers ISEG. The relationship between reference
current and segment current of a color is:
ISEG = Contrast / 256 * IREF * scale factor *2
in which
the contrast (0~255) is set by Set Contrast command (C1h); and
the scale factor (1 ~ 16) is set by Master Current Control command (C7h).
For example, in order to achieve ISEG = 300uA at maximum contrast 255, IREF is set to around 10uA.
This current value is obtained by connecting an appropriate resistor from IREF pin to VSS as shown in
Figure 8-8.
Recommended IREF = 10uA
Figure 8-8 : IREF Current Setting by Resistor Value
SSD1322
IREF (voltage at
this pin = VCC – 6)
IREF ≈ 10uA
R1
VSS
Since the voltage at IREF pin is VCC – 6V, the value of resistor R1 can be found as below:
For IREF = 10uA, VCC = 18V:
R1 = (Voltage at IREF – VSS) / IREF
= (18 – 6) / 10uA
≈ 1.2MΩ
SSD1322
Rev 1.2
P 24/60 Jul 2010
Solomon Systech
8.7
SEG / COM Driver
Segment drivers consist of 480 current sources to drive OLED panel. The driving current can be adjusted
from 0 to 300uA with 8 bits, 256 steps by contrast setting command (C1h). Common drivers generate
scanning voltage pulse. The block diagrams and waveforms of the segment and common driver are shown as
follow.
Figure 8-9 : Segment and Common Driver Block Diagram – Single COM mode
VCC
ISEG
VCOMH
Current
Drive
Non-selected
Row
Reset
OLED
Pixel
Selected
Row
VLSS
VLSS
Segment Driver
Common Driver
SSD1322
Rev 1.2
P 25/60 Jul 2010
Solomon Systech
Figure 8-10 : Segment and Common Driver Block Diagram – Dual COM mode
ISEG
Current
Drive
Reset
OLED
Pixel
V LSS
Segment Driver
VCOMH
V COMH
Non -selected
Row
Non -selected
Row
Selected
Row
Selected
Row
Common
Driver
COMA
V LSS
V LSS
Common
Driver
COMB
The commons are scanned sequentially, row by row. If a row is not selected, all the pixels on the row are in
reverse bias by driving those commons to voltage VCOMH as shown in Figure 8-11.
In the scanned row, the pixels on the row will be turned ON or OFF by sending the corresponding data signal
to the segment pins. If the pixel is turned OFF, the segment current is kept at 0. On the other hand, the
segment drives to ISEG when the pixel is turned ON.
SSD1322
Rev 1.2
P 26/60 Jul 2010
Solomon Systech
Figure 8-11 : Segment and Common Driver Signal Waveform
One Frame Period
Non-selected Row
COM0
VCOMH
VLSS
Selected Row
COM1
VCOMH
VLSS
COM
Voltage
This row is selected to
turn on
VCOMH
VLSS
Time
Segment
Voltage
Waveform for ON
VP
Waveform for OFF
VLSS
Time
There are four phases to driving an OLED a pixel. In phase 1, the pixel is reset by the segment driver to VLSS
in order to discharge the previous data charge stored in the parasitic capacitance along the segment electrode.
The period of phase 1 can be programmed by command B1h A[3:0]. An OLED panel with larger capacitance
requires a longer period for discharging.
SSD1322
Rev 1.2
P 27/60 Jul 2010
Solomon Systech
In phase 2, first pre-charge is performed. The pixel is driven to attain the corresponding voltage level VP from
VLSS. The amplitude of VP can be programmed by the command BBh. The period of phase 2 can be
programmed by command B1h A[7:4]. If the capacitance value of the pixel of OLED panel is larger, a longer
period is required to charge up the capacitor to reach the desired voltage.
In phase 3, the OLED pixel is driven to the targeted driving voltage through second pre-charge. The second
pre-charge can control the speed of the charging process. The period of phase 3 can be programmed by
command B6h.
Last phase (phase 4) is current drive stage. The current source in the segment driver delivers constant current
to the pixel. The driver IC employs PWM (Pulse Width Modulation) method to control the gray scale of each
pixel individually. The gray scale can be programmed into different Gamma settings by command B8h/B9h.
The bigger gamma setting (the wider pulse widths) in the current drive stage results in brighter pixels and vice
versa (details refer to Section 8.8). This is shown in the following figure.
Figure 8-12 : Gray Scale Control by PWM in Segment
Phase2
Phase1
Segment
Voltage
Phase4
Phase3
VP
VLSS
Wider pulse width
drives pixel brighter
OLED
Panel
After finishing phase 4, the driver IC will go back to phase 1 to display the next row image data. This fourstep cycle is run continuously to refresh image display on OLED panel.
The length of phase 4 is defined by command B8h or B9h. In the table, the gray scale is defined in
incremental way, with reference to the length of previous table entry.
SSD1322
Rev 1.2
P 28/60 Jul 2010
Solomon Systech
8.8
Gray Scale Decoder
The gray scale effect is generated by controlling the pulse width (PW) of current drive phase, except GS0
there is no pre-charge (phase 2, 3) and current drive (phase 4). The driving period is controlled by the gray
scale settings (setting 0 ~ setting 180). The larger the setting, the brighter the pixel will be. The Gray Scale
Table stores the corresponding gray scale setting of the 16 gray scale levels (GS0~GS15) through the
software commands B8h or B9h.
As shown in Figure 8-13, GDDRAM data has 4 bits, represent the 16 gray scale levels from GS0 to GS15.
Note that the frame frequency is affected by GS15 setting.
Figure 8-13 : Relation between GDDRAM content and Gray Scale table entry (under command B9h Enable
Linear Gray Scale Table)
GDDRAM data (4 bits)
Gray Scale Table
0000
0001
0010
0011
:
:
1101
1110
1111
GS0
GS1 (1)
GS2
GS3
:
:
GS13
GS14
GS15
Default Gamma Setting
(Command B9h)
Setting 0
Setting 0
Setting 8
Setting 16
:
:
Setting 96
Setting 104
Setting 112
Note:
(1)
Both GS0 and GS1 have no 2nd pre-charge (phase 3) and current drive (phase 4), however GS1 has 1st precharge (phase 2).
SSD1322
Rev 1.2
P 29/60 Jul 2010
Solomon Systech
8.9
Power ON and OFF sequence
The following figures illustrate the recommended power ON and power OFF sequence of SSD1322 (assume
VCI and VDDIO are at the same voltage level and internal VDD is used).
Power ON sequence:
1. Power ON VCI, VDDIO.
2. After VCI, VDDIO become stable, set wait time at least 1ms (t0) for internal VDD become stable. Then
set RES# pin LOW (logic low) for at least 100us (t1) (4) and then HIGH (logic high).
3. After set RES# pin LOW (logic low), wait for at least 100us (t2). Then Power ON VCC.(1)
4. After VCC become stable, send command AFh for display ON. SEG/COM will be ON after 200ms
(tAF).
5. After VCI become stable, wait for at least 300ms to send command.
Figure 8-14 : The Power ON sequence.
ON VCI, VDDIO
VCI,, VDDIO
RES#
ON VCC
Send AFh command for Display ON
t0
OFF
t1
RES#
GND
t2
VCC
OFF
tAF
ON
SEG/COM
OFF
Power OFF sequence:
1. Send command AEh for display OFF.
2. Power OFF VCC.(1), (2)
3. Wait for tOFF. Power OFF VCI,, VDDIO. (where Minimum tOFF=0ms (3), Typical tOFF=100ms)
Figure 8-15 : The Power OFF sequence
Send command AEh for display OFF
VCC
OFF VCC
OFF VCI ,VDDIO
OFF
tOFF
VCI, VDDIO
OFF
Note:
(1)
Since an ESD protection circuit is connected between VCI, VDDIO and VCC, VCC becomes lower than VCI whenever VCI,
VDDIO is ON and VCC is OFF as shown in the dotted line of VCC in Figure 8-14 and Figure 8-15.
(2)
VCC should be kept float (disable) when it is OFF.
(3)
VCI, VDDIO should not be Power OFF before VCC Power OFF.
(4)
The register values are reset after t1.
(5)
Power pins (VDD, VCC) can never be pulled to ground under any circumstance.
SSD1322
Rev 1.2
P 30/60 Jul 2010
Solomon Systech
8.10 VDD Regulator
In SSD1322, the power supply pin for core logic operation, VDD, can be supplied by external source or
internally regulated through the VDD regulator.
The internal VDD regulator is enabled by setting bit A[0] to 1b in command ABh “Function Selection”.
VCI should be larger than 2.6V when using the internal VDD regulator. The typical regulated VDD is about 2.5V
It should be notice that, no matter VDD is supplied by external source or internally regulated; VCI must always
be set equivalent to or higher than VDD and VDDIO.
The following figure shows the VDD regulator pin connection scheme:
Figure 8-16 VCI > 2.6V, VDD regulator enable pin connection scheme
VCI > 2.6V, VDD Regulator Enable,
Command: ABh A[0]=1b.
VCI
VCI
VDDIO
VSS
VDDIO
GND
VDD
Figure 8-17 VDD regulator disable pin connection scheme
VDD Regulator Disable,
Command: ABh A[0]=0b.
SSD1322
Rev 1.2
VCI
VDDIO
VSS
VDD
VCI
VDDIO
GND
VDD
P 31/60 Jul 2010
Solomon Systech
9
COMMAND TABLE
Table 9-1 : Command table
(D/C#=0, R/W#(WR#) = 0, E(RD#)=1) unless specific setting is stated)
Fundamental Command Table
D/C#
Hex
D7 D6
D5
D4
0
00
0
0
1
1
15
A[6:0]
B[6:0]
0
D3 D2
D2
D0
0
0
0
0
0
*
*
0
A6
B6
0
A5
B5
1
A4
B4
5C
0
1
0
0
5D
0
1
0
1
1
75
A[6:0]
B[6:0]
0
*
*
0
1
1
A0
A[7:0]
B[4]
1
0
*
Command
Description
0
0
0
0
A3
B3
1
A2
B2
0
A1
B1
1
A0
B0
1
1
1
0
0
Write RAM
Command
Enable MCU to write Data into RAM
0
1
1
1
0
1
Read RAM
Command
Enable MCU to read Data from RAM
1
A6
B6
1
A5
B5
1
A4
B4
0
A3
B3
1
A2
B2
0
A1
B1
1
A0
B0
0
0
*
1
A5
0
0
A4
B4
0
0
0
0
A2
0
0
A1
0
0
A0
1
Enable Gray This command is sent to enable the Gray Scale table setting
Scale table (command B8h)
Set Column
Address
Set Row
Address
Set Column start and end address
A[6:0]: Start Address. [reset=0]
B[6:0]: End Address. [reset=119]
Range from 0 to 119
Set Row start and end address
A[6:0]: Start Address. [reset=0]
B[6:0]: End Address. [reset=127]
Range from 0 to 127
A[0]=0b, Horizontal address increment [reset]
A[0]=1b, Vertical address increment
A[1]=0b, Disable Column Address Re-map [reset]
A[1]=1b, Enable Column Address Re-map
A[2]=0b, Disable Nibble Re-map [reset]
A[2]=1b, Enable Nibble Re-map
A[4]=0b, Scan from COM0 to COM[N –1] [reset]
A[4]=1b, Scan from COM[N-1] to COM0, where N is the
Multiplex ratio
Set Re-map and
Dual COM Line
A[5]=0b, Disable COM Split Odd Even [reset]
mode
A[5]=1b, Enable COM Split Odd Even
B[4], Enable / disable Dual COM Line mode
0b, Disable Dual COM mode [reset]
1b, Enable Dual COM mode (MUX ≤ 63)
Note
(1]
COM Split Odd Even mode must be disabled (A[5]=0b)
when enabling the Dual COM mode (B[4]=1b)
Details refer to Section 10.1.6
0
1
A1
A[6:0]
1
*
SSD1322
0
A6
1
A5
0
A4
Rev 1.2
0
A3
0
A2
0
A1
P 32/60 Jul 2010
1
A0
Set Display
Start Line
Set display RAM display start line register from 0-127
Display start line register is reset to 00h after RESET
Solomon Systech
D/C#
0
Hex
A2
D7 D6
1
0
1
A[6:0]
*
0
A4~A7
1
D5
1
D4
0
D3 D2
0
0
D2
1
D0
0
A6
A5
A4
A3
A2
A1
A0
0
1
0
0
X2
X1
X0
Command
Set Display
Offset
Description
Set vertical scroll by COM from 0-127
The value is reset to 00H after RESET
A4h = Entire Display OFF, all pixels turns OFF in GS level 0
A5h = Entire Display ON, all pixels turns ON in GS level 15
Set Display
Mode
A6h = Normal Display [reset]
A7h = Inverse Display (GS0 Æ GS15, GS1 Æ GS14, GS2
Æ GS13, …)
0
1
1
A8
A[6:0]
B[6:0]
1
0
0
0
A6
B6
1
A5
B5
0
A4
B4
1
A3
B3
0
A2
B2
0
A1
B1
0
A0
B0
0
A9
1
0
1
0
1
0
0
1
0
1
AB
A[0]
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
A0
0
AE~AF
1
0
1
0
1
1
1
X0
0
1
B1
A[7:0]
1
A7
0
A6
1
A5
1
A4
0
A3
0
A2
0
A1
1
A0
This command turns ON partial mode. The partial mode
display area is defined by the following two parameters,
Enable Partial
Display
A[6:0]: Address of start row in the display area
B[6:0]: Address of end row in the display area,
where B[6:0] must be ≥ A[6:0]
Exit Partial
Display
Function
Selection
This command is sent to exit the Partial Display mode
A[0]=0b, Select external VDD
A[0]=1b, Enable internal VDD regulator [reset]
Set Sleep mode AEh = Sleep mode ON (Display OFF)
ON/OFF
AFh = Sleep mode OFF (Display ON)
A[3:0] Phase 1 period (reset phase length) of 5~31 DCLK(s)
clocks as follow:
A[3:0]
0000
0001
0010
0011
0100
:
1111
Set Phase
Length
A[7:4] Phase 2 period (first pre-charge phase length) of
3~15 DCLK(s) clocks as follow:
A[7:4]
0000
0001
0010
0011
:
0111
:
1111
SSD1322
Rev 1.2
P 33/60 Jul 2010
Phase 1 period
invalid
invalid
5 DCLKs
7 DCLKs
9 DCLKs [reset]
:
31 DCLKs
Phase 2 period
invalid
invalid
invalid
3 DCLKs
:
7 DCLKs [reset]
:
15 DCLKs
Solomon Systech
D/C#
0
Hex
B3
1
A[7:0]
D7 D6
1
0
D5
1
D4
1
D3 D2
0
0
D2
1
D0
1
A7
A5
A4
A3
A1
A0
A6
A2
Command
Set Front Clock
Divider /
Oscillator
Frequency
Description
A[3:0] [reset=0], divide by DIVSET where
A[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
>=1011
DIVSET
divide by 1
divide by 2
divide by 4
divide by 8
divide by 16
divide by 32
divide by 64
divide by 128
divide by 256
divide by 512
divide by 1024
invalid
A[7:4] Oscillator frequency, frequency increases as level
increases [reset=0101b]
0
1
1
B4
A[1:0]
B[7:3]
1
1
B7
0
0
B6
1
1
B5
1
0
B4
0
0
B3
1
0
1
0
A1
0
A[1:0] = 00b: Enable external VSL
A[1:0] = 10b: Internal VSL [reset]
0
A0
1
Display
B[7:3] = 11111b: Enhanced low GS display quality
Enhancement A B[7:3] = 10110b: Normal [reset]
0
B5
1
0
1
1
0
1
0
1
1
A[3:0]
*
*
*
*
A3
A2
A1
A0
A[1:0] GPIO0: 00 pin HiZ, Input disabled
01 pin HiZ, Input enabled
10 pin output LOW [reset]
11 pin output HIGH
Set GPIO
0
1
B6
A[3:0]
1
*
0
*
1
*
1
*
0
A3
1
A2
1
A1
0
A0
Set Second
Precharge
Period
SSD1322
Rev 1.2
P 34/60 Jul 2010
A[3:2] GPIO1: 00 pin HiZ, Input disabled
01 pin HiZ, Input enabled
10 pin output LOW [reset]
11 pin output HIGH
A[3:0] Second Pre-charge period
0000b 0 dclk
0001b 1 dclk
……
1000b 8 dclks [reset]
……
1111b 15 dclks
Solomon Systech
D/C# Hex
D7 D6 D5 D4 D3 D2 D2
0
B8
1
0
1
1
1
0
0
A1
A1
A1
A1
A1
A1
A1
1
A1[7:0]
7
6
5
4
3
2
1
1
A2[7:0] A27 A26 A25 A24 A23 A22 A21
.
.
.
.
.
.
.
1
.
.
.
.
.
.
.
.
1
.
.
.
.
.
.
.
.
1
.
A14
A14
A14
A14
A14
A14
A14
1 A14[7:0]
7
6
5
4
3
2
1
1
A15[7:0]
A157 A156 A155 A154 A153 A152 A151
D0
0
Command
A10
A20
.
.
.
A140
A150
Description
The next 15 data bytes define Gray Scale (GS) Table by
setting the gray scale pulse width in unit of DCLK’s
(ranges from 0d ~ 180d)
Set Gray Scale A1[7:0]: Gamma Setting for GS1,
Table
A2[7:0]: Gamma Setting for GS2,
:
A14[7:0]: Gamma Setting for GS14,
A15[7:0]: Gamma Setting for GS15
Note
0 ≤ Setting of GS1 < Setting of GS2 < Setting of GS3.....
< Setting of GS14 < Setting of GS15
(1]
Refer to Section 8.8 for details
(2]
The setting must be followed by the Enable Gray Scale
Table command (00h)
0
B9
1
0
1
1
1
0
0
The default Linear Gray Scale table is set in unit of DCLK’s
as follow
1
GS0 level pulse width = 0;
GS1 level pulse width = 0;
GS2 level pulse width = 8;
Select Default GS3 level pulse width = 16;
Linear Gray
:
Scale table
:
GS14 level pulse width = 104;
GS15 level pulse width = 112
Refer to Section 8.8 for details
0
1
BB
A[4:0]
1
*
0
*
1
*
1
A4
1
A3
0
A2
1
A1
Set pre-charge voltage level.[reset = 17h]
1
A0
Set Pre-charge
voltage
0
BE
1
0
1
1
1
1
1
0
1
A[2:0]
*
*
*
*
0
A2
A1
A0
C1
A[7:0]
1
A7
SSD1322
1
A6
0
A5
0
A4
Rev 1.2
0
A3
0
A2
0
A1
P 35/60 Jul 2010
1
A0
Hex code
00h
:
1Fh
pre-charge voltage
0.20 x VCC
:
0.60 x VCC
Set COM deselect voltage level [reset = 04h]
Set VCOMH
0
1
A[4:0]
00000
:
11111
Set Contrast
Current
A[2:0]
000
:
100
:
111
Hex code
00h
:
04h
:
07h
V COMH
0.72 x VCC
:
0.80 x VCC [reset]
:
0.86 x VCC
A[7:0]: Contrast current value, range:00h~FFh,
i.e. 256 steps for ISEG current [reset = 7Fh]
Solomon Systech
D/C#
0
Hex
C7
D7 D6
1
1
D5
0
D4
0
1
A[3:0]
*
0
CA
1
A[6:0]
D3 D2
0
1
D2
1
D0
1
*
*
*
A3
A2
A1
A0
1
1
0
0
1
0
1
0
*
A6
A5
A4
A3
A2
A1
A0
0
1
1
D1
A[5:4]
20
1
1
0
1
0
0
0
A5
1
1
A4
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
FD
A[2]
1
0
1
0
1
0
1
1
1
0
1
A2
0
1
1
0
Command
Description
A[3:0] =
0000b, reduce output currents for all colors to 1/16
0001b, reduce output currents for all colors to 2/16
Master Contrast
:
Current Control
1110b, reduce output currents for all colors to 15/16
1111b, no change [reset]
A[6:0]: Set MUX ratio from 16MUX ~ 128MUX
Set MUX Ratio
A[6:0] = 15d represents 16MUX
:
A[6:0] = 127d represents 128MUX [reset]
A[5:4] = 00b: Reserved
Display
Enhancement B A[5:4] = 10b: Normal [reset]
A[2]: MCU protection status [reset = 12h]
A[2] = 0b, Unlock OLED driver IC MCU interface from
entering command [reset]
Set Command A[2] = 1b, Lock OLED driver IC MCU interface from
Lock
entering command
Note
(1)
The locked OLED driver IC MCU interface prohibits all
commands and memory access except the FDh command
Note
(1)
“*” stands for “Don’t care”.
SSD1322
Rev 1.2
P 36/60 Jul 2010
Solomon Systech
10 COMMAND
10.1.1 Enable Gray Scale Table (00h)
This command is sent to enable the Gray Scale Table setting (command B8h).
10.1.2 Set Column Address (15h)
This triple byte command specifies column start address and end address of the display data RAM. This
command also sets the column address pointer to column start address. This pointer is used to define the
current read/write column address in graphic display data RAM. If horizontal address increment mode is
enabled by command A0h, after finishing read/write one column data, it is incremented automatically to the
next column address. Whenever the column address pointer finishes accessing the end column address, it is
reset back to start column address and the row address is incremented to the next row.
10.1.3 Write RAM Command (5Ch)
After entering this single byte command, data entries will be written into the display RAM until another
command is written. Address pointer is increased accordingly. This command must be sent before write data
into RAM.
10.1.4 Read RAM Command (5Dh)
After entering this single byte command, data is read from display RAM until another command is written.
Address pointer is increased accordingly. This command must be sent before read data from RAM.
SSD1322
Rev 1.2
P 37/60 Jul 2010
Solomon Systech
10.1.5 Set Row Address (75h)
This triple byte command specifies row start address and end address of the display data RAM. This
command also sets the row address pointer to row start address. This pointer is used to define the current
read/write row address in graphic display data RAM. If vertical address increment mode is enabled by
command A0h, after finishing read/write one row data, it is incremented automatically to the next row address.
Whenever the row address pointer finishes accessing the end row address, it is reset back to start row address.
The diagram below shows the way of column and row address pointer movement through the example:
column start address is set to 1 and column end address is set to 118, row start address is set to 2 and row end
address is set to 126. Horizontal address increment mode is enabled by command A0h. In this case, the
graphic display data RAM column accessible range is from column 1 to column 118 and from row 1 to row
126 only. In addition, the column and row address pointers are set to 1 and 2, respectively. After finishing
read/write four pixels of data, the column address is increased automatically by 1 to access the next RAM
location for next read/write operation (solid line in Figure 10-1). Whenever the column address pointer
finishes accessing the end column 118, it is reset back to column 1 and row address is automatically increased
by 1 (solid line in Figure 10-1). While the end row 126 and end column 118 RAM location is accessed, the
row address is reset back to 2 and the column address is reset back to 1 (dotted line in Figure 10-1).
Figure 10-110-2 : Example of Column and Row Address Pointer Movement (Gray Scale Mode)
Row 0
Row 1
Row 2
:
:
:
Row 125
Row 126
Row 127
SSD1322
SEG479
SEG478
SEG477
SEG476
119
SEG475
SEG474
SEG473
SEG472
:
118
:
:
:
SEG7
...
SEG6
SEG5
SEG4
SEG3
1
SEG2
SEG1
SEG0
0
Column address
SEG Outputs
:
:
:
Rev 1.2
P 38/60 Jul 2010
Solomon Systech
10.1.6 Set Re-map & Dual COM Line Mode (A0h)
This command has multiple configurations and each bit setting is described as follows:
•
Address increment mode (A[0])
When A[0] is set to 0, the driver is set as horizontal address increment mode. After the display RAM
is read / written, the column address pointer is increased automatically by 1. If the column address
pointer reaches column end address, the column address pointer is reset to column start address and
row address pointer is increased by 1. The sequence of movement of the row and column address
point for horizontal address increment mode is shown in Figure 10-3.
Figure 10-3 : Address Pointer Movement of Horizontal Address Increment Mode
Row 0
Row 1
:
Row 126
Row 127
Col 0
Col 1
…..
Col 118
Col 119
:
:
:
:
:
When A[0] is set to 1, the driver is set to vertical address increment mode. After the display RAM is
read / written, the row address pointer is increased automatically by 1. If the row address pointer
reaches the row end address, the row address pointer is reset to row start address and column address
pointer is increased by 1. The sequence of movement of the row and column address point for
vertical address increment mode is shown in Figure 10-4.
Figure 10-4: Address Pointer Movement of Vertical Address Increment Mode
Col 0
Row 0
Row 1
:
Row 126
Row 127
Col 1
…..
…..
…..
:
…..
…..
Col 118
Col 119
•
Column Address Remap (A[1])
This command bit is made for increasing the layout flexibility of segment signals in OLED module
with segment arranged from left to right (when A[1] is set to 0) or vice versa (when A[1] is set to 1),
as demonstrated in Figure 10-5.
A[1] = 0 (reset): RAM Column 0 ~ 119 maps to SEG0-SEG3 ~ SEG476-SEG479
A[1] = 1: RAM Column 0 ~ 119 maps to SEG476-SEG479 ~ SEG0-SEG3
•
Nibble Remap (A[2])
A[2] = 0 (reset): Data bits direct mapping is performed
A[2] = 1: The four nibbles of the data bus for RAM access are re-mapped
The effects are demonstrated in Figure 10-5.
SSD1322
Rev 1.2
P 39/60 Jul 2010
Solomon Systech
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
:
:
:
:
SEG472
SEG473
SEG474
SEG475
SEG476
SEG477
SEG478
SEG479
SEG477
SEG476
SEG475
SEG474
SEG473
SEG472
:
:
:
:
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
SEG1
SEG0
SEG7
SEG6
SEG5
SEG4
:
:
:
:
SEG475
SEG474
SEG473
SEG472
SEG479
SEG478
SEG477
SEG476
SEG478
SEG479
SEG472
SEG473
SEG474
SEG475
:
:
:
:
SEG4
SEG5
SEG6
SEG7
SEG0
SEG1
SEG2
SEG3
D238[7:4]
D30478[7:4]
D30718[7:4]
D478[7:4]
D238[3:0]
D30719[7:4]
D478[3:0]
D30479[7:4]
D30719[3:0]
D30478[3:0]
D30479[3:0]
D30716[7:4]
D30718[3:0]
D30476[7:4]
D30716[3:0]
D239[7:4]
D30476[3:0]
D30717[7:4]
:
D479[7:4]
D30477[7:4]
D30717[3:0]
D239[3:0]
D30477[3:0]
:
:
:
D479[3:0]
:
:
D236[7:4]
:
:
:
D476[7:4]
:
:
D236[3:0]
:
D30482[7:4]
D476[3:0]
D30242[7:4]
D30482[3:0]
D237[7:4]
D30242[3:0]
D30483[7:4]
COM Outputs
RAM /
Row
address
(HEX)
D477[7:4]
D30243[7:4]
7F
D30483[3:0]
D237[3:0]
D30243[3:0]
COM0
D477[3:0]
D30240[7:4]
COM127
:
7E
:
COM1
:
COM126
:
D242[3:0]
:
D30480[7:4]
D2[7:4]
D243[7:4]
:
D242[7:4]
D243[3:0]
:
D30240[3:0]
D2[3:0]
1
D30480[3:0]
D3[3:0]
COM126
D240[7:4]
COM1
D240[3:0]
0
D241[7:4]
COM127
D241[3:0]
COM0
SEG
Outputs
RAM /
Column
address
(HEX)
77
D30241[7:4]
D0[7:4]
76
D30481[7:4]
D0[3:0]
…
D30241[3:0]
D1[3:0]
1
D30481[3:0]
D1[7:4]
0
Normal, Remap,
A[4] = 0 A[4] = 1
D3[7:4]
SEG1
Remap,
A[1] = 1 & A[2] = 0
SEG478
SEG2
SEG477
SEG0
SEG3
Normal,
A[1] = 1 & A[2] = 1
Normal,
A[1] = 0 & A[2] = 0
SEG479
Remap,
A[1] = 0 & A[2] = 1
SEG476
Figure 10-5: GDDRAM in Gray Scale mode with or without Column Address (A[1]) & Nibble remapping (A[2])
Corresponding to one pixel
•
COM scan direction Remap (A[4])
This command bit determines the scanning direction of the common for flexible layout of common
signals in OLED module either from up to down or vice versa.
A[1] = 0 (reset): Scan from up to down
A[1] = 1: Scan from bottom to up
Details of pin arrangement can be found in Figure 10-5.
•
Odd even split of COM pins (A[5])
This command bit can set the odd even arrangement of COM pins.
A[5] = 0 (reset): Disable COM split odd even, pin assignment of common is in sequential as
COM127 COM126...COM 65 COM64...SEG479...SEG0...COM0 COM1...COM62 COM63
A[5] = 1: Enable COM split odd even, pin assignment of common is in odd even split as
COM127 COM125...COM3 COM1...SEG479...SEG0...COM0 COM2...COM124 COM126
Details of pin arrangement can be found in Figure 10-6.
SSD1322
Rev 1.2
P 40/60 Jul 2010
Solomon Systech
•
Set Dual COM mode (B[4])
This command bit can set the dual COM mode.
B[4] = 0 (reset): Disable the dual COM mode, as shown on Figure 10-6
B[4] = 1: Enable the dual COM mode, details of pin arrangement can be found in Figure 10-7
Notice that Odd even split of COM pins must be disabled (A[5]=0) and MUX must be set equating to
or smaller than 63 (MUX≤63) when dual COM mode is enabled (B[4]=1).
Figure 10-6 : COM Pins Hardware Configuration – 1 (MUX ratio: 128)
Case 1
A[5] =0
Disable Odd Even
Split of COM pins
Case 2
B[4]=0
Disable Dual COM
mode
A[5] =1
Enable Odd Even
Split of COM pins
B[4]=0
Disable Dual COM
mode
ROW126
ROW127
ROW127
ROW125
480 x 128
ROW64
480 x 128
ROW63
ROW2
ROW1
ROW0
ROW0
COM64
COM0
SSD1322Z2
COM127
SSD1322Z2
COM64
COM63
COM126
Pad 1,2,3,…
Gold Bumps face up
COM127
COM0
COM1
COM63
Pad 1,2,3,…
Gold Bumps face up
Figure 10-7 : COM Pins Hardware Configuration – 2 (MUX ratio: 64)
A[5] =0
Disable Odd Even
Split of COM pins
B[4]=1
Enable Dual COM
mode
ROW63
ROW63
ROW62
ROW62
480 x 64
ROW1
ROW1
ROW0
ROW0
COM64
COM65
COM126
SSD1322Z2
COM127
COM63
COM0
COM1
COM62
Pad 1,2,3,…
Gold Bumps face up
SSD1322
Rev 1.2
P 41/60 Jul 2010
Solomon Systech
10.1.7 Set Display Start Line (A1h)
This command is used to set Display Start Line register to determine starting address of display RAM to be
displayed by selecting a value from 0 to 127. Figure 10-8 shows an example of using this command when
MUX ratio = 128 and MUX ratio = 90 and Display Start Line = 40. In there, “Row” means the graphic
display data RAM row.
Figure 10-8 : Example of Set Display Start Line with no Remap
MUX ratio (CAh) = 128 MUX ratio (CAh) = 128 MUX ratio (CAh) = 90
MUX ratio (CAh) = 90
COM Pin Display Start Line (A1h) Display Start Line (A1h) Display Start Line (A1h) Display Start Line (A1h)
=0
= 40
=0
= 40
COM0 ROW0
ROW40
ROW0
ROW40
COM1 ROW1
ROW41
ROW1
ROW41
COM2 ROW2
ROW42
ROW2
ROW42
COM3 ROW3
ROW43
ROW3
ROW43
:
:
:
:
:
:
:
:
:
:
COM48 ROW48
ROW88
ROW48
ROW88
COM49 ROW49
ROW89
ROW49
ROW89
COM50 ROW50
ROW90
ROW50
ROW90
COM51 ROW51
ROW91
ROW51
ROW91
:
:
:
:
:
:
:
:
:
:
COM86 ROW86
ROW126
ROW86
ROW126
COM87 ROW87
ROW127
ROW87
ROW127
COM88 ROW88
ROW0
ROW88
ROW0
COM89 ROW89
ROW1
ROW89
ROW1
COM90 ROW90
ROW2
COM91 ROW91
ROW3
:
:
:
:
:
:
:
:
:
:
COM124 ROW124
ROW36
COM125 ROW125
ROW37
COM126 ROW126
ROW38
COM127 ROW127
ROW39
Display
Example
SSD1322
Rev 1.2
P 42/60 Jul 2010
Solomon Systech
10.1.8 Set Display Offset (A2h)
This command specifies the mapping of display start line (it is assumed that COM0 is the display start line,
display start line register equals to 0) to one of COM0-127. For example, to move the COM39 towards the
COM0 direction for 40 lines, the 7-bit data in the second command should be given by 0101000. The figure
below shows an example of this command. In there, “Row” means the graphic display data RAM row.
Figure 10-9 : Example of Set Display Offset with no Remap
MUX ratio (CAh) = 128
COM Pin Display Offset (A2h)=0
COM0 ROW0
COM1 ROW1
COM2 ROW2
COM3 ROW3
:
:
:
:
COM48 ROW48
COM49 ROW49
COM50 ROW50
COM51 ROW51
:
:
:
:
COM86 ROW86
COM87 ROW87
COM88 ROW88
COM89 ROW89
COM90 ROW90
COM91 ROW91
:
:
:
:
COM124 ROW124
COM125 ROW125
COM126 ROW126
COM127 ROW127
MUX ratio (CAh) = 128
Display Offset (A2h)=40
ROW40
ROW41
ROW42
ROW43
:
:
ROW88
ROW89
ROW90
ROW91
:
:
ROW126
ROW127
ROW0
ROW1
ROW2
ROW3
:
:
ROW36
ROW37
ROW38
ROW39
MUX ratio (CAh) = 90
Display Offset (A2h)=0
ROW0
ROW1
ROW2
ROW3
:
:
ROW48
ROW49
ROW50
ROW51
:
:
ROW86
ROW87
ROW88
ROW89
:
:
-
MUX ratio (CAh) = 90
Display Offset (A2h)=40
ROW40
ROW41
ROW42
ROW43
:
:
ROW88
ROW89
:
:
ROW0
ROW1
R0W2
ROW3
:
:
ROW36
ROW37
ROW38
ROW39
Display
Example
SSD1322
Rev 1.2
P 43/60 Jul 2010
Solomon Systech
10.1.9 Set Display Mode (A4h ~ A7h)
These are single byte command and they are used to set Normal Display, Entire Display ON, Entire Display
OFF and Inverse Display.
• Normal Display (A4h)
Reset the above effect and turn the data to ON at the corresponding gray level. Figure 10-10 shows an
example of Normal Display.
Figure 10-10 : Example of Normal Display
GDDRAM
•
Display
Set Entire Display ON (A5h)
Force the entire display to be at gray scale “GS15” regardless of the contents of the display data RAM
as shown in Figure 10-11.
Figure 10-11 : Example of Entire Display ON
GDDRAM
•
Display
Set Entire Display OFF (A6h)
Force the entire display to be at gray scale level “GS0” regardless of the contents of the display data
RAM as shown in Figure.
Figure 10-12 : Example of Entire Display OFF
GDDRAM
•
Display
Inverse Display (A7h)
The gray level of display data are swapped such that “GS0” ↔ “GS15”, “GS1” ↔ “GS14”, …
Figure 10-13 shows an example of inverse display.
Figure 10-13 : Example of Inverse Display
GDDRAM
SSD1322
Rev 1.2
P 44/60 Jul 2010
Display
Solomon Systech
10.1.10 Enable Partial Display (A8h)
The partial mode display area is defined this triple byte command. Figure 10-14 shows an example of enabling
the partial mode display with start row address A[6:0] = 20h and end start row address B[6:0] = 5Fh at MUX
ratio = 128.
Figure 10-14 : Example of Partial Mode Display
GDDRAM
Display
10.1.11 Exit Partial Display (A9h)
This single byte command is sent to exit the partial mode display area (command A8h).
10.1.12 Set Function selection (ABh)
This double byte command is used to enable or disable the VDD regulator.
Internal VDD regulator is selected when the bit A[0] is set to 1b, while external VDD is selected when A[0] is
set to 0b.
10.1.13 Set Display ON/OFF (AEh / AFh)
These single byte commands are used to turn the OLED panel display ON or OFF.
When the display is ON (command AFh), the selected circuits by Set Master Configuration command will be
turned ON. When the display is OFF (command AEh), those circuits will be turned off, the segment is in VSS
state and common is in high impedance state.
10.1.14 Set Phase Length (B1h)
This double byte command sets the length of phase 1 and 2 of segment waveform of the driver.
• Phase 1 (A[3:0]): Set the period from 5 to 31 in the unit of 2 DCLKs. A larger capacitance of the
OLED pixel may require longer period to discharge the previous data charge completely.
• Phase 2 (A[7:4]): Set the period from 3 to 15 in the unit of DCLKs. A longer period is needed to
charge up a larger capacitance of the OLED pixel to the target voltage VP.
10.1.15 Set Front Clock Divider / Oscillator Frequency (B3h)
This double byte command consists of two functions:
• Front Clock Divide Ratio (A[3:0])
Set the divide ratio to generate DCLK (Display Clock) from CLK. The divide ratio is from 1 to 16,
with reset value = 1. Please refer to Section 8.5 for the detail relationship of DCLK and CLK.
•
Oscillator Frequency (A[7:4])
Program the oscillator frequency Fosc which is the source of CLK if CLS pin is pulled HIGH. The 4bit value results in 16 different frequency settings being available.
SSD1322
Rev 1.2
P 45/60 Jul 2010
Solomon Systech
10.1.16 Display Enhancement A (B4h)
This triple byte command is sent to enhance the display performance.
Setting A[1:0] to 00b enables the external VSL, while the low GS display quality would be improved by
setting B[7:3] to 11111b.
10.1.17 Set GPIO (B5h)
This double byte command is used to set the states of GPIO0 and GPIO1 pins. Refer to Table 9-1 for details.
10.1.18 Set Second Pre-charge period (B6h)
This double byte command is used to set the phase 3 second pre-charge period. The period of phase 3 can be
programmed by command B6h and it is ranged from 0 to 15 DCLK's. Please refer to Table 9-1 for the detail
information.
10.1.19 Set Gray Scale Table (B8h)
This command is used to set each individual gray scale level for the display. Except gray scale levels GS0
that has no pre-charge and current drive, each gray scale level is programmed in the length of current drive
stage pulse width with unit of DCLK. The longer the length of the pulse width, the brighter the OLED pixel
when it’s turned ON. Following the command B8h, the user has to set the gray scale setting for GS1, GS2, …,
GS14, GS15 one by one in sequence. Refer to Section 8.8 for details.
The setting of gray scale table entry can perform gamma correction on OLED panel display. Since the
perception of the brightness scale shall match the image data value in display data RAM, appropriate gray
scale table setting like the example shown below (Figure 10-15) can compensate this effect.
Figure 10-15 : Example of Gamma correction by Gamma Look Up table setting
Brightness
Gamma
Setting
Gamma Look Up
table setting
Gray Scale Table
Brightness
Panel
response
Gamma Setting
Result in linear
response
Gray Scale Table
10.1.20 Select Default Linear Gray Scale Table (B9h)
This single byte command reloads the preset linear Gray Scale table as GS0 =Gamma Setting 0, GS1 =
Gamma Setting 0, GS2 = Gamma Setting 2, ... GS14 = Gamma Setting 104, GS14 = Gamma Setting 112.
Refer to Section 8.8 for details.
10.1.21 Set Pre-charge voltage (BBh)
This double byte command sets the first pre-charge voltage (phase 2) level of segment pins. The level of precharge voltage is programmed with reference to VCC. Refer to Table 9-1 for details.
SSD1322
Rev 1.2
P 46/60 Jul 2010
Solomon Systech
10.1.22 Set VCOMH Voltage (BEh)
This double byte command sets the high voltage level of common pins, VCOMH. The level of VCOMH is
programmed with reference to VCC. Refer to Table 9-1 for details.
10.1.23 Set Contrast Current (C1h)
This double byte command is used to set Contrast Setting of the display. The chip has 256 contrast steps from
00h to FFh. The segment output current ISEG increases linearly with the contrast step, which results in
brighter display.
10.1.24 Master Current Control (C7h)
This double byte command is to control the segment output current by a scaling factor. The chip has 16
master control steps, with the factor ranges from 1 [0000b] to 16 [1111b – default]. The smaller the master
current value, the dimmer the OLED panel display is set.
For example, if original segment output current is 160uA at scale factor = 16, setting scale factor to 8 would
reduce the current to 80uA.
10.1.25 Set Multiplex Ratio (CAh)
This double byte command switches default 1:128 multiplex mode to any multiplex mode from 16 to 128.
For example, when multiplex ratio is set to 16, only 16 common pins are enabled. The starting and the ending
of the enabled common pins are depended on the setting of “Display Offset” register programmed by
command A2h. Figure 10-8 and Figure 10-9 show examples of setting the multiplex ratio through command
CAh.
10.1.26 Display Enhancement B (D1h)
This triple byte command is sent to enhance the display performance.
User is recommended to set A[5:4] to 00b.
10.1.27 Set Command Lock (FDh)
This command is used to lock the OLED driver IC from accepting any command except itself. After entering
FDh 16h (A[2]=1b), the OLED driver IC will not respond to any newly-entered command (except FDh 12h
A[2]=0b) and there will be no memory access. This is call “Lock” state. That means the OLED driver IC
ignore all the commands (except FDh 12h A[2]=0b) during the “Lock” state.
Entering FDh 12h (A[2]=0b) can unlock the OLED driver IC. That means the driver IC resume from the
“Lock” state. And the driver IC will then respond to the command and memory access.
SSD1322
Rev 1.2
P 47/60 Jul 2010
Solomon Systech
11 MAXIMUM RATINGS
Table 11-1 : Maximum Ratings
(Voltage Reference to VSS)
Symbol
Parameter
VDD
VCC
Supply Voltage
VDDIO
VCI
VSEG
SEG output voltage
VCOM
COM output voltage
Vin
Input voltage
TA
Operating Temperature
Tstg
Storage Temperature Range
Value
-0.5 to 2.75
-0.5 to 21.0
-0.5 to VCI
-0.3 to 4.0
0 to VCC
0 to 0.9*VCC
Vss-0.3 to VDDIO+0.3
-40 to +85
-65 to +150
Unit
V
V
V
V
V
V
V
ºC
ºC
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the
Electrical Characteristics tables or Pin Description.
*This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device
is not radiation protected.
SSD1322
Rev 1.2
P 48/60 Jul 2010
Solomon Systech
12
DC CHARACTERISTICS
Conditions (Unless otherwise specified):
Voltage referenced to VSS
VDD = 2.4 to 2.6V
VCI = 2.4 to 3.5V (VCI must be larger than or equal to VDD)
TA = 25°C
Table 12-1 : DC Characteristics
Symbol
VCC
VDD
VCI
VDDIO
VOH
VOL
VIH
VIL
Parameter
Operating Voltage
Logic Supply Voltage
Low voltage power supply
Power Supply for I/O pins
High Logic Output Level
Low Logic Output Level
High Logic Input Level
Low Logic Input Level
ISLP_VDD
VDD Sleep mode Current
ISLP_VDDIO VDDIO Sleep mode Current
ISLP_VCI
IDD
IDDIO
ICI
ICC
ISEG
Dev
VCI Sleep mode Current
VDD Supply Current
VDDIO Supply Current
VCI Supply Current
VCC Supply Current
Segment Output Current
Setting
VCC=20V, IREF=10uA
Segment output current
uniformity
Adjacent pin output
Adj. Dev current uniformity
(contrast = FF)
SSD1322
Rev 1.2
Test Condition
Iout = 100uA
Iout = 100uA
-
Min.
Typ.
Max.
Unit
10
20
V
2.4
2.6
V
2.4
3.5
V
1.65
VCI
V
0.9*VDDIO
VDDIO
V
0
0.1*VDDIO V
0.8*VDDIO
VDDIO
V
0
0.2*VDDIO V
VCI = VDDIO =2.8V, VCC =OFF
VDD(external) = 2.5V, Display OFF,
No panel attached
VCI = VDDIO =2.8V,
External VDD =
VCC =OFF
2.5V
Display OFF,
Internal VDD
No panel attached
External VDD =
2.5V
Enable Internal
VCI = VDDIO =2.8V,
VDD during
VCC =OFF
Sleep mode
Display OFF,
Disable
No panel attached
Internal VDD
during Sleep
mode
-
-
10
uA
-
-
10
uA
-
-
10
uA
-
-
10
uA
-
-
50
uA
-
-
10
uA
VCI = 2.8V, VCC = 18V, VDDIO =
2.8V, External VDD = 2.5V, Display
ON, No panel attached, contrast = FF
VCI = 2.8V, VCC = 18V, External
VDDIO = 2.8V, Display VDD = 2.5V
ON, No panel attached, Internal
contrast = FF
VDD = 2.5V
VCI = 2.8V, VCC = 18V, External
VDDIO = 2.8V, Display VDD = 2.5V
ON, No panel attached, Internal
contrast = FF
VDD = 2.5V
VCI = 2.8V, VCC = 18V, External
VDDIO = 2.8V, Display VDD = 2.5V
ON, No panel attached, Internal
contrast = FF
VDD = 2.5V
Contrast = FF
-
100
130
-
40
50
-
40
50
-
35
45
uA
-
170
220
uA
-
2.2
2.6
mA
-
2.2
2.6
mA
310
340
370
uA
Contrast = 7F
-
170
-
uA
Contrast = 3F
Dev = (ISEG – IMID) / IMID
IMID = (IMAX + IMIN) / 2
ISEG = Segment current at contrast FF
-
85
-
uA
-3
-
3
%
-2
-
2
%
Adj Dev = ( I[n]-I[n+1] ) /
(I[n]+I[n+1])
P 49/60 Jul 2010
uA
uA
uA
Solomon Systech
13 AC CHARACTERISTICS
Conditions:
Voltage referenced to VSS
VDD = 2.4 to2.6V
VCI = 2.4 to 3.5V (VCI must be larger than or equal to VDD)
TA = 25°C
Table 13-1 : AC Characteristics
Symbol
FOSC
(1)
FFRM
tRES
Parameter
Oscillation Frequency of
Display Timing Generator
Test Condition
VCI = 2.8V
480x128 Graphic Display Mode,
Display ON, Internal Oscillator
Enabled
Reset low pulse width (RES#) Frame Frequency for 128
MUX Mode
Min.
Typ.
Max. Unit
1.75
1.94
2.13
MHz
-
FOSC * 1 / (D * K * 128)(2)
-
Hz
3
-
-
us
Note
(1)
FOSC stands for the frequency value of the internal oscillator and the value is measured when command B3h A[7:4] is
in default value.
(2)
D: divide ratio
K: Phase 1 period + Phase 2 period + X
X: DCLKs in current drive period.
Default K is 9 + 7 + 122 = 138
SSD1322
Rev 1.2
P 50/60 Jul 2010
Solomon Systech
Table 13-2 : 6800-Series MCU Parallel Interface Timing Characteristics
(VDD - VSS = 2.4 to 2.6V, VDDIO=1.6V, VCI = 3.3V, TA = 25°C)
Symbol
Parameter
tcycle
Clock Cycle Time
tAS
Address Setup Time
tAH
Address Hold Time
tDSW
Write Data Setup Time
tDHW
Write Data Hold Time
tDHR
Read Data Hold Time
tOH
Output Disable Time
tACC
Access Time
Chip Select Low Pulse Width (read)
PWCSL
Chip Select Low Pulse Width (write)
Chip Select High Pulse Width (read)
PWCSH
Chip Select High Pulse Width (write)
tR
Rise Time
tF
Fall Time
Min
300
10
0
40
7
20
120
60
60
60
-
Typ
-
Max
70
140
Unit
ns
ns
ns
ns
ns
ns
ns
ns
-
-
ns
-
-
ns
-
15
15
ns
ns
Figure 13-1 : 6800-series MCU parallel interface characteristics
D/C#
tAS
tAH
R/W#(WR#)#
E(RD#)
tcycle
PWCSL
CS#
PWCSH
tR
tF
tDHW
tDSW
D[7:0] (WRITE)
Valid Data
tACC
D[7:0] (READ)
tDHR
Valid Data
tOH
SSD1322
Rev 1.2
P 51/60 Jul 2010
Solomon Systech
Table 13-3 : 8080-Series MCU Parallel Interface Timing Characteristics
(VDD - VSS = 2.4 to 2.6V, VDDIO=1.6V, VCI = 3.3V, TA = 25°C)
Symbol
Parameter
tcycle
Clock Cycle Time
tAS
Address Setup Time
tAH
Address Hold Time
tDSW
Write Data Setup Time
tDHW
Write Data Hold Time
tDHR
Read Data Hold Time
tOH
Output Disable Time
tACC
Access Time
tPWLR
Read Low Time
tPWLW
Write Low Time
tPWHR
Read High Time
tPWHW
Write High Time
tR
Rise Time
tF
Fall Time
tCS
Chip select setup time
tCSH
Chip select hold time to read signal
tCSF
Chip select hold time
Min
300
10
0
40
7
20
150
60
60
60
0
0
20
Typ
-
Max
70
140
15
15
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 13-2 : 8080-series MCU parallel interface characteristics
Write cycle
Read cycle
CS#
CS#
tCSF
tCS
D/C#
tCSH
tCS
D/C#
tAH
tAS
tR
tF
tPWLW
R/W#(WR#)
tDSW
D[7:0]
tAS
tcycle
tAH
tPWHW
tDHW
tR
tF
tcycle
tPWLR
tPWHR
E(RD#)
tACC
tDHR
D[7:0]
tOH
SSD1322
Rev 1.2
P 52/60 Jul 2010
Solomon Systech
Table 13-4 : Serial Interface Timing Characteristics (4-wire SPI)
(VDD - VSS = 2.4 to 2.6V, VDDIO=1.6V, VCI = 3.3V, TA = 25°C)
Symbol
tcycle
tAS
tAH
tCSS
tCSH
tDSW
tDHW
tCLKL
tCLKH
tR
tF
Parameter
Clock Cycle Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise Time
Fall Time
Min
100
15
15
20
10
15
15
20
20
-
Typ
-
Max
15
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 13-3 : Serial interface characteristics (4-wire SPI)
D/C#
t AS
t CSS
CS#
t CSH
t cycle
t CLKL
SCLK
(D0)
t AH
tF
tCLKH
tR
t DSW
SDIN
(D1)
t DHW
Valid Data
CS#
SCLK
(D0)
D7
SDIN(D1)
SSD1322
Rev 1.2
D6
P 53/60 Jul 2010
D5
D4
D3
D2
D1
D0
Solomon Systech
Table 13-5: Serial Interface Timing Characteristics (3-wire SPI)
(VDD - VSS = 2.4 to 2.6V, VDDIO=1.6V, VCI = 3.3V, TA = 25°C)
Symbol
tcycle
tCSS
tCSH
tDSW
tDHW
tCLKL
tCLKH
tR
tF
Parameter
Clock Cycle Time
Chip Select Setup Time
Chip Select Hold Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise Time
Fall Time
Min
100
20
10
15
15
20
20
-
Typ
-
Max
15
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 13-4: Serial interface characteristics (3-wire SPI)
t CSS
CS#
t CSH
t CYCLE
tCLKH
t CLKL
SCLK
(D0)
tF
tR
t DSW
SDIN
(D1)
tDHW
Valid Data
CS#
SCLK
(D0)
SDIN
(D1)
SSD1322
D/C#
D7
Rev 1.2
D6
P 54/60 Jul 2010
D5
D4
D3
D2
D1
D0
Solomon Systech
14 APPLICATION EXAMPLES
Figure 14-1 : SSD1322 application example for 8-bit 6800-parallel interface mode (Internal regulated VDD)
The configuration for 8-bit 6800-parallel interface mode, externally VCC is shown in the following diagram:
(VCI =3.3V (VCI must be > 2.6V), Internal regulated VDD = 2.5V, VDDIO =1.8V, external VCC = 18V, IREF = 10uA)
COM1
:
:
:
COM127
SEG0
SEG1
:
:
:
:
:
:
:
:
:
SEG478
SEG479
COM126
:
:
:
COM0
OLED Panel
480x128
VSS
VLSS
VCI
VDDIO
IREF
DOF#
CL
FR
D/C#
CS#
RES#
BS0
BS1
E
R/W#
VDD
VDD1
D[7:0]
DN[9:0]
BGGND
CLS
M/S#
VSL
VCOMH
VCC
VSS
VLSS
SSD1322Z2
R1
C1
C2
C3
R2
D1
C4a
D2
C4b
D/C#
CS#
RES#
18V
VCC
E
R/W#
D[7:0]
C5
1.8V 3.3V
VDDIO VCI
VSS
[GND]
Voltage at IREF = VCC – 6V. For VCC = 18V, IREF = 10uA:
R1 = (Voltage at IREF - VSS) / IREF
= (18 - 6) / 10u
= 1.2MΩ
R2 = 50Ω, 1/8W (1)
D1 - D2 = Vth = 0.7V, 1N4148 (1)
C1 ~ C3: 1uF, C4a and C5: 4.7uF, C4b: 0.1uF
Note
(1)
The value is recommended value. Select appropriate value against module application.
SSD1322
Rev 1.2
P 55/60 Jul 2010
Solomon Systech
Figure 14-2 : SSD1322 application example for 8-bit 6800-parallel interface, dual COM mode (Internal VDD)
The configuration for 8-bit 6800-parallel interface mode, externally VCC is shown in the following diagram:
(VCI =3.3V (VCI must be > 2.6V), Internal regulated VDD = 2.5V, VDDIO =1.8V, external VCC = 18V, IREF = 10uA)
COMB0
:
:
:
COMB63
SEG0
SEG1
:
:
:
:
:
:
:
:
:
SEG478
SEG479
COMA63
:
:
:
COMA0
OLED Panel
480x64
Dual COM
VSS
VLSS
VCI
VDDIO
IREF
DOF#
CL
FR
D/C#
CS#
RES#
BS0
BS1
E
R/W#
VDD
VDD1
D[7:0]
DN[9:0]
BGGND
CLS
M/S#
VSL
VCOMH
VCC
VSS
VLSS
SSD1322Z2
R1
C1
C2
C3
R2
D1
C4a
D2
C4b
D/C#
CS#
RES#
18V
VCC
E
R/W#
D[7:0]
C5
1.8V 3.3V
VDDIO VCI
VSS
[GND]
Voltage at IREF = VCC – 6V. For VCC = 18V, IREF = 10uA:
R1 = (Voltage at IREF - VSS) / IREF
= (18 - 6) / 10u
= 1.2MΩ
R2 = 50Ω, 1/8W (1)
D1 - D2 = Vth = 0.7V, 1N4148 (1)
C1 ~ C3: 1uF, C4a and C5: 4.7uF, C4b: 0.1uF
Note
(1)
The value is recommended value. Select appropriate value against module application.
SSD1322
Rev 1.2
P 56/60 Jul 2010
Solomon Systech
15 PACKAGE INFORMATION
15.1 SSD1322UR1 detail dimension
SSD1322
Rev 1.2
P 57/60 Jul 2010
I/O
VLSS
VCC
VSL
VDD
VCI
VDDIO
NC
RVI
RVI
RVI
RVI
GND
NC
IREF
FR
RES#
DC#
BS1
BS0
E
R/W#
CS#
D0
D2
D1
D3
D5
D4
D6
D7
VCOMH
VCC
VSS
VLSS
UVI
GND
RVI
RVI
RVI
RVI
NC
Figure 15-1: SSD1322UR1 Detail Dimension
Solomon Systech
15.2 SSD1322Z2 Die Tray Information
Figure 15-2: SSD1322Z2 Die Tray Drawing
Remark
1. Tray material: ABS
2. Tray color code: Black
3. Surface resistance 109 ~ 1012 Ω
4. Pocket bottom: Rough Surface
SSD1322
Rev 1.2
P 58/60 Jul 2010
Solomon Systech
Table 15-1: SSD1322Z2 Die Tray Dimensions
W1
W2
H
DX
TPX
DY
TPY
PX
PY
X
Y
Z
Dimensions
mm
(mil)
76.00±0.10 (2992)
68.00±0.10 (2677)
4.20±0.10 (165)
17.39±0.10 (685)
41.22±0.10 (1623)
6.10±0.10 (240)
63.80±0.10 (2512)
13.74±0.05 (541)
2.90±0.05 (114)
12.52±0.05 (493)
1.68±0.05 (66)
0.40±0.05 (16)
N (number of die)
92 (pocket number)
Parameter
SSD1322
Rev 1.2
P 59/60 Jul 2010
Solomon Systech
Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any, and all, liability, including without
limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters,
including “Typical” must be validated for each customer application by the customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the
part.
The product(s) listed in this datasheet comply with Directive 2002/95/EC of the European Parliament and of the council of
27 January 2004 on the restriction of the use of certain hazardous substances in electrical and electronic equipment and
People’s Republic of China Electronic Industry Standard SJ/T 11363-2006 “Requirements for concentration limits for certain
hazardous substances in electronic information products (电子信息产品中有毒有害物质的限量要求)”. Hazardous Substances
test report is available upon request.
http://www.solomon-systech.com
SSD1322
Rev 1.2
P 60/60 Jul 2010
Solomon Systech