SSD1351 - NewHaven Display

SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1351
Advance Information
128 RGB x 128 Dot Matrix
OLED/PLED Segment/Common Driver with Controller
This document contains information on a new product. Specifications and information herein are subject to change
without notice.
http://www.solomon-systech.com
SSD1351
Rev 1.5
P 1/57
Jan 2011
Copyright © 2011 Solomon Systech Limited
Appendix: IC Revision history of SSD1351 Specification
Version
0.10
1.
1.0
1.
2.
3.
4.
5.
6.
1.1
1.
1.2
1
12-Dec-08
Change to Advance Info
Revise die thickness tolerance from ±25um to ±15um
Revise table 12-1 DC characteristic
Revise tables 13 AC characteristic
Revise command table
Revise VCC voltage range
19-Feb-09
Revised section 8.1 MCU interface
27-Oct-09
5
Added +/- 0.05mm tolerance for Die Size (after sawing) in Section 5 – P.9
Added command C1h in the description of command FDh – P.37
Revised typo error on the description of command C1h – P.46
Updated the ISLP VCI sleep mode current section of Table 12-1 (Max = 50uA when
internal VDD is enabled) – P.49
Revised declaimer
1
P.30 Update Power On/OFF sequence
23-Jul-10
1
2
3
4
2
3
1.5
Effective Date
10-Jun-08
31-Aug-09
3
4
1.4
Change Items
Change “Gold Bump Die” to “COG” for SSD1351Z in Table 3-1 Ordering
information
Revise typo in Figure 5 1: SSD1351Z Die Drawing ( position of L, T alignment
mark)
Revise typo in P.45 : 10.1.9 Set Function selection (ABh)
Add Note 2 in application example Fig 14-1
2
1.3
1st release
4
5
1.
2.
3.
4.
5.
6.
7.
8.
9.
P.51 Revise Table 13-2 : 6800-Series MCU Parallel Interface Timing
Characteristics
P.52 Revise Table 13-3 : 8080-Series MCU Parallel Interface Timing
Characteristics
P.53 Revise Table 13-4 : Serial Interface Timing Characteristics (4-wire SPI)
P.54 Revise Table 13-5: Serial Interface Timing Characteristics (3-wire SPI)
Update the power supply on Section 2 (P.7) and Section 12 (P.48)
Updated the pin description of VDD and VCI on Table 7-1 (P.15)
Updated Section 8.9 “Power On and Off sequence” (P.30)
Updated Section 8.10 “VDD Regulator” and Figure 8-15 (P.31)
Updated Figure 8-17 (P.31)
Updated command ABh (Function selection) on Table 9-1 (P.33) and Section 10.1.9
(P.44)
Revise Table 11-1: Maximum Ratings (P.47)
Revise DC CHARACTERISTICS information in Table 12-1 (P.48)
Revise the information on the application example Figure 14-1 and revised the
diagram (P.54)
Solomon Systech
Jan 2011
P 2/57
Rev 1.5
02-Feb-11
SSD1351
CONTENTS
1
GENERAL DESCRIPTION ....................................................................................................7
2
FEATURES................................................................................................................................7
3
ORDERING INFORMATION ................................................................................................7
4
BLOCK DIAGRAM..................................................................................................................8
5
DIE PAD FLOOR PLAN..........................................................................................................9
6
PIN ARRANGEMENT...........................................................................................................12
6.1
SSD1351UR1 PIN ASSIGNMENT .......................................................................................................... 12
7
PIN DESCRIPTIONS .............................................................................................................15
8
FUNCTIONAL BLOCK DESCRIPTIONS..........................................................................18
8.1
MCU INTERFACE ................................................................................................................................ 18
8.1.1
8.1.2
8.1.3
8.1.4
8.2
8.3
MCU Parallel 6800-series Interface................................................................................................................18
MCU Parallel 8080-series Interface................................................................................................................19
MCU Serial Interface (4-wire SPI) .................................................................................................................20
MCU Serial Interface (3-wire SPI) .................................................................................................................21
RESET CIRCUIT .................................................................................................................................... 22
GDDRAM........................................................................................................................................... 22
8.3.1
8.3.2
8.4
8.5
GDDRAM structure........................................................................................................................................22
Data bus to RAM mapping under different input mode..................................................................................23
COMMAND DECODER .......................................................................................................................... 24
OSCILLATOR & TIMING GENERATOR.................................................................................................. 24
8.5.1
8.6
8.7
8.8
8.9
8.10
Oscillator.........................................................................................................................................................24
SEG/COM DRIVING BLOCK ................................................................................................................ 25
SEG / COM DRIVER ............................................................................................................................ 26
GRAY SCALE DECODER ...................................................................................................................... 29
POWER ON AND OFF SEQUENCE ........................................................................................................ 30
VDD REGULATOR ............................................................................................................................. 31
8.10.1
9
VDD Regulator in Sleep Mode.....................................................................................................................31
COMMAND.............................................................................................................................32
9.1
10
BASIC COMMAND LIST........................................................................................................................ 32
COMMAND.............................................................................................................................38
10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
10.1.6
10.1.7
10.1.8
10.1.9
10.1.10
10.1.11
10.1.12
10.1.13
10.1.14
10.1.15
10.1.16
10.1.17
10.1.18
SSD1351
Set Column Address (15h)..........................................................................................................................38
Set Row Address (75h) ...............................................................................................................................38
Write RAM Command (5Ch) .....................................................................................................................39
Read RAM Command (5Dh) ......................................................................................................................39
Set Re-map & Dual COM Line Mode (A0h)..............................................................................................39
Set Display Start Line (A1h).......................................................................................................................41
Set Display Offset (A2h) ............................................................................................................................42
Set Display Mode (A4h ~ A7h) ..................................................................................................................43
Set Function selection (ABh)......................................................................................................................44
Set Sleep mode ON/OFF (AEh / AFh) .......................................................................................................44
Set Phase Length (B1h) ..............................................................................................................................44
Display Enhancement (B2h) .......................................................................................................................44
Set Front Clock Divider / Oscillator Frequency (B3h) ...............................................................................44
Set GPIO (B5h)...........................................................................................................................................44
Set Second Pre-charge period (B6h) ...........................................................................................................45
Look Up Table for Gray Scale Pulse width (B8h) ......................................................................................45
Use Built-in Linear LUT (B9h) ..................................................................................................................45
Set Pre-charge voltage (BBh) .....................................................................................................................45
Rev 1.5
P 3/57
Jan 2011
Solomon Systech
10.1.19
10.1.20
10.1.21
10.1.22
10.1.23
Set VCOMH Voltage (BEh) ...........................................................................................................................45
Set Contrast Current for Color A,B,C (C1h)...............................................................................................46
Master Contrast Current Control (C7h) ......................................................................................................46
Set Multiplex Ratio (CAh)..........................................................................................................................46
Set Command Lock (FDh)..........................................................................................................................46
11
MAXIMUM RATINGS ..........................................................................................................47
12
DC CHARACTERISTICS .....................................................................................................48
13
AC CHARACTERISTICS .....................................................................................................49
14
APPLICATION EXAMPLE ..................................................................................................54
15
PACKAGE INFORMATION ................................................................................................55
15.1
15.2
SSD1351UR1 DETAIL DIMENSION .................................................................................................. 55
SSD1351Z DIE TRAY INFORMATION .............................................................................................. 56
Solomon Systech
Jan 2011
P 4/57
Rev 1.5
SSD1351
TABLES
Table 3-1 : Ordering Information .........................................................................................................................................7
Table 5-1: SSD1351Z Bump Die Pad Coordinates ............................................................................................................10
Table 6-1: SSD1351UR1 Pin Assignment Table................................................................................................................13
Table 7-1 : SSD1351 Pin Description.................................................................................................................................15
Table 7-2 : Bus Interface selection .....................................................................................................................................16
Table 8-1 : MCU interface assignment under different bus interface mode .......................................................................18
Table 8-2 : Data bus selection modes .................................................................................................................................18
Table 8-3 : Control pins of 6800 interface..........................................................................................................................18
Table 8-4 : Control pins of 8080 interface..........................................................................................................................20
Table 8-5 : Control pins of 4-wire Serial interface .............................................................................................................20
Table 8-6 : Control pins of 3-wire Serial interface .............................................................................................................21
Table 8-7 : 262k Color Depth Graphic Display Data RAM Structure................................................................................22
Table 8-8 : Write Data bus usage under different bus width and color depth mode ...........................................................23
Table 8-9 : Read Data bus usage under different bus width and color depth mode............................................................23
Table 9-1 : Command table ................................................................................................................................................32
Table 9-2: SSD1351 Graphic Acceleration Command List................................................................................................37
Table 10-11: Bus interface selection...................................................................................................................................44
Table 11-1 : Maximum Ratings ..........................................................................................................................................47
Table 12-1 : DC Characteristics..........................................................................................................................................48
Table 13-1 : AC Characteristics..........................................................................................................................................49
Table 13-2 : 6800-Series MCU Parallel Interface Timing Characteristics .........................................................................50
Table 13-3 : 8080-Series MCU Parallel Interface Timing Characteristics .........................................................................51
Table 13-4 : Serial Interface Timing Characteristics (4-wire SPI) .....................................................................................52
Table 13-5 : Serial Interface Timing Characteristics (3-wire SPI) .....................................................................................53
SSD1351
Rev 1.5
P 5/57
Jan 2011
Solomon Systech
FIGURES
Figure 4-1 Block Diagram ....................................................................................................................................................8
Figure 5-1: SSD1351Z Die Drawing ....................................................................................................................................9
Figure 6-1: SSD1351UR1 Pin Assignment ........................................................................................................................12
Figure 8-1 : Data read back procedure - insertion of dummy read .....................................................................................19
Figure 8-2 : Example of Write procedure in 8080 parallel interface mode ........................................................................19
Figure 8-3 : Example of Read procedure in 8080 parallel interface mode .........................................................................19
Figure 8-4 : Display data read back procedure - insertion of dummy read.........................................................................20
Figure 8-5 : Write procedure in 4-wire Serial interface mode ............................................................................................21
Figure 8-6 : Write procedure in 3-wire Serial interface mode ............................................................................................21
Figure 8-7 : Oscillator Circuit.............................................................................................................................................24
Figure 8-8 : IREF Current Setting by Resistor Value............................................................................................................25
Figure 8-9 : Segment and Common Driver Block Diagram ...............................................................................................26
Figure 8-10 : Segment and Common Driver Signal Waveform..........................................................................................27
Figure 8-11: Gray Scale Control in Segment......................................................................................................................28
Figure 8-12 : Relation between GDDRAM content and Gray Scale table entry for three colors in 262K color mode
(under command B9h Use Built-in Linear LUT)........................................................................................................29
Figure 8-13 : The Power ON sequence...............................................................................................................................30
Figure 8-14 : The Power OFF sequence .............................................................................................................................30
Figure 8-15 VDD pin connection scheme.............................................................................................................................31
Figure 8-16 : Case 1 - Command sequence for just entering/ exiting sleep mode..............................................................31
Figure 8-17 : Case 2 - Command sequence for disabling internal VDD regulator during sleep mode.................................31
Figure 10-1 : Example of Column and Row Address Pointer Movement ..........................................................................38
Figure 10-2 : Address Pointer Movement of Horizontal Address Increment Mode ...........................................................39
Figure 10-3: Address Pointer Movement of Vertical Address Increment Mode ................................................................39
Figure 10-4 : COM Pins Hardware Configuration (MUX ratio: 128) ................................................................................40
Figure 10-5 : Example of Set Display Start Line with no Remap.......................................................................................41
Figure 10-6 : Example of Set Display Offset with no Remap ...........................................................................................42
Figure 10-7 : Example of Entire Display OFF....................................................................................................................43
Figure 10-8 : Example of Entire Display ON .....................................................................................................................43
Figure 10-9 : Example of Normal Display..........................................................................................................................43
Figure 10-10 : Example of Inverse Display ........................................................................................................................43
Figure 13-1 : 6800-series MCU parallel interface characteristics.......................................................................................50
Figure 13-2 : 8080-series MCU parallel interface characteristics.......................................................................................51
Figure 13-3 : Serial interface characteristics (4-wire SPI)..................................................................................................52
Figure 13-4 : Serial interface characteristics (3-wire SPI)..................................................................................................53
Figure 14-1 : SSD1351Z application example for 18-bit 6800-parallel interface mode.....................................................54
Figure 15-1: SSD1351UR1 Detail Dimension....................................................................................................................55
Figure 15-2: SSD1351UR1 Die Tray Information..............................................................................................................56
Solomon Systech
Jan 2011
P 6/57
Rev 1.5
SSD1351
1
GENERAL DESCRIPTION
The SSD1351 is a CMOS OLED/PLED driver with 384 segments and 128 commons output, supporting
up to 128RGB x 128 dot matrix display. This chip is designed for Common Cathode type OLED/PLED
panel.
The SSD1351 has embedded Graphic Display Data RAM (GDDRAM). It supports with 8, 16, 18 bits
8080 / 6800 parallel interface, Serial Peripheral Interface. It has 256-step contrast and 262K color control,
giving vivid color display on OLED panels.
2
FEATURES
• Resolution: 128 RGB x 128 dot matrix panel
• 262k color depth supported by embedded 128x128x18 bit SRAM display buffer
Power supply
o VDDIO = 1.65V – VCI
(MCU interface logic level)
o VCI = 2.4V – 3.5V
(Low voltage power supply)
o VCC = 10.0V – 18.0V
(Panel driving power supply)
• Segment maximum source current: 200uA
• Common maximum sink current: 70mA
• 256 step brightness current control for the each color component plus 16 step master current control
Pin selectable MCU Interfaces:
o 8/16/18 bits 6800-series parallel interface
o 8/16/18 bits 8080-series parallel interface
o 3 –wire and 4-wire Serial Peripheral Interface
• Support various color depths
o 262k color (6:6:6)
o 65k color (5:6:5)
• Gamma Look Up Tables (GLUT) with 8 bit entry
• Row re-mapping and Column re-mapping
• Vertical and horizontal scrolling
• Programmable Frame Rate and Multiplexing Ratio
• On-Chip Oscillator
• Color Swapping Function (RGB – BGR), arranged in RGB sequence when reset
• Slim chip layout for COF
• Operating temperature range -40°C to 85°C.
3
ORDERING INFORMATION
Table 3-1 : Ordering Information
Ordering Part
Number
SEG
COM
Package
Form
Reference
SSD1351Z
128RGB
128
COG
9 , 56
SSD1351UR1
128RGB
128
COF
12 , 55
SSD1351
Rev 1.5
P 7/57
Jan 2011
Remark
• Min SEG pad pitch: 25um
• Min COM pad pitch: 35um
• Die thickness : 300 +/- 15um
• 48mm film, 4 sprocket hole
• Hot bar type COF
• 8/16/18-bit 80/68/SPI interface
• SEG lead pitch: 0.050x0.999=0.04995mm
• COM lead pitch: 0.06x0.999=0.05994mm
Solomon Systech
4
BLOCK DIAGRAM
Figure 4-1 Block Diagram
BGGND
VDD
VDD Regulator
RES#
BS[1:0]
Common Drivers
(odd)
Gray Scale Decoder
D[17:0]
GDDRAM
CS#
D/C#
R/W#(W/R#)
E(RD#)
MCU Interface
VCI
Segment Drivers
VDDIO
VLSS
VCC
V CI
VSS
Solomon Systech
Common Drivers
(even)
SEG/COM Driving Block
Jan 2011
SC127
SB127
SA127
SC126
SB126
SA126
SC125
SB125
SA125
.
.
.
SC2
SB2
SA2
SC1
SB1
SA1
SC0
SB0
SA0
COM0
COM2
COM4
.
.
.
COM122
COM124
COM126
IREF
FR
CLS
CL
V PP
VCOMH
Display Timing
Generator
GPIO 1
Oscillator
GPIO 0
Command
Decoder
VSL
COM127
COM125
COM123
.
.
.
COM5
COM3
COM1
P 8/57
Rev 1.5
SSD1351
5
DIE PAD FLOOR PLAN
Figure 5-1: SSD1351Z Die Drawing
Y
X
SSD1351
Pad 1,2,3,->613
Gold Bumps face up
Die size (after sawing)
10.7mm ± 0.05mm x 1.5mm ± 0.05mm
Die Thickness
300 +/- 15um
Min I/O pad pitch
70um
Min SEG pad pitch
25um
Min COM pad pitch
35um
Bump height
Nominal 15um
Bump size
Pad 1, 157
49um x 70um
Pad 2-37, 121-156
23um x 70um
Pad 38-120
45um x 90um
Pad 158-189, 582-613
70um x 23um
Pad 192-579
13um x 96um
Pad 190,581
70um x 49um
Pad 191,580
50um x 96um
Alignment mark
SSD1351
Rev 1.5
P 9/57
L shape
(-4736.35, 126.58)
75um x 75um
T shape
(4736.35, 126.58)
75um x 75um
+ shape
(-4736.35, -284.77)
75um x 75um
Jan 2011
Solomon Systech
Table 5-1: SSD1351Z Bump Die Pad Coordinates
Pad # Pad Name
NC
1
COM94
2
COM95
3
COM96
4
COM97
5
COM98
6
COM99
7
COM100
8
COM101
9
COM102
10
COM103
11
COM104
12
COM105
13
COM106
14
COM107
15
COM108
16
COM109
17
COM110
18
COM111
19
COM112
20
COM113
21
COM114
22
COM115
23
COM116
24
COM117
25
COM118
26
COM119
27
COM120
28
COM121
29
COM122
30
COM123
31
COM124
32
COM125
33
COM126
34
COM127
35
VLSS
36
VLSS
37
VLSS
38
VSS
39
VCC
40
VCC
41
VCOMH
42
VLSS
43
VLSS
44
VSS
45
VSS
46
VSL
47
VCI
48
VCI
49
VDD
50
VDD
51
VDD
52
VDD
53
VDD
54
VDDIO
55
VDDIO
56
VLSS
57
GPIO0
58
GPIO1
59
IREF
60
FR
61
CL
62
VSS
63
64
RES#
65
D/C#
66
CS#
VSS
67
BS1
68
VDDIO
69
BS0
70
VSS
71
72 R/W# (WR#
E(RD#)
73
VDDIO
74
VCI
75
VDD
76
VPP
77
VPP
78
D0
79
D1
80
Solomon Systech
X-Axis
-5245.12
-5197.62
-5162.62
-5127.62
-5092.62
-5057.62
-5022.62
-4987.62
-4952.62
-4917.62
-4882.62
-4847.62
-4812.62
-4777.62
-4742.62
-4707.62
-4672.62
-4637.62
-4602.62
-4567.62
-4532.62
-4497.62
-4462.62
-4427.62
-4392.62
-4357.62
-4322.62
-4287.62
-4252.62
-4217.62
-4182.62
-4147.62
-4112.62
-4077.62
-4042.62
-4007.62
-3972.62
-3786.30
-3716.30
-3619.30
-3549.30
-3442.30
-3372.30
-3302.30
-3232.30
-3162.30
-3092.30
-3022.30
-2952.30
-2799.30
-2729.30
-2659.30
-2589.30
-2519.30
-2366.30
-2296.30
-2226.30
-2134.30
-2048.30
-1956.30
-1864.30
-1778.30
-1686.30
-1616.30
-1546.30
-1476.30
-1406.30
-1336.30
-1266.30
-1196.30
-1126.30
-1056.30
-986.30
-916.30
-763.30
-693.30
-579.30
-509.30
-389.30
-303.30
Y-Axis
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
Pad # Pad Name
D2
81
D3
82
D4
83
D5
84
D6
85
D7
86
D8
87
D9
88
D10
89
D11
90
D12
91
D13
92
D14
93
D15
94
D16
95
D17
96
VSS
97
BGGND
98
VSL
99
VSL
100
CLS
101
VDDIO
102
VDDIO
103
VSS
104
VLSS
105
106 VCOMH
107 VCOMH
VCC
108
VCC
109
TR0
110
VCI1
111
TR1
112
TR2
113
TR3
114
TR4
115
VSS1
116
VLSS
117
VLSS
118
VSS
119
VSS
120
VLSS
121
VLSS
122
123 COM63
124 COM62
125 COM61
126 COM60
127 COM59
128 COM58
129 COM57
130 COM56
131 COM55
132 COM54
133 COM53
134 COM52
135 COM51
136 COM50
137 COM49
138 COM48
139 COM47
140 COM46
141 COM45
142 COM44
143 COM43
144 COM42
145 COM41
146 COM40
147 COM39
148 COM38
149 COM37
150 COM36
151 COM35
152 COM34
153 COM33
154 COM32
155 COM31
156 COM30
NC
157
VLSS
158
VLSS
159
160 COM29
X-Axis
-193.30
-107.30
2.70
88.70
198.70
284.70
394.70
480.70
590.70
676.70
786.70
872.70
982.70
1068.70
1178.70
1264.70
1356.70
1426.70
1496.70
1566.70
1636.70
1706.70
1776.70
1890.70
1960.70
2030.70
2100.70
2207.70
2277.70
2395.70
2535.70
2699.70
2949.70
3144.70
3409.70
3479.70
3549.70
3619.70
3689.70
3759.70
3972.62
4007.62
4042.62
4077.62
4112.62
4147.62
4182.62
4217.62
4252.62
4287.62
4322.62
4357.62
4392.62
4427.62
4462.62
4497.62
4532.62
4567.62
4602.62
4637.62
4672.62
4707.62
4742.62
4777.62
4812.62
4847.62
4882.62
4917.62
4952.62
4987.62
5022.62
5057.62
5092.62
5127.62
5162.62
5197.62
5245.12
5234.62
5234.62
5234.62
Y-Axis
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-651.82
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-662.08
-440.04
-405.04
-370.04
Pad # Pad Name
COM28
161
COM27
162
COM26
163
COM25
164
COM24
165
COM23
166
COM22
167
COM21
168
COM20
169
COM19
170
COM18
171
COM17
172
COM16
173
COM15
174
COM14
175
COM13
176
COM12
177
COM11
178
COM10
179
COM9
180
COM8
181
COM7
182
COM6
183
COM5
184
COM4
185
COM3
186
COM2
187
COM1
188
COM0
189
NC
190
VLSS
191
SA0
192
SB0
193
SC0
194
SA1
195
SB1
196
SC1
197
SA2
198
SB2
199
SC2
200
SA3
201
SB3
202
SC3
203
SA4
204
SB4
205
SC4
206
SA5
207
SB5
208
SC5
209
SA6
210
SB6
211
SC6
212
SA7
213
SB7
214
SC7
215
SA8
216
SB8
217
SC8
218
SA9
219
SB9
220
SC9
221
SA10
222
SB10
223
SC10
224
SA11
225
SB11
226
SC11
227
SA12
228
SB12
229
SC12
230
SA13
231
SB13
232
SC13
233
SA14
234
SB14
235
SC14
236
SA15
237
SB15
238
SC15
239
SA16
240
X-Axis
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
5234.62
4890.00
4843.00
4818.00
4793.00
4768.00
4743.00
4718.00
4693.00
4668.00
4643.00
4618.00
4593.00
4568.00
4543.00
4518.00
4493.00
4468.00
4443.00
4418.00
4393.00
4368.00
4343.00
4318.00
4293.00
4268.00
4243.00
4218.00
4193.00
4168.00
4143.00
4118.00
4093.00
4068.00
4043.00
4018.00
3993.00
3968.00
3943.00
3918.00
3893.00
3868.00
3843.00
3818.00
3793.00
3768.00
3743.00
3718.00
3693.00
3668.00
3643.00
Jan 2011
Y-Axis
-335.04
-300.04
-265.04
-230.04
-195.04
-160.04
-125.04
-90.04
-55.04
-20.04
14.96
49.96
84.96
119.96
154.96
189.96
224.96
259.96
294.96
329.96
364.96
399.96
434.96
469.96
504.96
539.96
574.96
609.96
644.96
692.96
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
Pad # Pad Name
SB16
241
SC16
242
SA17
243
SB17
244
SC17
245
SA18
246
SB18
247
SC18
248
SA19
249
SB19
250
SC19
251
SA20
252
SB20
253
SC20
254
SA21
255
SB21
256
SC21
257
SA22
258
SB22
259
SC22
260
SA23
261
SB23
262
SC23
263
SA24
264
SB24
265
SC24
266
SA25
267
SB25
268
SC25
269
SA26
270
SB26
271
SC26
272
SA27
273
SB27
274
SC27
275
SA28
276
SB28
277
SC28
278
SA29
279
SB29
280
SC29
281
SA30
282
SB30
283
SC30
284
SA31
285
SB31
286
SC31
287
SA32
288
SB32
289
SC32
290
SA33
291
SB33
292
SC33
293
SA34
294
SB34
295
SC34
296
SA35
297
SB35
298
SC35
299
SA36
300
SB36
301
SC36
302
SA37
303
SB37
304
SC37
305
SA38
306
SB38
307
SC38
308
SA39
309
SB39
310
SC39
311
SA40
312
SB40
313
SC40
314
SA41
315
SB41
316
SC41
317
SA42
318
SB42
319
SC42
320
P 10/57
X-Axis
3618.00
3593.00
3568.00
3543.00
3518.00
3493.00
3468.00
3443.00
3418.00
3393.00
3368.00
3343.00
3318.00
3293.00
3268.00
3243.00
3218.00
3193.00
3168.00
3143.00
3118.00
3093.00
3068.00
3043.00
3018.00
2993.00
2968.00
2943.00
2918.00
2893.00
2868.00
2843.00
2818.00
2793.00
2768.00
2743.00
2718.00
2693.00
2668.00
2643.00
2618.00
2593.00
2568.00
2543.00
2518.00
2493.00
2468.00
2443.00
2418.00
2393.00
2368.00
2343.00
2318.00
2293.00
2268.00
2243.00
2218.00
2193.00
2168.00
2143.00
2118.00
2093.00
2068.00
2043.00
2018.00
1993.00
1968.00
1943.00
1918.00
1893.00
1868.00
1843.00
1818.00
1793.00
1768.00
1743.00
1718.00
1693.00
1668.00
1643.00
Rev 1.5
Y-Axis
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
SSD1351
Pad # Pad Name
SA43
321
SB43
322
SC43
323
SA44
324
SB44
325
SC44
326
SA45
327
SB45
328
SC45
329
SA46
330
SB46
331
SC46
332
SA47
333
SB47
334
SC47
335
SA48
336
SB48
337
SC48
338
SA49
339
SB49
340
SC49
341
SA50
342
SB50
343
SC50
344
SA51
345
SB51
346
SC51
347
SA52
348
SB52
349
SC52
350
SA53
351
SB53
352
SC53
353
SA54
354
SB54
355
SC54
356
SA55
357
SB55
358
SC55
359
SA56
360
SB56
361
SC56
362
SA57
363
SB57
364
SC57
365
SA58
366
SB58
367
SC58
368
SA59
369
SB59
370
SC59
371
SA60
372
SB60
373
SC60
374
SA61
375
SB61
376
SC61
377
SA62
378
SB62
379
SC62
380
SA63
381
SB63
382
SC63
383
SA64
384
SB64
385
SC64
386
SA65
387
SB65
388
SC65
389
SA66
390
SB66
391
SC66
392
SA67
393
SB67
394
SC67
395
SA68
396
SB68
397
SC68
398
SA69
399
SB69
400
SSD1351
X-Axis
1618.00
1593.00
1568.00
1543.00
1518.00
1493.00
1468.00
1443.00
1418.00
1393.00
1368.00
1343.00
1318.00
1293.00
1268.00
1243.00
1218.00
1193.00
1168.00
1143.00
1118.00
1093.00
1068.00
1043.00
1018.00
993.00
968.00
943.00
918.00
893.00
868.00
843.00
818.00
793.00
768.00
743.00
718.00
693.00
668.00
643.00
618.00
593.00
568.00
543.00
518.00
493.00
468.00
443.00
418.00
393.00
368.00
343.00
318.00
293.00
268.00
243.00
218.00
193.00
168.00
143.00
118.00
93.00
68.00
43.00
18.00
-7.00
-32.00
-57.00
-82.00
-107.00
-132.00
-157.00
-182.00
-207.00
-232.00
-257.00
-282.00
-307.00
-332.00
-357.00
Rev 1.5
Y-Axis
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
Pad # Pad Name
SC69
401
SA70
402
SB70
403
SC70
404
SA71
405
SB71
406
SC71
407
SA72
408
SB72
409
SC72
410
SA73
411
SB73
412
SC73
413
SA74
414
SB74
415
SC74
416
SA75
417
SB75
418
SC75
419
SA76
420
SB76
421
SC76
422
SA77
423
SB77
424
SC77
425
SA78
426
SB78
427
SC78
428
SA79
429
SB79
430
SC79
431
VCC
432
VCC
433
VCC
434
VCC
435
SA80
436
SB80
437
SC80
438
SA81
439
SB81
440
SC81
441
SA82
442
SB82
443
SC82
444
SA83
445
SB83
446
SC83
447
SA84
448
SB84
449
SC84
450
SA85
451
SB85
452
SC85
453
SA86
454
SB86
455
SC86
456
SA87
457
SB87
458
SC87
459
SA88
460
SB88
461
SC88
462
SA89
463
SB89
464
SC89
465
SA90
466
SB90
467
SC90
468
SA91
469
SB91
470
SC91
471
SA92
472
SB92
473
SC92
474
SA93
475
SB93
476
SC93
477
SA94
478
SB94
479
SC94
480
P 11/57
X-Axis
-382.00
-407.00
-432.00
-457.00
-482.00
-507.00
-532.00
-557.00
-582.00
-607.00
-632.00
-657.00
-682.00
-707.00
-732.00
-757.00
-782.00
-807.00
-832.00
-857.00
-882.00
-907.00
-932.00
-957.00
-982.00
-1007.00
-1032.00
-1057.00
-1082.00
-1107.00
-1132.00
-1158.00
-1186.00
-1214.00
-1242.00
-1268.00
-1293.00
-1318.00
-1343.00
-1368.00
-1393.00
-1418.00
-1443.00
-1468.00
-1493.00
-1518.00
-1543.00
-1568.00
-1593.00
-1618.00
-1643.00
-1668.00
-1693.00
-1718.00
-1743.00
-1768.00
-1793.00
-1818.00
-1843.00
-1868.00
-1893.00
-1918.00
-1943.00
-1968.00
-1993.00
-2018.00
-2043.00
-2068.00
-2093.00
-2118.00
-2143.00
-2168.00
-2193.00
-2218.00
-2243.00
-2268.00
-2293.00
-2318.00
-2343.00
-2368.00
Jan 2011
Y-Axis
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
Pad # Pad Name
SA95
481
SB95
482
SC95
483
SA96
484
SB96
485
SC96
486
SA97
487
SB97
488
SC97
489
SA98
490
SB98
491
SC98
492
SA99
493
SB99
494
SC99
495
SA100
496
SB100
497
SC100
498
SA101
499
SB101
500
SC101
501
SA102
502
SB102
503
SC102
504
SA103
505
SB103
506
SC103
507
SA104
508
SB104
509
SC104
510
SA105
511
SB105
512
SC105
513
SA106
514
SB106
515
SC106
516
SA107
517
SB107
518
SC107
519
SA108
520
SB108
521
SC108
522
SA109
523
SB109
524
SC109
525
SA110
526
SB110
527
SC110
528
SA111
529
SB111
530
SC111
531
SA112
532
SB112
533
SC112
534
SA113
535
SB113
536
SC113
537
SA114
538
SB114
539
SC114
540
SA115
541
SB115
542
SC115
543
SA116
544
SB116
545
SC116
546
SA117
547
SB117
548
SC117
549
SA118
550
SB118
551
SC118
552
SA119
553
SB119
554
SC119
555
SA120
556
SB120
557
SC120
558
SA121
559
SB121
560
X-Axis
-2393.00
-2418.00
-2443.00
-2468.00
-2493.00
-2518.00
-2543.00
-2568.00
-2593.00
-2618.00
-2643.00
-2668.00
-2693.00
-2718.00
-2743.00
-2768.00
-2793.00
-2818.00
-2843.00
-2868.00
-2893.00
-2918.00
-2943.00
-2968.00
-2993.00
-3018.00
-3043.00
-3068.00
-3093.00
-3118.00
-3143.00
-3168.00
-3193.00
-3218.00
-3243.00
-3268.00
-3293.00
-3318.00
-3343.00
-3368.00
-3393.00
-3418.00
-3443.00
-3468.00
-3493.00
-3518.00
-3543.00
-3568.00
-3593.00
-3618.00
-3643.00
-3668.00
-3693.00
-3718.00
-3743.00
-3768.00
-3793.00
-3818.00
-3843.00
-3868.00
-3893.00
-3918.00
-3943.00
-3968.00
-3993.00
-4018.00
-4043.00
-4068.00
-4093.00
-4118.00
-4143.00
-4168.00
-4193.00
-4218.00
-4243.00
-4268.00
-4293.00
-4318.00
-4343.00
-4368.00
Y-Axis
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
Pad # Pad Name
SC121
561
SA122
562
SB122
563
SC122
564
SA123
565
SB123
566
SC123
567
SA124
568
SB124
569
SC124
570
SA125
571
SB125
572
SC125
573
SA126
574
SB126
575
SC126
576
SA127
577
SB127
578
SC127
579
VLSS
580
NC
581
582 COM64
583 COM65
584 COM66
585 COM67
586 COM68
587 COM69
588 COM70
589 COM71
590 COM72
591 COM73
592 COM74
593 COM75
594 COM76
595 COM77
596 COM78
597 COM79
598 COM80
599 COM81
600 COM82
601 COM83
602 COM84
603 COM85
604 COM86
605 COM87
606 COM88
607 COM89
608 COM90
609 COM91
610 COM92
611 COM93
VLSS
612
VLSS
613
X-Axis
-4393.00
-4418.00
-4443.00
-4468.00
-4493.00
-4518.00
-4543.00
-4568.00
-4593.00
-4618.00
-4643.00
-4668.00
-4693.00
-4718.00
-4743.00
-4768.00
-4793.00
-4818.00
-4843.00
-4890.00
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
-5234.62
Y-Axis
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
681.25
692.96
644.96
609.96
574.96
539.96
504.96
469.96
434.96
399.96
364.96
329.96
294.96
259.96
224.96
189.96
154.96
119.96
84.96
49.96
14.96
-20.04
-55.04
-90.04
-125.04
-160.04
-195.04
-230.04
-265.04
-300.04
-335.04
-370.04
-405.04
-440.04
Solomon Systech
6
PIN ARRANGEMENT
6.1
SSD1351UR1 pin assignment
Solomon Systech
COM12 5
COM12 7
NC
NC
NC
NC
V CI
NC
V SS
4
NC
NC
COM1
COM3
SA12 7
SB12 7
SC12 7
NC
NC
11 NC
10 NC
SA0
SB0
SC0
V COMH
31
COM0
NC
NC
NC
3 COM12 6
2 COM12 4
Figure 6-1: SSD1351UR1 Pin Assignment
Jan 2011
P 12/57
Rev 1.5
SSD1351
Table 6-1: SSD1351UR1 Pin Assignment Table
Pad#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SSD1351
Rev 1.5
Pad Name
NC
VCC
VCOMH
VDDIO
VSL
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
E (RD#)
R/W# (WR#)
BS0
BS1
NC
CS#
D/C#
RES#
IREF
VDD
NC
NC
VCI
NC
VSS
NC
NC
NC
COM127
COM126
COM125
COM124
COM123
COM122
COM121
COM120
COM119
COM118
COM117
COM116
COM115
COM114
COM113
COM112
COM111
COM110
COM109
COM108
COM107
COM106
COM105
COM104
COM103
COM102
COM101
COM100
COM99
COM98
COM97
COM96
COM95
COM94
COM93
COM92
COM91
COM90
COM89
P 13/57
Pad#
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Jan 2011
Pad Name
COM88
COM87
COM86
COM85
COM84
COM83
COM82
COM81
COM80
COM79
COM78
COM77
COM76
COM75
COM74
COM73
COM72
COM71
COM70
COM69
COM68
COM67
COM66
COM65
COM64
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SC127
SB127
SA127
SC126
SB126
SA126
SC125
SB125
SA125
SC124
SB124
SA124
SC123
SB123
SA123
SC122
SB122
SA122
SC121
SB121
SA121
SC120
SB120
SA120
SC119
SB119
SA119
SC118
SB118
SA118
SC117
SB117
SA117
SC116
SB116
Pad#
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Pad Name
SA116
SC115
SB115
SA115
SC114
SB114
SA114
SC113
SB113
SA113
SC112
SB112
SA112
SC111
SB111
SA111
SC110
SB110
SA110
SC109
SB109
SA109
SC108
SB108
SA108
SC107
SB107
SA107
SC106
SB106
SA106
SC105
SB105
SA105
SC104
SB104
SA104
SC103
SB103
SA103
SC102
SB102
SA102
SC101
SB101
SA101
SC100
SB100
SA100
SC99
SB99
SA99
SC98
SB98
SA98
SC97
SB97
SA97
SC96
SB96
SA96
SC95
SB95
SA95
SC94
SB94
SA94
SC93
SB93
SA93
SC92
SB92
SA92
SC91
SB91
SA91
SC90
SB90
SA90
SC89
Pad#
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
Pad Name
SB89
SA89
SC88
SB88
SA88
SC87
SB87
SA87
SC86
SB86
SA86
SC85
SB85
SA85
SC84
SB84
SA84
SC83
SB83
SA83
SC82
SB82
SA82
SC81
SB81
SA81
SC80
SB80
SA80
SC79
SB79
SA79
SC78
SB78
SA78
SC77
SB77
SA77
SC76
SB76
SA76
SC75
SB75
SA75
SC74
SB74
SA74
SC73
SB73
SA73
SC72
SB72
SA72
SC71
SB71
SA71
SC70
SB70
SA70
SC69
SB69
SA69
SC68
SB68
SA68
SC67
SB67
SA67
SC66
SB66
SA66
SC65
SB65
SA65
SC64
SB64
SA64
SC63
SB63
SA63
Solomon Systech
Pad#
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
Solomon Systech
Pad Name
SC62
SB62
SA62
SC61
SB61
SA61
SC60
SB60
SA60
SC59
SB59
SA59
SC58
SB58
SA58
SC57
SB57
SA57
SC56
SB56
SA56
SC55
SB55
SA55
SC54
SB54
SA54
SC53
SB53
SA53
SC52
SB52
SA52
SC51
SB51
SA51
SC50
SB50
SA50
SC49
SB49
SA49
SC48
SB48
SA48
SC47
SB47
SA47
SC46
SB46
SA46
SC45
SB45
SA45
SC44
SB44
SA44
SC43
SB43
SA43
SC42
SB42
SA42
SC41
SB41
SA41
SC40
SB40
SA40
SC39
SB39
SA39
SC38
SB38
SA38
SC37
SB37
SA37
SC36
SB36
Pad#
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
Pad Name
SA36
SC35
SB35
SA35
SC34
SB34
SA34
SC33
SB33
SA33
SC32
SB32
SA32
SC31
SB31
SA31
SC30
SB30
SA30
SC29
SB29
SA29
SC28
SB28
SA28
SC27
SB27
SA27
SC26
SB26
SA26
SC25
SB25
SA25
SC24
SB24
SA24
SC23
SB23
SA23
SC22
SB22
SA22
SC21
SB21
SA21
SC20
SB20
SA20
SC19
SB19
SA19
SC18
SB18
SA18
SC17
SB17
SA17
SC16
SB16
SA16
SC15
SB15
SA15
SC14
SB14
SA14
SC13
SB13
SA13
SC12
SB12
SA12
SC11
SB11
SA11
SC10
SB10
SA10
SC9
Pad#
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
Pad Name
SB9
SA9
SC8
SB8
SA8
SC7
SB7
SA7
SC6
SB6
SA6
SC5
SB5
SA5
SC4
SB4
SA4
SC3
SB3
SA3
SC2
SB2
SA2
SC1
SB1
SA1
SC0
SB0
SA0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
Jan 2011
Pad#
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
P 14/57
Pad Name
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
NC
NC
Rev 1.5
SSD1351
7
PIN DESCRIPTIONS
Key:
I = Input
O =Output
I/O = Bi-directional (input/output)
P = Power pin
NC = Not Connected
Pull LOW= connect to Ground
Pull HIGH= connect to VDDIO
Table 7-1 : SSD1351 Pin Description
Pin Name
VDD
Pin Type Description
P
Power supply for core logic operation. A capacitor is necessary to connected between
this pin and VSS. It is regulated internally from VCI.
Refer to Section 8.10 for details.
Power supply for interface logic level. It should match with the MCU interface
voltage level and must be connected to external source.
VDDIO
P
VCI
P
VCC
P
Refer to Section 8.10 for details.
Power supply for panel driving voltage. This is also the most positive power voltage
supply pin. It is supplied by external high voltage source.
VPP
P
Reserved pin. It must be connected to VDD.
VSS
P
Ground pin
VLSS
P
Analog system ground pin
VCOMH
P
COM signal deselected voltage level.
A capacitor should be connected between this pin and VSS.
BGGND
P
It should be connected to Ground.
Low voltage power supply
VCI must always be equal to or higher than VDDIO.
GPIO0
I/O
Detail refer to Command B5h
GPIO1
I/O
Detail refer to Command B5h
VSL
P
This is segment voltage reference pin. External VSL is set as default. This pin has to
connect with resistor and diode to ground. (details depend on application)
Refer to Command B4h for details.
SSD1351
Rev 1.5
P 15/57
Jan 2011
Solomon Systech
Pin Name
BS[1:0]
Pin Type Description
I
MCU bus interface selection pins. Select appropriate logic setting as described in the
following table. BS3 and BS2 are command programmable (by command ABh).
[reset = 00]. BS1 and BS0 are pin select.
Table 7-2 : Bus Interface selection
BS[3:0]
XX00
XX01
0011
0010
0111
0110
1111
1110
Interface
4 line SPI
3 line SPI
8-bit 6800 parallel
8-bit 8080 parallel
16-bit 6800 parallel
16-bit 8080 parallel
18-bit 6800 parallel
18-bit 8080 parallel
Note
(1)
0 is connected to VSS
(2)
1 is connected to VDDIO
IREF
I
This pin is the segment output current reference pin.
A resistor should be connected between this pin and VSS.
CL
I
External clock input pin.
When internal clock is enable (i.e. pull HIGH in CLS pin), this pin is not used and
should be connected to Ground.
When internal clock is disable (i.e. pull LOW in CLS pin), this pin is the external
clock source input pin.
CLS
I
Internal clock selection pin.
When this pin is pulled HIGH, internal oscillator is enabled (normal operation).
When this pin is pulled LOW, an external clock signal should be connected to CL.
CS#
I
This pin is the chip select input connecting to the MCU.
The chip is enabled for MCU communication only when CS# is pulled LOW.
RES#
I
This pin is reset signal input.
When the pin is pulled LOW, initialization of the chip is executed.
Keep this pin pull HIGH during normal operation.
D/C#
I
This pin is Data/Command control pin connecting to the MCU.
When the pin is pulled HIGH, the data at D[17:0] will be interpreted as data.
When the pin is pulled LOW, the data at D[17:0] will be interpreted as command.
R/W# (WR#)
I
This pin is read / write control input pin connecting to the MCU interface.
When 6800 interface mode is selected, this pin will be used as Read/Write (R/W#)
selection input. Read mode will be carried out when this pin is pulled HIGH and
write mode when LOW.
When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data
write operation is initiated when this pin is pulled LOW and the chip is selected.
When serial interface is selected, this pin R/W (WR#) must be connected to VSS.
Solomon Systech
Jan 2011
P 16/57
Rev 1.5
SSD1351
Pin Name
E (RD#)
Pin Type Description
I
This pin is MCU interface input.
When 6800 interface mode is selected, this pin will be used as the Enable (E) signal.
Read/write operation is initiated when this pin is pulled HIGH and the chip is
selected.
When 8080 interface mode is selected, this pin receives the Read (RD#) signal. Read
operation is initiated when this pin is pulled LOW and the chip is selected.
When serial interface is selected, this pin E(RD#) must be connected to VSS.
D[17:0]
I/O
These pins are bi-directional data bus connecting to the MCU data bus.
Unused pins are recommended to tie LOW. (Except for D2 pin in SPI mode)
FR
O
This pin is reserved pin. No connection is necessary and should be left open
individually.
TR[4:0]
O
These are reserved pins. No connection is necessary and should be left open
individually.
VSS1
P
This pin is reserved pin. It should be connected to VSS.
VCI1
P
This pin is reserved pin. No connection is necessary and should be left open
individually.
SA[127:0]
SB[127:0]
SC[127:0]
O
These pins provide the OLED segment driving signals. These pins are VSS state when
display is OFF.
The 384 segment pins are divided into 3 groups, SA, SB and SC. Each group can
have different color settings for color A, B and C.
COM[127:0]
SSD1351
Rev 1.5
I/O
P 17/57
These pins provide the Common switch signals to the OLED panel.
Jan 2011
Solomon Systech
8
FUNCTIONAL BLOCK DESCRIPTIONS
8.1
MCU Interface
SSD1351 MCU interface consist of 18 data pin and 5 control pins. The pin assignment at different interface
mode is summarized in Table 8-1. Different MCU mode can be set by hardware selection on BS[1:0] pins
and software command on BS[3:0].(refer to Table 7-2 for BS[3:0] setting)
Table 8-1 : MCU interface assignment under different bus interface mode
Pin Name
Bus Interface
8b / 8080
8b / 6800
16b / 8080
16b / 6800
18b / 8080
18b / 6800
SPI 4-wire
SPI 3-Wire
Data / Command Interface
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
Tie Low
Tie Low
Tie Low
D[15:0]
Tie Low
D[15:0]
D[17:0]
D[17:0]
Tie Low
Tie Low
D5
D4
D3 D2
D[7:0]
D[7:0]
D1
D0
NC SDIN SCLK
NC SDIN SCLK
Control Signal
E
R/W# CS#
D/C#
RD#
WR#
CS#
D/C#
E
R/W# CS#
D/C#
RD#
WR#
CS#
D/C#
E
R/W# CS#
D/C#
RD#
WR#
CS#
D/C#
E
R/W# CS#
D/C#
Tie Low
CS#
D/C#
Tie Low
CS# Tie Low
RES#
RES#
RES#
RES#
RES#
RES#
RES#
RES#
RES#
Table 8-2 : Data bus selection modes
Data Read
Data Write
Command Read
Command Write
6800 – series Parallel
Interface
18-/16-/8-bits
18-/16-/8-bits
Yes. Refer to section 9
Yes
8080 – series Parallel
Interface
18-/16-/8-bits
18-/16-/8-bits
Yes. Refer to section 9
Yes
3-wire Serial Interface or
4-wire Serial Interface
No
8-bits
No
Yes
8.1.1 MCU Parallel 6800-series Interface
The parallel interface consists of 18 bi-directional data pins (D[17:0]), R/W#, D/C#, E and CS#.
A LOW in R/W# indicates WRITE operation and HIGH in R/W# indicates READ operation.
A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.
The E input serves as data latch signal while CS# is LOW. Data is latched at the falling edge of E signal.
Table 8-3 : Control pins of 6800 interface
Function
E
R/W#
CS#
D/C#
Write command
↓
L
L
L
Read status
↓
H
L
L
Write data
↓
L
L
H
Read data
↓
H
L
H
Note
(1)
↓ stands for falling edge of signal
(2)
H stands for HIGH in signal
(3)
L stands for LOW in signal
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual display
data read. This is shown in Figure 8-1.
Solomon Systech
Jan 2011
P 18/57
Rev 1.5
SSD1351
Figure 8-1 : Data read back procedure - insertion of dummy read
R/W#
E
N
Databus
Write column
address
Dummy read
n
n+1
Read 1st data
Read 2nd data
n+2
Read 3rd data
8.1.2 MCU Parallel 8080-series Interface
The parallel interface consists of 18 bi-directional data pins (D[17:0]), RD#, WR#, D/C# and CS#.
A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.
A rising edge of RD# input serves as a data READ latch signal while CS# is kept LOW.
A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept LOW.
Figure 8-2 : Example of Write procedure in 8080 parallel interface mode
CS#
WR#
D[17:0]
D/C#
high
RD#
low
Figure 8-3 : Example of Read procedure in 8080 parallel interface mode
CS#
RD#
D[17:0]
D/C#
WR#
high
low
SSD1351
Rev 1.5
P 19/57
Jan 2011
Solomon Systech
Table 8-4 : Control pins of 8080 interface
Function
Write command
Read status
Write data
Read data
RD#
H
↑
H
↑
WR#
↑
H
↑
H
CS#
L
L
L
L
D/C#
L
L
H
H
Note
(1)
↑ stands for rising edge of signal
(2)
H stands for HIGH in signal
(3)
L stands for LOW in signal
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual display
data read. This is shown in Figure 8-4.
Figure 8-4 : Display data read back procedure - insertion of dummy read
WR#
RD#
Databus
N
Write column
address
Dummy read
n
n+1
Read 1st data
Read 2nd data
n+2
Read 3rd data
8.1.3 MCU Serial Interface (4-wire SPI)
The 4-wire serial interface consists of serial clock: SCLK, serial data: SDIN, D/C#, CS#. In 4-wire SPI mode,
D0 acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. The pins from D3 to
D17and E can be connected to an external ground.
Table 8-5 : Control pins of 4-wire Serial interface
Function
Write command
Write data
E
Tie LOW
Tie LOW
CS#
L
L
D/C#
L
H
Note
(1)
H stands for HIGH in signal
(2)
L stands for LOW in signal
SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C#
is sampled on every eighth clock and the data byte in the shift register is written to the Graphic Display Data
RAM (GDDRAM) or command register in the same clock.
Under serial mode, only write operations are allowed.
Solomon Systech
Jan 2011
P 20/57
Rev 1.5
SSD1351
Figure 8-5 : Write procedure in 4-wire Serial interface mode
CS#
D/C#
SDIN/
SCLK
DB1
DB2
DBn
SCLK
(D0)
SDIN(D1)
D7
D6
D5
D4
D3
D2
D0
D1
8.1.4 MCU Serial Interface (3-wire SPI)
The 3-wire serial interface consists of serial clock SCLK, serial data SDIN and CS#.
In 3-wire SPI mode, D0 acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open.
The pins from D3 to D17, R/W# (WR#), E(RD#) and D/C# can be connected to an external ground.
The operation is similar to 4-wire serial interface while D/C# pin is not used. There are altogether 9-bits will
be shifted into the shift register on every ninth clock in sequence: D/C# bit, D7 to D0 bit. The D/C# bit (first
bit of the sequential data) will determine the following data byte in the shift register is written to the Display
Data RAM (D/C# bit = 1) or the command register (D/C# bit = 0). Under serial mode, only write operations
are allowed.
Table 8-6 : Control pins of 3-wire Serial interface
Function
Write command
Write data
E(RD#)
Tie LOW
Tie LOW
R/W#(WR#)
Tie LOW
Tie LOW
CS#
L
L
D/C#
Tie LOW
Tie LOW
D0
↑
↑
Note
L stands for LOW in signal
(1)
Figure 8-6 : Write procedure in 3-wire Serial interface mode
CS#
SDIN/
SCLK
DB1
DB2
DBn
SCLK
(D0)
D/C#
SDIN(D1)
SSD1351
Rev 1.5
D7
P 21/57
D6
Jan 2011
D5
D4
D3
D2
D1
D0
Solomon Systech
8.2 Reset Circuit
When RES# input is pulled LOW, the chip is initialized with the following status:
1. Display is OFF
2. 128 MUX Display Mode
3. Normal segment and display data column address and row address mapping (SEG0 mapped to
address 00h and COM0 mapped to address 00h)
4. Display start line is set at display RAM address 0
5. Column address counter is set at 0
6. Normal scan direction of the COM outputs
7. Command A2h,B1h,B3h,BBh,BEh are locked by command FDh
8.3
GDDRAM
8.3.1
GDDRAM structure
The GDDRAM is a bit mapped static RAM holding the pattern to be displayed. The RAM size is 128 x 128 x
18bits. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by
software. Each pixel has 18-bit data. Each sub-pixels for color A, B and C have 6 bits. The arrangement of
data pixel in graphic display data RAM is shown in Table 8-7
Table 8-7 : 262k Color Depth Graphic Display Data RAM Structure
Normal
Segment
Address Remapped
Color
Data
Format
Common
Address
Normal
0
1
2
3
4
5
6
7
:
:
:
123
124
125
126
127
Remapped
127
126
125
124
123
122
121
120
:
:
:
4
3
2
1
0
SEG output
Solomon Systech
A
A5
A4
A3
A2
A1
A0
0
127
B
B5
B4
B3
B2
B1
B0
6
6
6
6
6
6
6
6
6
6
6
6
6
6
:
:
:
6
6
6
6
6
:
:
:
6
6
6
6
6
:
:
:
6
6
6
6
6
:
:
:
6
6
6
6
6
SA0
SB0
SC0
SA1
C
C5
C4
C3
C2
C1
C0
6
6
6
6
6
6
no of bits
A
A5
A4
A3
A2
A1
A0
1
126
B
B5
B4
B3
B2
B1
B0
C
C5
C4
C3
C2
C1
C0
2
125
A
A5
A4
A3
A2
A1
A0
6
6
6
6
6
6
6
6
6
6
6
6
6
6
:
:
:
6
6
6
6
6
:
:
:
6
6
6
6
6
:
:
:
6
6
6
6
6
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
SB1
SC1
SA2
……
6
6
6
6
6
6
6
6
6
6
6
6
in this cell
……
……
……
……
……
……
……
……
……
……
126
1
C
C5
C4
C3
C2
C1
C0
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
6
6
6
6
6
6
6
6
:
:
:
6
6
6
6
6
……
Jan 2011
A
A5
A4
A3
A2
A1
A0
127
0
B
B5
B4
B3
B2
B1
B0
C
C5
C4
C3
C2
C1
C0
6
6
6
6
6
6
6
6
:
:
:
6
6
6
6
6
6
6
6
6
6
6
6
6
:
:
:
6
6
6
6
6
6
6
6
6
6
6
6
6
:
:
:
6
6
6
6
6
Common
output
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
:
:
:
:
COM124
COM125
COM126
COM127
SC126 SA127 SB127 SC127
P 22/57
Rev 1.5
SSD1351
8.3.2
Data bus to RAM mapping under different input mode
Table 8-8 : Write Data bus usage under different bus width and color depth mode
Write Data
8 bits/Se rial
8 bits/Se rial
65k
262k
16 bits
65k
16 bits
262k
format 1
16 bits
262k
format 2
18 bits
262k
Data bus
D9
D8
D17
D16
D15
D14
D13
D12
D11
D10
1st
X
X
X
X
X
X
X
X
X
2nd
X
X
X
X
X
X
X
X
X
1st
X
X
X
X
X
X
X
X
2nd
X
X
X
X
X
X
X
3rd
X
X
X
X
X
X
X
X
X
C4
C3
C2
C1
C0
Bus width C olor De pth Input orde r
D7
D6
D5
D4
D3
D2
D1
D0
X
C4
C3
C2
C1
C0
B5
B4
B3
X
B2
B1
B0
A4
A3
A2
A1
A0
X
X
X
X
C5
C4
C3
C2
C1
C0
X
X
X
X
X
B5
B4
B3
B2
B1
B0
X
X
X
X
X
A5
A4
A3
A2
A1
A0
B5
B4
B3
B2
B1
B0
A4
A3
A2
A1
A0
1st
X
X
X
X
X
X
X
X
X
X
X
X
C5
C4
C3
C2
C1
C0
2nd
X
X
X
X
B5
B4
B3
B2
B1
B0
X
X
A5
A4
A3
A2
A1
A0
1st
X
X
X
X
C15
C14
C13
C12
C11
C10
X
X
B15
B14
B13
B12
B11
B10
2nd
X
X
X
X
A15
A14
A13
A12
A11
A10
X
X
C25
C24
C23
C22
C21
C20
3rd
X
X
X
X
B25
B24
B23
B22
B21
B20
X
X
A25
A24
A23
A22
A21
A20
C5
C4
C3
C2
C1
C0
B5
B4
B3
B2
B1
B0
A5
A4
A3
A2
A1
A0
Table 8-9 : Read Data bus usage under different bus width and color depth mode
Read Data
8 bits
8 bits
65k
262k
16 bits
65k
16 bits
262k
format 1
16 bits
262k
format 2
18 bits
262k
D16
D15
D14
D13
D12
D11
D10
D7
D6
D5
D4
D3
D2
D1
D0
1st
X
X
X
X
X
X
X
X
X
X
C4
C3
C2
C1
C0
B5
B4
B3
2nd
X
X
X
X
X
X
X
X
X
X
B2
B1
B0
A4
A3
A2
A1
A0
1st
X
X
X
X
X
X
X
X
X
X
X
X
C5
C4
C3
C2
C1
C0
2nd
X
X
X
X
X
X
X
X
X
X
X
X
B5
B4
B3
B2
B1
B0
3rd
X
X
X
X
X
X
X
X
X
X
X
X
A5
A4
A3
A2
A1
A0
X
X
C4
C3
C2
C1
C0
B5
B4
B3
B2
B1
B0
A4
A3
A2
A1
A0
1st
X
X
X
X
X
X
X
X
X
X
X
X
C5
C4
C3
C2
C1
C0
2nd
X
X
X
X
B5
B4
B3
B2
B1
B0
X
X
A5
A4
A3
A2
A1
A0
1st
X
X
X
X
C15
C14
C13
C12
C11
C10
X
X
B15
B14
B13
B12
B11
B10
2nd
X
X
X
X
A15
A14
A13
A12
A11
A10
X
X
C25
C24
C23
C22
C21
C20
3rd
SSD1351
Data bus
D9
D8
D17
Bus width Color De pth Input orde r
X
X
X
X
B25
B24
B23
B22
B21
B20
X
X
A25
A24
A23
A22
A21
A20
C5
C4
C3
C2
C1
C0
B5
B4
B3
B2
B1
B0
A5
A4
A3
A2
A1
A0
Rev 1.5
P 23/57
Jan 2011
Solomon Systech
8.4 Command Decoder
This module determines whether the input should be interpreted as data or command based upon the input of
the D/C# pin.
If D/C# pin is HIGH, data is written to Graphic Display Data RAM (GDDRAM). If it is LOW, the inputs at
D0-D17 are interpreted as a Command and it will be decoded and be written to the corresponding command
register.
8.5
8.5.1
Oscillator & Timing Generator
Oscillator
Figure 8-7 : Oscillator Circuit
Internal
Oscillator
Fosc
M
U
X
CL
CLK
DCLK
Divider
Display
Clock
CLS
This module is an On-Chip low power RC oscillator circuitry (Figure 8-7). The operation clock (CLK) can be
generated either from internal oscillator or external source CL pin by CLS pin. If CLS pin is HIGH, internal
oscillator is selected. If CLS pin is LOW, external clock from CL pin will be used for CLK. The frequency of
internal oscillator FOSC can be programmed by command B3h.
The display clock (DCLK) for the Display Timing Generator is derived from CLK. The division factor “D”
can be programmed from 1 to 16 by command B3h.
DCLK = FOSC / D
The frame frequency of display is determined by the following formula:
FFRM =
Fosc
D × K × No. of Mux
where
• D stands for clock divide ratio. It is set by command B3h A[3:0]. The divide ratio has the range from 1 to
1024 .
• K is the number of display clocks per row. The value is derived by
K = Phase 1 period +Phase 2 period + X
X = DCLKs in current drive period. Default X = 134
Default K is 5 + 8 + 134 = 147
• Number of multiplex ratio is set by command CAh. The reset value is 127 (i.e. 128MUX).
• Fosc is the oscillator frequency. It can be changed by command B3h A[7:4]. The higher the register setting
results in higher frequency.
If the frame frequency is set too low, flickering may occur. On the other hand, higher frame frequency leads
to higher power consumption on the whole system.
Solomon Systech
Jan 2011
P 24/57
Rev 1.5
SSD1351
8.6
SEG/COM Driving block
This block is used to derive the incoming power sources into the different levels of internal use voltage and
current.
• VCC is the most positive voltage supply.
• VCOMH is the Common deselected level. It is internally regulated.
• VLSS is the ground path of the analog and panel current.
• IREF is a reference current for segment current drivers ISEG. The relationship between reference
current and segment current of a color is:
ISEG = Contrast / 256 * IREF * scale factor
in which
the contrast is set by Set Contrast command (C1h); and
the scale factor (1 ~ 16) is set by Master Current Control command (C7h).
A resistor should be connected between IREF pin and VSS pin.
For example, in order to achieve ISEG = 200uA at maximum contrast 255, IREF is set to around 12.5uA.
This current value is obtained by connecting an appropriate resistor from IREF pin to VSS as shown in
Figure 8-8.
Figure 8-8 : IREF Current Setting by Resistor Value
SSD1351
IREF ≈ 12.5uA
IREF (voltage at this
pin = VCC – 6V)
R1
VSS
Since the voltage at IREF pin is VCC – 6V, the value of resistor R1 can be found as below:
For IREF = 12.5uA, VCC =16V:
R1 = (Voltage at IREF – VSS) / IREF
≈ (16 – 6) / 12.5uA
≈ 800KΩ
SSD1351
Rev 1.5
P 25/57
Jan 2011
Solomon Systech
8.7
SEG / COM Driver
Segment drivers consist of 384 (128 x 3 colors) current sources to drive OLED panel. The driving current can
be adjusted from 0 to 200uA with 256 steps by contrast setting command (C1h). Common drivers generate
scanning voltage pulse. The block diagrams and waveforms of the segment and common driver are shown as
follow.
Figure 8-9 : Segment and Common Driver Block Diagram
VCC
ISEG
VCOMH
Current
Drive
Non-select
Row
Reset
OLED
Pixel
Selected
Row
VLSS
VLSS
Segment Driver
Common Driver
The commons are scanned sequentially, row by row. If a row is not selected, all the pixels on the row are in
reverse bias by driving those commons to voltage VCOMH as shown in Figure 8-10.
In the scanned row, the pixels on the row will be turned ON or OFF by sending the corresponding data signal
to the segment pins. If the pixel is turned OFF, the segment current is disabled and the Reset switch is
enabled. On the other hand, the segment drives to ISEG when the pixel is turned ON.
Solomon Systech
Jan 2011
P 26/57
Rev 1.5
SSD1351
Figure 8-10 : Segment and Common Driver Signal Waveform
One Frame Period
COM 0
De -select Row
V COMH
V LSS
Selected Row
C OM 1
V COMH
V LSS
COM
Voltage
This row is selected to
turn on
V COMH
V LSS
Time
Segment
Voltage
Waveform for ON
VP
Waveform for OFF
V LSS
Time
There are four phases to driving an OLED a pixel. In phase 1, the pixel is reset by the segment driver to VLSS
in order to discharge the previous data charge stored in the parasitic capacitance along the segment electrode.
The period of phase 1 can be programmed by command B1h A[3:0]. An OLED panel with larger capacitance
requires a longer period for discharging.
SSD1351
Rev 1.5
P 27/57
Jan 2011
Solomon Systech
In phase 2, first pre-charge is performed. The pixel is driven to attain the corresponding voltage level VP from
VLSS. The amplitude of VP can be programmed by the command BBh. The period of phase 2 can be
programmed by command B1h A[7:4]. If the capacitance value of the pixel of OLED panel is larger, a longer
period is required to charge up the capacitor to reach the desired voltage.
In phase 3, the OLED pixel is driven to the targeted driving voltage through second pre-charge. The second
pre-charge can control the speed of the charging process. The period of phase 3 can be programmed by
command B6h.
Last phase (phase 4) is current drive stage. The current source in the segment driver delivers constant current
to the pixel. The driver IC employs PWM (Pulse Width Modulation) method to control the gray scale of each
pixel individually. The gray scale can be programmed into different Gamma settings by command B8h/B9h.
The bigger gamma setting in the current drive stage results in brighter pixels and vice versa (Details refer to
Section 8.8). This is shown in the following figure.
Figure 8-11: Gray Scale Control in Segment
Phase2
Phase1
Segment
Voltage
Phase4
Phase3
VP
VLSS
Time
Wider pulse width
drives pixel brighter
OLED
Panel
After finishing phase 4, the driver IC will go back to phase 1 to display the next row image data. This four-step cycle is
run continuously to refresh image display on OLED panel.
The length of phase 4 is defined by command B8h “Look Up Table for Gray Scale Pulse width” or B9h “Use Built-in
Linear LUT”. In the table, the gray scale is defined in incremental way, with reference to the length of previous table
entry.
Solomon Systech
Jan 2011
P 28/57
Rev 1.5
SSD1351
8.8
Gray Scale Decoder
The gray scale effect is generated by controlling the segment current in current drive phase. The segment
current is controlled by the Gamma Settings (Setting 0~ Setting 180) through command B8h. The larger the
setting, the brighter the pixel will be. The Gray Scale Table stores the corresponding Gamma Setting of the 64
gray scale levels (GS0~GS63) through the software commands B8h or B9h. Three programmable Gray Scale
Tables (Gamma Look Up table) support the three colors A, B and C.
As shown in Figure 8-12, color A, B, C sub-pixel RAM data has 6 bits, represent the 64 gray scale level from
GS0 to GS63.
Figure 8-12 : Relation between GDDRAM content and Gray Scale table entry for three colors in 262K color mode (under
command B9h Use Built-in Linear LUT)
Color A, B or C
GDDRAM data (6 bits)
000000
000001
000010
000011
000100
:
111101
111110
111111
Gray Scale Table
GS0
GS1
GS2
GS3
GS4
:
GS61
GS62
GS63
Default Gamma Setting
(Command B9h Linear Gamma Look Up Table)
Setting 0
Setting 0
Setting 2
Setting 4
Setting 6
:
Setting 120
Setting 122
Setting 124
In command B8h, there are total 180 Gamma Settings (Setting 0 to Setting 180) available for the Gray Scale
table. GS0 has no pre-charge and current drive stages so it is in Gamma Setting 0. GS1 can be set as only precharge but no current drive stage by input Gamma Setting 0.
When setting the Gray Scale Table (by B8h command) , the rules below must follow:
1) All Gamma Settings (i.e. GS1, GS2, GS3,.....GS63) are entered after command B8h.
2) The gray scale is defined in incremental way, with reference to the length of previous table entry:
Setting of GS1 has to be >= 0
Setting of GS2 has to be > Setting of GS1 +1
Setting of GS3 has to be > Setting of GS2 +1
:
Setting of GS63 has to be > Setting of GS62 +1
SSD1351
Rev 1.5
P 29/57
Jan 2011
Solomon Systech
8.9
Power ON and OFF sequence
The following figures illustrate the recommended power ON and power OFF sequence of SSD1351 (assume
VCI and VDDIO are at the same voltage level).
Power ON sequence:
1. Power ON VCI, VDDIO.
2. After VCI, VDDIO become stable, set wait time at least 1ms (t0) for internal VDD become stable. Then set
RES# pin LOW (logic low) for at least 2us (t1) (4) and then HIGH (logic high).
3. After set RES# pin LOW (logic low), wait for at least 2us (t2). Then Power ON VCC.(1)
4. After VCC become stable, send command AFh for display ON. SEG/COM will be ON after 200ms (tAF).
5. After VCI become stable, wait for at least 300ms to send command.
Figure 8-13 : The Power ON sequence.
ON VCI, VDDIO
VCI,, VDDIO
RES#
ON VCC
Send AFh command for Display ON
t0
OFF
t1
RES#
GND
t2
VCC
OFF
tAF
ON
SEG/COM
OFF
Power OFF sequence:
1. Send command AEh for display OFF.
2. Power OFF VCC.(1), (2)
3. Wait for tOFF. Power OFF VCI, VDDIO. (where Minimum tOFF=0ms (3), Typical tOFF=100ms)
Figure 8-14 : The Power OFF sequence
Send command AEh for display OFF
VCC
OFF VCC
OFF VCI ,VDDIO
OFF
VCI, VDDIO
tOFF
OFF
Note:
(1)
Since an ESD protection circuit is connected between VCI, VDDIO and VCC, VCC becomes lower than VCI whenever VCI,
VDDIO is ON and VCC is OFF as shown in the dotted line of VCC in Figure 8-13 and Figure 8-14.
(2)
VCC should be kept float (disable) when it is OFF.
(3)
VCI, VDDIO should not be Power OFF before VCC Power OFF.
(4)
The register values are reset after t1.
(5)
Power pins (VCI, VDDIO and VCC) can never be pulled to ground under any circumstance.
Solomon Systech
Jan 2011
P 30/57
Rev 1.5
SSD1351
8.10 VDD Regulator
In SSD1351, the power supply pin for core logic operation: VDD, is internally regulated through the VDD
regulator. The following figure shows the VDD regulator pin connection scheme:
Figure 8-15 VDD pin connection scheme
VDD Regulator Enable
Command: ABh A[0]=1b.
VCI
VCI
VDDIO
VSS
VDDIO
VDD
GND
8.10.1 VDD Regulator in Sleep Mode
Power can be saved by disable the internal VDD regulator during Sleep mode. The following figures show the
corresponding command sequence:
Figure 8-16 : Case 1 - Command sequence for just entering/ exiting sleep mode
Command for entering sleep mode :
AEh (Sleep In)
Sleep mode
Command for exiting sleep mode :
AFh (Sleep Out)
Figure 8-17 : Case 2 - Command sequence for disabling internal VDD regulator during sleep mode
Command for entering sleep mode :
AEh (Sleep In)
Command for disable internal VDD regulator:
ABh, bit A[0] is set to 0b
Sleep mode
Command for enable internal VDD regulator (1):
ABh, bit A[0] is set to 1b
Wait at least 1ms for VDD becomes stable
Command for exiting sleep mode :
AFh (Sleep Out)
In the above two cases, the RAM content can also be kept during the sleep mode.
Note:
(1)
It should be noted that the internal VDD regulator should be enabled before exiting sleep mode (issuing command AFh).
(2)
No RAM access through MCU interface when there is no internal VDD.
SSD1351
Rev 1.5
P 31/57
Jan 2011
Solomon Systech
9
COMMAND
9.1
Basic Command List
Table 9-1 : Command table
(D/C# = 0, R/W#(WR#)= 0, E(RD#) = 1) unless specific setting is stated
Single byte command (D/C# = 0), Multiple byte command (D/C# = 0 for first byte, D/C# = 1 for other bytes)
Fundamental Command Table
D/C# Hex D7 D6
0
15
0 0
1
A[6:0] * A6
1
B[6:0] * B6
D5
0
A5
B5
D4
1
A4
B4
D3
0
A3
B3
D2
1
A2
B2
D2
0
A1
B1
D0
1
A0
B0
Command
Set Column
Address
A[6:0]: Start Address. [reset=0]
B[6:0]: End Address. [reset=127]
Range from 0 to 127
Set Row
Address
A[6:0]: Start Address. [reset=0]
B[6:0]: End Address. [reset=127]
Range from 0 to 127
0
1
1
75
A[6:0]
B[6:0]
0
*
*
1 1 1 0 1 0 1
A6 A5 A4 A3 A2 A1 A0
B6 B5 B4 B3 B2 B1 B0
0
5C
0
1
0
1
1
1
0
0
Write RAM
Command
0
5D
0
1
0
1
1
1
0
1
Read RAM
Command
0
A0
1
0
1
0
0
0
0
0
1
A[7:0] A7 A6 A5 A4 A3 A2 A1 A0
Description
Enable MCU to write Data into RAM
Enable MCU to read Data from RAM
A[0]=0b, Horizontal address increment [reset]
A[0]=1b, Vertical address increment
A[1]=0b, Column address 0 is mapped to SEG0 [reset]
A[1]=1b, Column address 127 is mapped to SEG0
A[2]=0b, Color sequence: A Æ B Æ C [reset]
A[2]=1b, Color sequence is swapped: C Æ B Æ A
A[3]=0b, Reserved
A[3]=1b, Reserved
Set Re-map /
Color Depth
(Display RAM A[4]=0b, Scan from COM0 to COM[N –1] [reset]
to Panel)
A[4]=1b, Scan from COM[N-1] to COM0. Where N is the
Multiplex ratio.
A[5]=0b, Disable COM Split Odd Even
A[5]=1b, Enable COM Split Odd Even [reset]
A[7:6] Set Color Depth,
00b / 01b: 65k color [reset]
10b: 262k color
11b 262k color, 16-bit format 2
Refer to Table 8-8 for details
Solomon Systech
Jan 2011
P 32/57
Rev 1.5
SSD1351
Fundamental Command Table
D/C# Hex D7 D6 D5 D4 D3 D2 D2 D0
0
A1
1 0 1 0 0 0 0 1
1
A[6:0] * A6 A5 A4 A3 A2 A1 A0
0
A2
1
0
1
A[6:0]
*
A6 A5 A4 A3 A2 A1 A0
0
A4~A7 1
0
1
1
0
0
0
0
0
1
1
Command
Set Display
Start Line
Description
Set vertical scroll by RAM from 0~127. [reset=00h]
Set vertical scroll by Row from 0-127. [reset=60h]
0
Set Display
Offset
Note
This command is locked by Command FDh by default. To
unlock it, please refer to Command FDh.
(1)
A4h: All OFF
X1 X0
Set Display
Mode
A5h: All ON (All pixels have GS63)
A6h : Reset to normal display [reset]
A7h: Inverse Display (GS0 -> GS63, GS1 -> GS62, ....)
0
1
AB
1 0
A[7:0] A7 A6
1
0
0
0
1
0
0
0
1
0
1
A0
Function
Selection
0
0
0
0
1
AD
1
0
1
0
1
1
0
1
AE~AF 1
0
1
0
1
1
1
X0
0
1
1
0
0
0
0
B0
1
NOP
A[0]=0b, Disable internal VDD regulator (for power save
during sleep mode only)
A[0]=1b, Enable internal VDD regulator [reset]
A[7:6]=00b, Select 8-bit parallel interface [reset]
A[7:6]=01b, Select 16-bit parallel interface
A[7:6]=11b, Select 18-bit parallel interface
Command for no operation.
AEh = Sleep mode On (Display OFF)
Set Sleep mode AFh = Sleep mode OFF (Display ON)
ON/OFF
NOP
Command for no operation.
A[3:0] Phase 1 period of 5~31 DCLK(s) clocks
[reset=0010b]
A[3:0]:
0-1 invalid
2 = 5 DCLKs
3 = 7 DCLKs
:
15 = 31DCLKs
B1
1 0 1 1 0 0 0 1
A[7:0] A7 A6 A5 A4 A3 A2 A1 A0
Set Reset
(Phase 1) /
Pre-charge
(Phase 2)
period
A[7:4] Phase 2 period of 3~15 DCLK(s) clocks
[reset=1000b]
A[7:4]:
0-2 invalid
3 = 3 DCLKs
4 = 4 DCLKs
:
15 =15DCLKs
Note
(1)
0 DCLK is invalid in phase 1 & phase 2
(2)
This command is locked by Command FDh by default. To
unlock it, please refer to Command FDh.
SSD1351
Rev 1.5
P 33/57
Jan 2011
Solomon Systech
Fundamental Command Table
D/C# Hex D7 D6 D5 D4 D3 D2 D2 D0
0
B2
1 0 1 1 0 0 1 0
1
A[7:0] A7 A6 A5 A4 A3 A2 A1 A0
1
1
0
1
B[7:0] 0 0 0 0 0 0 0 0
C[7:0] 0 0 0 0 0 0 0 0
B3
1 0 1 1 0 0 1 1
A[7:0] A7 A6 A5 A4 A3 A2 A1 A0
Command
Description
A[7:0] = 00h, B[7:0] = 00h, C[7:0] = 00h normal [reset]
Display
A[7:0] = A4h, B[7:0] = 00h, C[7:0] = 00h enhance display
Enhancement
performance
A[3:0] [reset=0001], divide by DIVSET where
Front Clock
Divider
(DivSet)/
Oscillator
Frequency
A[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
>=1011
DIVSET
divide by 1
divide by 2
divide by 4
divide by 8
divide by 16
divide by 32
divide by 64
divide by 128
divide by 256
divide by 512
divide by 1024
invalid
A[7:4] Oscillator frequency, frequency increases as level
increases [reset=1101b]
Note
(1)
This command is locked by Command FDh by default. To
unlock it, please refer to Command FDh.
0
1
1
1
B4
A[7:0]
B[7:0]
C[7:0]
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
1
0
0
0
0
1
0
1
1
0 0
A1 A0
0 1
0 1
0
1
B5
A[3:0]
1
*
0
*
1
*
1
*
0 1 0 1
A3 A2 A1 A0
A[1:0]=00 External VSL [reset]
A[1:0]=01,10,11 are invalid
Set Segment
Low Voltage Note
(1)
When external VSL is enabled, in order to avoid distortion
(VSL)
in display pattern, an external circuit is needed to connect
between VSL and VSS as shown in Figure 14-1.
A[1:0] GPIO0: 00 pin HiZ, Input disabled
01 pin HiZ, Input enabled
10 pin output LOW [reset]
11 pin output HIGH
Set GPIO
0
1
B6
A[3:0]
1
0
1
1
*
*
*
*
0 1 0 0
A3 A2 A1 A0
A[3:0] Set Second Pre-charge Period
Set Second Precharge Period
Solomon Systech
A[3:2] GPIO1: 00 pin HiZ, Input disabled
01 pin HiZ, Input enabled
10 pin output LOW [reset]
11 pin output HIGH
0000b invalid
0001b 1 DCLKS
0010b 2 DCLKS
....
1000 8 DCLKS [reset]
....
1111 15 DCLKS
Jan 2011
P 34/57
Rev 1.5
SSD1351
Fundamental Command Table
D/C#
0
Hex
B8
1
A1[7:0]
1
A2[7:0]
1
.
.
.
.
.
.
.
.
.
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
D7 D6 D5 D4 D3 D2 D2 D0
1
0
1 1 1 0 0 0
A17 A16 A15 A14 A13 A12 A11 A10
A27 A26 A25 A24 A23 A22 A21 A20
1
A62[7:0] A627 A626 A625 A624 A623 A622 A621 A620
1
A63[7:0] A637 A636 A635 A634 A633 A632 A631 A630
Command
Description
The next 63 data bytes define Gray Scale (GS) Table by
setting the gray scale pulse width in unit of DCLK’s
(ranges from 0d ~ 180d)
A1[7:0]: Gamma Setting for GS1,
A2[7:0]: Gamma Setting for GS2,
:
A62[7:0]: Gamma Setting for GS62,
Look Up Table A63[7:0]: Gamma Setting for GS63
for Gray Scale
Pulse width
Note
0 ≤ Setting of GS1 < Setting of GS2 < Setting of GS3.....
< Setting of GS62 < Setting of GS63
(2)
GS0 has only pre-charge but no current drive stages.
(3)
GS1 can be set as only pre-charge but no current drive
stage by input gamma setting for GS1 equals 0.
(1]
0
B9
1
0
1
1
1
0
0
1
0
1
BB
A[4:0]
1
0
0
0
1
0
1 1 0 1 1
A4 A3 A2 A1 A0
Reset to default Look Up Table:
GS1 = 0 DCLK
GS2 = 2 DCLK
GS3 = 4 DCLK
Use Built-in
GS4 = 6 DCLK
Linear LUT
...
[reset= linear] GS62 = 122 DCLK
GS63 = 124 DCLK
Set pre-charge voltage level.[reset = 17h]
Set Pre-charge
voltage
A[4:0]
00000
:
11111
Hex code
00h
:
1Fh
pre-charge voltage
0.20 x VCC
:
0.60 x VCC
Note
(1)
This command is locked by Command FDh by default. To
unlock it, please refer to Command FDh.
0
BE
1
0
1
1
1
1
1
1
A[2:0]
0
0
0
0
0
A2 A1 A0
Set COM deselect voltage level [reset = 05h]
0
Set VCOMH
Voltage
A[2:0]
000
:
101
:
111
Hex code
00h
:
05h
:
07h
V COMH
0.72 x VCC
:
0.82 x VCC [reset]
:
0.86 x VCC
Note
(1)
This command is locked by Command FDh by default. To
unlock it, please refer to Command FDh.
SSD1351
Rev 1.5
P 35/57
Jan 2011
Solomon Systech
Fundamental Command Table
D/C# Hex D7
0
C1
1
1
A[7:0] A7
1
B[7:0] B7
1
C[7:0] C7
D6
1
A6
B6
C6
D5
0
A5
B5
C5
D4
0
A4
B4
C4
D3
0
A3
B3
C3
D2
0
A2
B2
C2
D2
0
A1
B1
C1
1
1
D0
1
A0
B0
C0
Command
Description
A[7:0] Contrast Value Color A [reset=10001010b]
Set Contrast B[7:0] Contrast Value Color B [reset=01010001b]
Current for C[7:0] Contrast Value Color C [reset=10001010b]
Color A,B,C
A[3:0] :
0000b reduce output currents for all colors to 1/16
A0
0001b reduce output currents for all colors to 2/16
Master Contrast
....
Current Control
1110b reduce output currents for all colors to 15/16
1111b no change [reset]
0
C7
1
1
0
0
0
1
A[3:0]
*
*
*
*
A3 A2 A1
0
1
CA
A[6:0]
1
0
A[6:0] MUX ratio 16MUX ~ 128MUX, [reset=127],
1 0 0 1 0 1 0
A6 A5 A4 A3 A2 A1 A0 Set MUX Ratio (Range from 15 to 127)
0
D1
1
0
1
0
1
1
0
1
NOP
0
E3
1
1
1
0
0
0
1
1
NOP
0
1
1
FD
1 1 1 1 1 1 0 1
A[7:0] A7 A6 A5 A4 A3 A2 A1 A0
Command for No Operation
Command for No Operation
A[7:0]: MCU protection status [reset = 12h]
A[7:0] = 12b, Unlock OLED driver IC MCU interface from
entering command [reset]
A[7:0] = 16b, Lock OLED driver IC MCU interface from
entering command
A[7:0] = B0b, Command A2,B1,B3,BB,BE,C1 inaccessible
Set Command
in both lock and unlock state [reset]
Lock
A[7:0] = B1b, Command A2,B1,B3,BB,BE,C1 accessible if
in unlock state
Note
The locked OLED driver IC MCU interface prohibits all
commands and memory access except the FDh command.
(1)
Note
(1)
“*” stands for “Don’t care”.
Solomon Systech
Jan 2011
P 36/57
Rev 1.5
SSD1351
Table 9-2: SSD1351 Graphic Acceleration Command List
Set (GAC) (D/C# = 0, R/W#(WR#)= 0, E(RD#) = 1) unless specific setting is stated
Single byte command (D/C# = 0), Multiple byte command (D/C# = 0 for first byte, D/C# = 1 for other bytes)
Graphic acceleration command
D/C# Hex D7 D6 D5 D4 D3 D2 D2 D0
0
96
1 0 0 1 0 1 1 0
1
1
1
1
1
A[7:0]
B[6:0]
C[7:0]
D[6:0]
E[1:0]
A7
0
C7
0
0
A6
B6
C6
D6
0
A5
B5
C5
D5
0
A4
B4
C4
D4
0
A3
B3
C3
D3
0
A2
B2
C2
D2
0
A1
B1
C1
D1
E1
Command
A0
B0
C0
D0
E0
Description
A[7:0] = 00000000b No scrolling
A[7:0] = 00000001b to 00111111b
Scroll towards SEG127 with 1 column offset
A[7:0] = 01000000b to 11111111b
Scroll towards SEG0 with 1 column offset
B[6:0] : start row address
Horizontal Scroll
C[7:0] : number of rows to be H-scrolled
B+C <= 128
D[6:0] : Reserved (reset=00h)
E[1:0] : scrolling time interval
00b test mode
01b normal
10b slow
11b slowest
Note
(1)
Operates during display ON.
0
9E
1
0
0
1
1
1
1
0
Stop horizontal scroll
Stop Moving
0
9F
1
0
0
1
1
1
1
1
Start Moving
Note
(1)
After sending 9Eh command to stop the scrolling
action, the ram data needs to be rewritten
Start horizontal scroll
Note
(1)
After executed the graphic command, waiting time is required for update GDDRAM content.
VCI =2.4~3.5V, waiting time = 500ns/pixel.
(2)
“*” stands for “Don’t care”.
SSD1351
Rev 1.5
P 37/57
Jan 2011
Solomon Systech
10 COMMAND
10.1.1 Set Column Address (15h)
This triple byte command specifies column start address and end address of the display data RAM. This
command also sets the column address pointer to column start address. This pointer is used to define the
current read/write column address in graphic display data RAM. If horizontal address increment mode is
enabled by command A0h, after finishing read/write one column data, it is incremented automatically to the
next column address. Whenever the column address pointer finishes accessing the end column address, it is
reset back to start column address and the row address is incremented to the next row.
10.1.2 Set Row Address (75h)
This triple byte command specifies row start address and end address of the display data RAM. This
command also sets the row address pointer to row start address. This pointer is used to define the current
read/write row address in graphic display data RAM. If vertical address increment mode is enabled by
command A0h, after finishing read/write one row data, it is incremented automatically to the next row address.
Whenever the row address pointer finishes accessing the end row address, it is reset back to start row address.
For example, column start address is set to 2 and column end address is set to 125, row start address is set to 1 and row
end address is set to 126. Horizontal address increment mode is enabled by command A0h. In this case, the graphic
display data RAM column accessible range is from column 2 to column 125 and from row 1 to row 126 only. In
addition, the column address pointer is set to 2 and row address pointer is set to 1. After finishing read/write one pixel of
data, the column address is increased automatically by 1 to access the next RAM location for next read/write
operation(solid line in Figure 10-1). Whenever the column address pointer finishes accessing the end column 125, it is
reset back to column 2 and row address is automatically increased by 1(solid line in Figure 10-1). While the end row
126 and end column 125 RAM location is accessed, the row address is reset back to 1 and the column address is reset
back to 2(dotted line in Figure 10-1).
Figure 10-1 : Example of Column and Row Address Pointer Movement
Col 0
Col 1
Col 2
…..
…….
Col125
Col126
Col127
Row 0
Row 1
Row 2
:
:
:
:
:
:
Row 125
Row 126
Row 127
Solomon Systech
Jan 2011
P 38/57
Rev 1.5
SSD1351
10.1.3 Write RAM Command (5Ch)
After entering this single byte command, data entries will be written into the display RAM until another
command is written. Address pointer is increased accordingly. This command must be sent before write data
into RAM.
10.1.4 Read RAM Command (5Dh)
After entering this single byte command, data is read from display RAM until another command is written.
Address pointer is increased accordingly. This command must be sent before read data from RAM.
10.1.5 Set Re-map & Dual COM Line Mode (A0h)
This command has multiple configurations and each bit setting is described as follows:
•
Address increment mode (A[0])
When A[0] is set to 0, the driver is set as horizontal address increment mode. After the display RAM
is read / written, the column address pointer is increased automatically by 1. If the column address
pointer reaches column end address, the column address pointer is reset to column start address and
row address pointer is increased by 1. The sequence of movement of the row and column address
point for horizontal address increment mode is shown in Figure 10-2.
Figure 10-2 : Address Pointer Movement of Horizontal Address Increment Mode
Row 0
Row 1
:
Row 126
Row 127
Col 0
Col 1
…..
Col 126
Col 127
:
:
:
:
:
When A[0] is set to 1, the driver is set to vertical address increment mode. After the display RAM is
read / written, the row address pointer is increased automatically by 1. If the row address pointer
reaches the row end address, the row address pointer is reset to row start address and column address
pointer is increased by 1. The sequence of movement of the row and column address point for
vertical address increment mode is shown in Figure 10-3.
Figure 10-3: Address Pointer Movement of Vertical Address Increment Mode
Col 0
Row 0
Row 1
:
Row 126
Row 127
•
Col 1
…..
…..
…..
:
…..
…..
Col 126
Col 127
Column Address Remap (A[1])
This command bit is made for increasing the layout flexibility of segment signals in OLED module
with segment arranged from left to right (when A[1] is set to 0) or vice versa (when A[1] is set to 1),
as demonstrated in Figure 10-4.
A[1] = 0 (reset): RAM Column 0 ~ 127 maps to Col0~Col127
A[1] = 1: RAM Column 0 ~ 127 maps to Col127~Col0
SSD1351
Rev 1.5
P 39/57
Jan 2011
Solomon Systech
•
Color Remap (A[2])
A[2] = 0 (reset): color sequence A Æ B Æ C
A[2] = 1: color sequence C Æ B Æ A
•
COM scan direction Remap (A[4])
This command bit determines the scanning direction of the common for flexible layout of common
signals in OLED module either from up to down or vice versa.
A[1] = 0 (reset): Scan from up to down
A[1] = 1: Scan from bottom to up
Details of pin arrangement can be found in Figure 10-4.
•
Odd even split of COM pins (A[5])
This command bit can set the odd even arrangement of COM pins.
A[5] = 0 (reset): Disable COM split odd even, pin assignment of common is in sequential as
COM127 COM126...COM 65 COM64...SEG479...SEG0...COM0 COM1...COM62 COM63
A[5] = 1: Enable COM split odd even, pin assignment of common is in odd even split as
COM127 COM125...COM3 COM1...SEG479...SEG0...COM0 COM2...COM124 COM126
Details of pin arrangement can be found in Figure 10-4.
Figure 10-4 : COM Pins Hardware Configuration (MUX ratio: 128)
A[0] =0
A[1]=0
Disable Odd Even Split of
Disable COM Left / Right
COM pins
Remap
A[7]=0
COM Scan Direction :
from COM0 to COM127
ROW127
128 x 128
ROW64
ROW63
ROW0
COM64
SSD1351Z
COM127
COM0
COM63
Pad 1,2,3,…Gold Bumps face up
A[0] =1
Enable Odd Even Split of
COM pins
A[1]=0
A[7]=0
Disable COM Left / Right COM Scan Direction : from
Remap
COM0 to COM127
ROW126
ROW127
ROW125
128 x 128
ROW2
ROW1
ROW0
SSD1351Z
COM64
COM126
COM127
COM0
COM1
COM63
Pad 1,2,3,… Gold Bumps face up
Solomon Systech
Jan 2011
P 40/57
Rev 1.5
SSD1351
•
Display color mode (A[7:6])
Select either 262k, 65k or 256 color mode.
10.1.6 Set Display Start Line (A1h)
This command is used to set Display Start Line register to determine starting address of display RAM to be
displayed by selecting a value from 0 to 127. Figure 10-5 shows an example of using this command when
MUX ratio = 128 and MUX ratio = 100 and Display Start Line = 28. In there, “Row” means the graphic
display data RAM row.
Figure 10-5 : Example of Set Display Start Line with no Remap
COM Pin
COM0
COM1
COM2
COM3
COM4
COM5
COM6
:
:
:
:
COM95
COM96
COM97
COM98
COM99
COM100
COM101
COM102
COM103
COM104
COM105
COM106
COM107
COM108
COM109
COM110
COM111
COM112
COM113
COM114
COM115
COM116
COM117
COM118
COM119
COM120
COM121
COM122
COM123
COM124
COM125
COM126
COM127
Display
example
128
0
Row0
Row1
Row2
Row3
Row4
Row5
Row6
:
:
:
:
Row95
Row96
Row97
Row98
Row99
Row100
Row101
Row102
Row103
Row104
Row105
Row106
Row107
Row108
Row109
Row110
Row111
Row112
Row113
Row114
Row115
Row116
Row117
Row118
Row119
Row120
Row121
Row122
Row123
Row124
Row125
Row126
Row127
128
28
Row28
Row29
Row30
Row31
Row32
Row33
Row34
:
:
:
:
Row123
Row124
Row125
Row126
Row127
Row0
Row1
Row2
Row3
Row4
Row5
Row6
Row7
Row8
Row9
Row10
Row11
Row12
Row13
Row14
Row15
Row16
Row17
Row18
Row19
Row20
Row21
Row22
Row23
Row24
Row25
Row26
Row27
(b)
(a)
SSD1351
Rev 1.5
100
0
Row0
Row1
Row2
Row3
Row4
Row5
Row6
:
:
:
:
Row95
Row96
Row97
Row98
Row99
-
P 41/57
Jan 2011
100
28
Row28
Row29
Row30
Row31
Row32
Row33
Row34
:
:
:
:
Row124
Row125
Row126
Row127
Row0
-
(c)
MUX ratio (CAh)
Display start line (A1h)
(d)
(GDDARAM)
Solomon Systech
10.1.7 Set Display Offset (A2h)
This command specifies the mapping of display start line (it is assumed that COM0 is the display start line, display start
line register equals to 0) to one of COM0-127. For example, to move the COM16 towards the COM0 direction for 16
lines, A[7:0] should be given by 00010000. The figure below shows an example of this command. In there, “Row”
means the graphic display data RAM row.
Figure 10-6 : Example of Set Display Offset with no Remap
COM0
COM1
COM2
a
128
0
Row0
Row1
Row2
b
96
0
Row0
Row1
Row2
c
96
32
Row32
Row33
Row34
:
:
:
:
COM61
COM62
COM63
COM64
COM65
COM66
:
COM93
COM94
COM95
COM96
COM97
COM98
:
COM125
COM126
COM127
Display
example
Row61
Row62
Row63
Row64
Row65
Row66
:
Row93
Row94
Row95
Row96
Row97
Row98
:
Row125
Row126
Row127
(a)
Solomon Systech
Row61
Row62
Row63
Row64
Row65
Row66
:
Row93
Row94
Row95
:
-
Case
MUX ratio (CAh)
Display offset (A2h A[7:0])
Row93
Row94
Row95
:
Row0
Row1
Row2
:
Row29
Row30
Row31
(c)
(d)
(GDDARAM)
Jan 2011
P 42/57
Rev 1.5
SSD1351
10.1.8 Set Display Mode (A4h ~ A7h)
These are single byte command and they are used to set Normal Display, Entire Display ON, Entire Display
OFF and Inverse Display.
• All OFF (A4h)
Force the entire display to be at gray scale level “GS0” regardless of the contents of the display data
RAM as shown in Figure.
Figure 10-7 : Example of Entire Display OFF
GDDRAM
•
Display
Set Entire Display ON (A5h)
Force the entire display to be at gray scale “GS63” regardless of the contents of the display data RAM
as shown in Figure 10-8.
Figure 10-8 : Example of Entire Display ON
GDDRAM
•
Display
Set Entire Display OFF (A6h)
Reset the above effect and turn the data to ON at the corresponding gray level. Figure 10-9 shows an
example of Normal Display.
Figure 10-9 : Example of Normal Display
GDDRAM
•
Display
Inverse Display (A7h)
The gray level of display data are swapped such that “GS0” ↔ “GS63”, “GS1” ↔ “GS62”, …
Figure 10-10 shows an example of inverse display.
Figure 10-10 : Example of Inverse Display
GDDRAM
SSD1351
Rev 1.5
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Jan 2011
Display
Solomon Systech
10.1.9 Set Function selection (ABh)
This double byte command is used to select MCU bus interface and to enable or disable the VDD regulator.
• MCU bus interface selection (A[7:6])
Select appropriate logic setting as described in the following table; for which BS3 and BS2 are command
programmable, and BS1 and BS0 are pin selected (refer to Section 7).
Table 10-11: Bus interface selection
BS[3:2]
00
01
11
Interface
SPI, 8-bit parallel [reset]
16-bit parallel
18-bit parallel
• Set VDD regulator (A[0])
This bit is used to enable or disable the VDD regulator.
A[0] = 0: Disable the internal VDD regulator (for power save during sleep mode only)
A[0] = 1 (reset): Enable the internal VDD regulator
10.1.10 Set Sleep mode ON/OFF (AEh / AFh)
These single byte commands are used to turn the OLED panel display ON or OFF.
When the display is OFF (command AEh), the segment is in VSS state and common is in high impedance state.
10.1.11 Set Phase Length (B1h)
This double byte command sets the length of phase 1 and 2 of segment waveform of the driver.
• Phase 1 (A[3:0]): Set the period from 5 to 31 in the unit of 2 DCLKs. A larger capacitance of the
OLED pixel may require longer period to discharge the previous data charge completely.
• Phase 2 (A[7:4]): Set the period from 3 to 15 in the unit of DCLKs. A longer period is needed to
charge up a larger capacitance of the OLED pixel to the target voltage VP.
10.1.12 Display Enhancement (B2h)
This four byte command enhancement display performance.
10.1.13 Set Front Clock Divider / Oscillator Frequency (B3h)
This double byte command consists of two functions:
• Front Clock Divide Ratio (A[3:0])
Set the divide ratio to generate DCLK (Display Clock) from CLK. The divide ratio is from 1 to 16,
with reset value = 1. Please refer to Section 8.5 for the detail relationship of DCLK and CLK.
•
Oscillator Frequency (A[7:4])
Program the oscillator frequency Fosc which is the source of CLK if CLS pin is pulled HIGH. The 4bit value results in 16 different frequency settings being available.
10.1.14 Set GPIO (B5h)
This double byte command is used to set the states of GPIO0 and GPIO1 pins. Refer to Table 9-1 for details.
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Jan 2011
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SSD1351
10.1.15 Set Second Pre-charge period (B6h)
This double byte command is used to set the phase 3 second pre-charge period. The period of phase 3 can be
programmed by command B6h and it is ranged from 1 to 15 DCLK's. Please refer to Table 9-1 for the detail
information.
10.1.16 Look Up Table for Gray Scale Pulse width (B8h)
This command is used to set each individual gray scale level for the display. Except gray scale levels GS0
that has no pre-charge and current drive, each gray scale level is programmed in the length of current drive
stage pulse width with unit of DCLK. The longer the length of the pulse width, the brighter the OLED pixel
when it’s turned ON. Following the command B8h, the user has to set the gray scale setting for GS1, GS2, …,
GS62, GS63 one by one in sequence. GS1 can be set as gamma setting 0, which means there is only precharge phase but no current drive phase. Refer to Section 8.8 for details.
The setting of gray scale table entry can perform gamma correction on OLED panel display. Since the
perception of the brightness scale shall match the image data value in display data RAM, appropriate gray
scale table setting like the example shown below (Figure 10-) can compensate this effect.
Figure 10-12 : Example of Gamma correction by Gamma Look Up table setting
Brightness
Gamma
Setting
Gamma Look Up
table setting
Brightness
Panel
response
Gray Scale Table
Gamma Setting
Result in linear
response
Gray Scale Table
10.1.17 Use Built-in Linear LUT (B9h)
This single byte command reloads the preset linear Gray Scale table as GS0 =Gamma Setting 0, GS1 =
Gamma Setting 0, GS2 = Gamma Setting 2, GS3 = Gamma Setting 4,... GS62 = Gamma Setting 122, GS63 =
Gamma Setting 124. Refer to Section 8.8 for details.
10.1.18 Set Pre-charge voltage (BBh)
This double byte command sets the first pre-charge voltage (phase 2) level of segment pins. The level of precharge voltage is programmed with reference to VCC. Refer to Table 9-1 for details.
10.1.19 Set VCOMH Voltage (BEh)
This double byte command sets the high voltage level of common pins, VCOMH. The level of VCOMH is
programmed with reference to VCC. Refer to Table 9-1 for details.
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Jan 2011
Solomon Systech
10.1.20 Set Contrast Current for Color A,B,C (C1h)
This command is used to set Contrast Setting of the display. The chip has 256 contrast steps from 00h to FFh.
The segment output current ISEG increases linearly with the contrast step, which results in brighter display.
10.1.21 Master Contrast Current Control (C7h)
This double byte command is to control the segment output current by a scaling factor. The chip has 16
master control steps, with the factor ranges from 1 [0000b] to 16 [1111b – default]. The smaller the master
current value, the dimmer the OLED panel display is set.
For example, if original segment output current is 160uA at scale factor = 16, setting scale factor to 8 would
reduce the current to 80uA.
10.1.22 Set Multiplex Ratio (CAh)
This double byte command switches default 1:128 multiplex mode to any multiplex mode from 16 to 128.
For example, when multiplex ratio is set to 16, only 16 common pins are enabled. The starting and the ending
of the enabled common pins are depended on the setting of “Display Offset” register programmed by
command A2h. Figure 10-5 and Figure 10-6 show examples of setting the multiplex ratio through command
CAh.
10.1.23 Set Command Lock (FDh)
This command is used to lock the OLED driver IC from accepting any command except itself. After entering
FDh 16h (A[2]=1b), the OLED driver IC will not respond to any newly-entered command (except FDh 12h
A[2]=0b) and there will be no memory access. This is call “Lock” state. That means the OLED driver IC
ignore all the commands (except FDh 12h A[2]=0b) during the “Lock” state.
Entering FDh 12h (A[2]=0b) can unlock the OLED driver IC. That means the driver IC resume from the
“Lock” state. And the driver IC will then respond to the command and memory access.
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Jan 2011
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Rev 1.5
SSD1351
11 MAXIMUM RATINGS
Table 11-1 : Maximum Ratings
(Voltage Reference to VSS)
Symbol
VCC
VDDIO
VCI
VSEG
VCOM
Vin
TA
Tstg
Parameter
Supply Voltage
SEG output voltage
COM output voltage
Input voltage
Operating Temperature
Storage Temperature Range
Value
-0.5 to 19.0
-0.5 to VCI
-0.3 to 4.0
0 to VCC
0 to 0.9*VCC
Vss-0.3 to VDDIO+0.3
-40 to +85
-65 to +150
Unit
V
V
V
V
V
V
ºC
ºC
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the
Electrical Characteristics tables or Pin Description.
*This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device
is not radiation protected.
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Rev 1.5
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Jan 2011
Solomon Systech
12 DC CHARACTERISTICS
Conditions (Unless otherwise specified):
Voltage referenced to VSS
VCI = 2.4 to 3.5V
TA = 25°C
Table 12-1 : DC Characteristics
Symbol
VCC
VCI
VDDIO
VOH
VOL
VIH
VIL
Parameter
Operating Voltage
Low voltage power supply
Power Supply for I/O pins
High Logic Output Level
Low Logic Output Level
High Logic Input Level
Low Logic Input Level
ISLP_VDDIO VDDIO Sleep mode Current
ISLP_VCC
VCC Sleep mode Current
Test Condition
Iout =100uA
Iout =100uA
VCI = VDDIO =2.8V,
VCC =16V
Display OFF,
No panel attached
VCI = VDDIO =2.8V,
VCC =16V
Display OFF,
No panel attached
VCI = VDDIO =2.8V,
VCC =16V
Display OFF,
No panel attached
Min
10
2.4
1.65
0.9*VDDIO
0
0.8*VDDIO
0
-
Typ
16
-
Max
18
3.5
VCI
VDDIO
0.1*VDDIO
VDDIO
0.2*VDDIO
10
Unit
V
V
V
V
V
V
V
uA
-
-
10
uA
-
50
uA
-
10
uA
0.5
10
uA
-
255
280
uA
-
1.15
1.26
mA
Contrast = FFh
-
200
-
uA
Contrast = 7Fh
-
100
-
uA
n=A
-3
50
-
3
uA
%
n=B
-3
-
3
n=C
-3
-
3
n=A
-2
-
2
n=B
-2
-
2
n=C
-2
-
2
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Rev 1.5
ISLP_VCI
VCI Sleep mode Current
IDDIO
VDDIO Supply Current
Enable Internal VDD during Sleep mode
Disable Internal VDD during Sleep mode
VCI = VDDIO =, 3.5V, VCC = 16V, Display ON,
No panel attached, contrast = FF
ICI
VCI Supply Current
VCI = VDDIO =, 3.5V, VCC = 16, Display ON, No
panel attached, contrast = FF
ICC
VCC Supply Current
VCI = VDDIO =, 3.5V, VCC = 16, Display ON, No
panel attached, contrast = FF
ISEG
Segment Output Current
Setting
VCC = 16 at IREF = 12.5uA
Dev
Adj. Dev
Contrast = 3Fh
Segment (SA, SB, SC) output Dev = (ISn – IMID)/IMID
current uniformity
IMID = (IMAX + IMIN)/2
(contrast = FF)
ISn = Segment n current . e.g. For n=A,
then ISn = ISA = SA current
Adj Dev = (ISn[m]-ISn[m+1]) / (ISn [m]+
Adjacent pin output current
ISn [m+1])
uniformity (contrast = FF)
e.g. For n=A, m=3, then ISn[m]= ISA[3]
= SA[3] current
Solomon Systech
Jan 2011
%
SSD1351
13 AC CHARACTERISTICS
Conditions (Unless otherwise specified):
Voltage referenced to VSS
TA = 25°C
Table 13-1 : AC Characteristics
Symbol Parameter
Test Condition
FOSC (1) Oscillation Frequency of Display VCI = 2.8V
Min
2.5
FFRM
Timing Generator
Frame Frequency for 128 MUX
Mode
128x128 Graphic Display Mode,
Display ON, Internal Oscillator Enabled
tRES
Reset low pulse width (RES#)
-
Typ
2.8
Max Unit
3.1 MHz
FOSC * 1/(D*K*128) (2)
2000 -
-
Hz
ns
Note
(1)
FOSC stands for the frequency value of the internal oscillator and the value is measured when command B3h A[7:4] is
in default value, and B3h A[3:0] is in [0001].
(2)
D: divide ratio set by command B3h A[3:0]
K: Phase 1 period +Phase 2 period + X
X: DCLKs in current drive period
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Jan 2011
Solomon Systech
Table 13-2 : 6800-Series MCU Parallel Interface Timing Characteristics
(VDDIO- VSS =1.65V- VCI, VCI - VSS = 2.4-3.5V, TA = 25°C)
Symbol Parameter
Clock Cycle Time (read)
tCYCLE
Clock Cycle Time (write)
Min
320
300
Typ
Max
Unit
-
-
ns
tAS
Address Setup Time
24
-
-
ns
tAH
Address Hold Time
0
-
-
ns
tDSW
Write Data Setup Time
40
-
-
ns
tDHW
Write Data Hold Time
7
-
-
ns
tDHR
Read Data Hold Time
20
-
-
ns
tOH
Output Disable Time
-
-
70
ns
tACC
Access Time
-
-
140
ns
120
60
60
60
-
-
ns
PWCSH
Chip Select Low Pulse Width (read)
Chip Select Low Pulse Width (write)
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
-
-
ns
tR
Rise Time
-
-
15
ns
tF
Fall Time
-
-
15
ns
PWCSL
Figure 13-1 : 6800-series MCU parallel interface characteristics
D/C#
tAS
tAH
R/W#
E
tCYCLE
CS#
tR
tF
tDHW
tDSW
D[17:0] (1)
(WRITE)
D[17:0] (1)
(READ)
PWCSH
PWCSL
Valid Data
tACC
tDHR
Valid Data
tOH
Note
(1)
when 8 bit used: D[7:0] instead; when 16 bit used: D[15:0] instead; when 18 bit used: D[17:0] instead.
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Jan 2011
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SSD1351
Table 13-3 : 8080-Series MCU Parallel Interface Timing Characteristics
(VDDIO- VSS =1.65V- VCI, VCI - VSS = 2.4-3.5V, TA = 25°C)
Symbol
tCYCLE
tAS
tAH
tDSW
tDHW
tDHR
tOH
tACC
tPWLR
tPWLW
tPWHR
tPWHW
tR
tF
tCS
tCSH
tCSF
Parameter
Clock Cycle Time
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
Read Data Hold Time
Output Disable Time
Access Time
Read Low Time
Write Low Time
Read High Time
Write High Time
Rise Time
Fall Time
Chip select setup time
Chip select hold time to read signal
Chip select hold time
Min
300
10
0
40
7
20
150
60
60
60
0
0
20
Typ
-
Max
46
140
15
15
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 13-2 : 8080-series MCU parallel interface characteristics
Write cycle
CS#
tCSF
tCS
D/C#
tAH
tAS
tR
tF
WR#
tPWLW
tPWHW
tDSW
D[17:0]
tCYCLE
tDHW
(1)
Read cycle
CS#
tCSH
tCS
D/C#
tAS
tR
tF
RD#
tAH
tCYCLE
tPWLR
tACC
tPWHR
tDHR
D[17:0] (1)
tOH
Note
(1)
when 8 bit used: D[7:0] instead; when 16 bit used: [15:0] instead; when 18 bit used: D[17:0] instead.
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Solomon Systech
Table 13-4 : Serial Interface Timing Characteristics (4-wire SPI)
(VDDIO- VSS =1.65V- VCI, VCI - VSS = 2.4-3.5V, TA = 25°C)
Symbol
tcycle
tAS
tAH
tCSS
tCSH
tDSW
tDHW
tCLKL
tCLKH
tR
tF
Parameter
Clock Cycle Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise Time
Fall Time
Min
220
15
42
20
10
15
20
20
20
-
Typ
-
Max
15
15
D1
D0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 13-3 : Serial interface characteristics (4-wire SPI)
D/C#
t AS
t AH
t CSS
CS#
t CSH
tcycle
t CLKL
tCLKH
SCLK(D0)
tF
tR
t DSW
SDIN(D1)
t DHW
Valid Data
CS#
SCLK(D0)
SDIN(D1)
Solomon Systech
D7
D6
D5
D4
D3
Jan 2011
D2
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SSD1351
Table 13-5 : Serial Interface Timing Characteristics (3-wire SPI)
(VDDIO- VSS =1.65V- VCI, VCI - VSS = 2.4-3.5V, TA = 25°C)
Symbol
tcycle
tCSS
tCSH
tDSW
tDHW
tCLKL
tCLKH
tR
tF
Parameter
Clock Cycle Time
Chip Select Setup Time
Chip Select Hold Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise Time
Fall Time
Min
220
20
44
15
20
20
20
-
Typ
-
Max
15
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 13-4 : Serial interface characteristics (3-wire SPI)
CS#
SCLK
SDIN
D/C#
D7
D6
D5
D4
D3
t CSS
CS#
D2
t CYCLE
tF
tCLKH
tR
t DSW
SDIN
(D1)
SSD1351
D0
t CSH
t CLKL
SCLK
(D0)
D1
t DHW
Valid Data
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Solomon Systech
14 APPLICATION EXAMPLE
Figure 14-1 : SSD1351Z application example for 18-bit 6800-parallel interface mode
The configuration for 18-bit 6800-parallel interface mode is shown in the following diagram:
(VCI = 3.3V, VDDIO = 1.8V, external VCC = 16V, IREF = 12.5uA, BS[3:2] are set to 11b through command A0h)
Color OLED Panel
COM1
:
:
:
COM127
:
:
:
:
:
:
:
SA127
SB127
SC127
SA0
SB0
SC0
COM126
:
:
:
COM0
128RGBx128
VSS
VLSS
BGGND
FR
VSL
CL
CLS
GPIO0
GPIO1
VCI
IREF
VPP
VDD
VDDIO
BS1
BS0
D[17:0]
E
R/W#
D/C#
RES#
CS#
VCC
VCOMH
SSD1351Z
R1
C1
C2
C3
C4a
C4b
VCC
D[17:0]
E
R/W#
D/C#
RES#
CS#
C5
VDDIO VCI
R2
D1
D2
GND
Voltage at IREF = VCC – 6V. For VCC = 16V, IREF = 12.5uA:
R1 = (Voltage at IREF - VSS) / IREF
= (16-6) / 12.5u
= 800KΩ
R2 = 50Ω, 1/8W (1)
D1 ~ D2: Vth=0.7V, 1N4148 (1)
C1 ~ C3: 1uF, C4a, C5: 4.7uF, C4b: 0.1uF (1)
Note
(1)
The values are recommended value. Select appropriate value against module application.
(2)
It is recommended to tie VLSS and VSS at one common ground point to minimize circulating ground noise.
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Jan 2011
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Rev 1.5
SSD1351
15 PACKAGE INFORMATION
15.1 SSD1351UR1 detail dimension
SSD1351U
Figure 15-1: SSD1351UR1 Detail Dimension
C
L
Contact Side
Plating: Sn
Contact Side
Plating: Sn
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Rev 1.5
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Solomon Systech
15.2 SSD1351Z Die Tray Information
Figure 15-2: SSD1351UR1 Die Tray Information
Solomon Systech
Jan 2011
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SSD1351
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in
different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Solomon
Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the
failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products
for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of
the part
The product(s) listed in this datasheet comply with Directive 2002/95/EC of the European Parliament and of the council of 27 January 2004 on the
restriction of the use of certain hazardous substances in electrical and electronic equipment and People’s Republic of China Electronic Industry
Standard SJ/T 11363-2006 “Requirements for concentration limits for certain hazardous substances in electronic information products (电子信息产品
中有毒有害物质的限量要求)”. Hazardous Substances test report is available upon request.
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