NJW4152 Switching Regulator IC for Buck Converter w/ 40V/1A or 40V/600mA MOSFET GENERAL DESCRIPTION ■ PACKAGE OUTLINE The NJW4152 is a buck converter with 40V/1A or 40V/600mA MOSFET. It corresponds to high oscillating frequency, and Low ESR Output Capacitor (MLCC) within wide input range from 4.6V to 40V. Therefore, the NJW4152 can realize downsizing of an application with a few external parts. Also, it has a soft start function, an over current protection and a thermal shutdown circuit. Moreover there is an automotive for extended operating temperature range version. It is suitable for logic voltage generation from high voltage that Car Accessory, Office Automation Equipment, Industrial Instrument and so on. FEATURES Maximum Rating Input Voltage Wide Operating Voltage Range Switching Current NJW4152GM1-A (HSOP8) NJW4152R-B (MSOP8 (VSP8)) 45V 4.6V to 40V 1.4A(min.) @A version 0.8A(min.) @B version PWM Control Wide Oscillating Frequency 300kHz to 1MHz Soft Start Function 4ms typ. UVLO (Under Voltage Lockout) Over Current Protection / Thermal Shutdown Protection Standby Function Package Outline NJW4152GM1: HSOP8 NJW4152R: MSOP8(VSP8)* *MEET JEDEC MO-187-DA PRODUCT CLASSIFICATION Status Part Number Version Output Current Switching Current Limit (MIN.) Operating Voltage Package MP NJW4152GM1-A A 1.0A 1.4A 4.6 to 40V HSOP8 MP NJW4152GM1-A-T A 1.0A 1.4A 4.6 to 40V HSOP8 MP NJW4152GM1-A-T1 A 1.0A 1.4A 4.6 to 40V HSOP8 MP NJW4152GM1-AB AB 1.0A 1.4A 3.6 to 40V HSOP8 MP NJW4152GM1-AB-T1 AB 1.0A 1.4A 3.6 to 40V HSOP8 MP NJW4152R-B B 600mA 0.8A 4.6 to 40V U.D. NJW4152R-BA-Z BA 600mA 0.8A 4.4 to 40V MSOP8 (VSP8) MSOP8 (VSP8) Operating Temperature Range General Spec. -40 to +85°C Automotive T Spec. -40 to +105°C Automotive T1 Spec. -40 to +125°C General Spec. -40 to +85°C Automotive T1 Spec. -40 to +125°C General Spec. -40 to +85°C Automotive Z Spec. -40 to +125°C This data sheet is applied to "NJW4152GM1-A, NJW4152R-B". Please refer to each data sheet for other versions. Ver.2013-01-23 -1- NJW4152 PIN CONFIGURATION 1 8 2 7 3 6 4 5 1 8 2 7 3 6 4 5 PIN FUNCTION 1. PV+ 2. V+ 3. ON/OFF 4. RT 5. IN6. FB 7. GND 8. SW Exposed PAD on backside connect to GND NJW4152GM1-A NJW4152R-B BLOCK DIAGRAM V + PV + Regulator OCP UVLO ON/OFF High: ON Low : OFF (Standby) Pulse by Pulse Standby ON/OFF Low Frequency Control 480kΩ FB PWM OSC ER⋅AMP Buffer IN- SW Vref Soft Start TSD 0.8V RT -2- GND Ver.2013-01-23 NJW4152 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL Supply Voltage V+ (V+ pin, PV+ pin) PV+- SW pin Voltage VPV-SW IN- pin Voltage VINON/OFF pin Voltage VON/OFF Power Dissipation MAXIMUM RATINGS (Ta=25°C) UNIT +45 V +45 -0.3 to +6 +45 790 (*1) HSOP8 2,500 (*2) PD MSOP8(VSP8) Junction Temperature Range Operating Temperature Range Storage Temperature Range Tj Topr Tstg V V V mW 595 (*1) 805 (*2) °C °C °C -40 to +150 -40 to +85 -40 to +150 (*1): Mounted on glass epoxy board. (76.2×114.3×1.6mm:EIA/JDEC standard size, 2Layers) (*2): Mounted on glass epoxy board. (76.2×114.3×1.6mm:EIA/JDEC standard size, 4Layers), internal Cu area: 74.2×74.2mm RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL Supply Voltage V+ A version Output Current (*3) IOUT B version Timing Resistor RT Oscillating Frequency fosc (*3): At Static Status Ver.2013-01-23 MIN. 4.6 – – 18 300 TYP. – – – 27 700 MAX. 40 1.0 0.6 68 1,000 UNIT V A A kΩ kHz -3- NJW4152 (Unless otherwise noted, V+=VON/OFF=12V, RT=27kΩ, Ta=25°C) ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Under Voltage Lockout Block ON Threshold Voltage OFF Threshold Voltage Hysteresis Voltage VT_ON VT_OFF VHYS TSS Soft Start Block Soft Start Time Oscillator Block Oscillation Frequency Oscillation Frequency (Low Frequency Control) RT pin Voltage Oscillation Frequency deviation (Supply voltage) Oscillation Frequency deviation (Temperature) TEST CONDITION MIN. TYP. MAX. UNIT V+= L → H V+= H → L 4.3 4.2 60 4.5 4.4 100 4.6 4.54 – V V mV VB=0.75V 2 4 8 ms 630 700 770 kHz – 270 – kHz 0.24 0.275 0.31 V fOSC fOSC_LOW VIN-=0.4V, VFB=0.55V VRT + fDV V =4.6 to 40V – 1 – % fDT Ta=-40°C to +85°C – 2 – % VFB=1V, VIN-=0.7V VFB=1V, VIN-=0.9V -1.0% -0.1 – – 8 1 0.8 – 80 0.6 16 2 +1.0% +0.1 – – 24 4 V µA dB MHz µA mA VIN-=0.7V 100 – – % – – 1.4 0.8 – 0.3 0.28 1.7 1.0 – 0.5 0.48 2.0 1.3 1 Ω Ω A A µA Error Amplifier Block Reference Voltage Input Bias Current Open Loop Gain Gain Bandwidth Output Source Current Output Sink Current VB IB AV GB IOM+ IOM- PWM Comparate Block Maximum Duty Cycle MAXDUTY Output Block Output ON Resistance RON Switching Current Limit ILIM Switching Leak Current ILEAK A version, ISW=1A B version, ISW=0.6A A version B version VON/OFF=0V, V+=45V, VSW=0V ON/OFF Block ON Control Voltage VON VON/OFF= L → H 1.6 – V+ V OFF Control Voltage VOFF VON/OFF= H → L 0 – 0.5 V Pull-down Resistance RPD – 480 – kΩ General Characteristics Quiescent Current Standby Current IDD – – 2.5 – 2.8 1 mA µA -4- IDD_STB RL=no load, VIN-=0.7V, VFB=0.55V VON/OFF=0V Ver.2013-01-23 NJW4152 TYPICAL APPLICATIONS CIN2 V IN CIN1 ON/OFF High: ON Low: OFF (Standby) 4 RT 3 2 ON/OFF V + RT 1 PV + NJW4152 IN- FB GND SW 5 6 7 8 L SBD RNF CNF COUT V OUT CFB R2 RFB R1 Ver.2013-01-23 -5- NJW4152 CHARACTERISTICS Timing Resistor vs.Oscillation Frequency + o (V =12V, Ta=25 C) Oscillation Frequency f OSC (kHz) 1000 100 10 100 Timing Resistor R (kΩ) T Oscillation Frequency vs. Supply Voltage Reference Voltage vs. Supply Voltage o (RT=27kΩ, Ta=25 C) B 705 700 695 690 0 (Ta=25 C) 0.81 10 20 30 Supply Voltage V+ (V) 0.805 0.8 0.795 0.79 40 0 + 2 1 0 -6- 60 L Voltage Gain Av (dB) Quiescent Current I DD (mA) o (R =no load, VIN-=0.5V, Ta=25 C) 3 0 10 20 30 Supply Voltage V+ (V) 40 40 Error Amplifier Block Voltage Gain, Phase vs. Frequency Quiescent Current vs. Supply Voltage 4 10 20 30 Supply Voltage V+ (V) Phase 45 30 o (V =12V, Gain=40dB, Ta=25 C) Gain 135 90 45 15 0 0.1 180 1 10 100 1000 Frequency f (kHz) Phase Φ (deg) 710 Reference Voltage V (V) Oscillation Frequency f OSC (kHz) o 0 10000 Ver.2013-01-23 NJW4152 ■ CHARACTERISTICS Oscillator Frequency vs. Temperature Reference Voltage vs. Temperature 700 680 0.805 0.8 0.795 660 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (oC) 0.79 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (oC) 2.4 2.2 + V =12V + 2 V =40V 1.8 1.6 1.4 V+=4.5V 1.2 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (oC) 0.4 Output ON Resistance vs.Temperature (A ver., I =1A) (Ω) SW ON 0.5 V+=4.5V 0.3 + V =12V,40V 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (oC) Ver.2013-01-23 Limited switching Current ILIM (A) Limited Switching Current vs. Temperature (A ver.) Output ON Resistance R 2.6 (V+=12V) B 720 LIM Limited switching Current I Output ON Resistance RON (Ω) 0.81 Reference Voltage V (V) 740 (A) Oscillator Frequency f OSC (kHz) + (V =12V, RT=27kΩ) 1.6 Limited Switching Current vs. Temperature (B ver.) 1.4 V+=12V 1.2 V+=40V 1 0.8 V+=4.5V 0.6 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (oC) 0.5 Output ON Resistance vs.Temperature (B ver., I =0.6A) SW 0.4 V+=4.5V 0.3 0.2 V+=12V,40V 0.1 0 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (oC) -7- NJW4152 CHARACTERISTICS T_ON 4.5 4.45 4.4 V 4.35 (mA) DD T_OFF 7 6 5 4 3 4.3 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (oC) 2 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (oC) Quiescent Current vs. Temperature (RT=27kΩ, RL=no load, VIN-=0.5V) Standby Current vs. Temperature (VON/OFF=0V) 3 Quiescent Current I V Soft Start Time Tss (ms) 4.55 (V+=12V, VB=0.75V) 8 2.5 V+=40V 2 1.5 V+=4.5V V+=12V 1 0.5 0 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (oC) 1 Standby Current IDD_STB (µA) Threshold Voltage (V) 4.6 Soft Start Time vs. Temperature Under Voltage Lockout Voltage vs. Temperature 0.8 0.6 0.4 0.2 V+=40V V+=12V V+=4.5V 0 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (oC) Switching Leak Current vs. Temperature Switching Leak Current ILEAK (µA) + -8- 5 (V =45V,VON/OFF =0V, VSW =0V) 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (oC) Ver.2013-01-23 NJW4152 ApplicationNJW4152 Manual Technical Information PIN DESCRIPTIONS PIN PIN NAME NUMBER 1 PV+ 2 V+ 3 ON/OFF 4 RT 5 IN- 6 FB 7 8 GND SW Exposed PAD – FUNCTION Power Supply pin for Power Line Power Supply pin for IC Control ON/OFF Control pin The ON/OFF pin internally pulls down with 480kΩ. Normal Operation at the time of High Level. Standby Mode at the time of Low Level or OPEN. Oscillating Frequency Setting pin by Timing Resistor. Oscillating Frequency should set between 300kHz and 1MHz. Output Voltage Detecting pin Connects output voltage through the resistor divider tap to this pin in order to voltage of the IN- pin become 0.8V. Feedback Setting pin The feedback resistor and capacitor are connected between the FB pin and the IN- pin. GND pin Switch Output pin of Power MOSFET Connect to GND (only HSOP8 PKG) Description of Block Features 1. Basic Functions / Features Error Amplifier Section (ER⋅AMP) 0.8V±1% precise reference voltage is connected to the non-inverted input of this section. To set the output voltage, connects converter's output to inverted input of this section (IN- pin). If requires output voltage over 0.8V, inserts resistor divider. This AMP section has high gain and external feedback pin (FB pin). It is easy to insert a feedback resistor and a capacitor between the FB pin and the IN- pin, making possible to set optimum loop compensation for each type of application. Oscillation Circuit Section (OSC) Oscillation frequency can be set by inserting resistor between the RT pin and GND. Referring to the sample characteristics in "Timing Resistor and Oscillation Frequency", set oscillation between 300kHz and 1MHz. Ver.2013-01-23 -9- NJW4152 NJW4152Application Manual Technical Information Description of Block Features (Continued) PWM Comparator Section (PWM) This section controls the switching duty ratio. PWM comparator receives the signal of the error amplifier and the triangular wave, and controls the duty ratio between 0% and 100%. The timing chart is shown in Fig.1. FB pin Voltage OSC Waveform (IC internal) Maximum duty: 100% ON SW pin OFF Fig. 1. Timing Chart PWM Comparator and SW pin Power MOSFET (SW Output Section) The power is stored in the inductor by the switch operation of built-in power MOSFET. The output current is limited to 1.4A(min.)@A version and 0.8A(min.)@B version by the overcurrent protection function. In case of step-down converter, the forward direction bias voltage is generated with inductance current that flows into the external regenerative diode when MOSFET is turned off. The SW pin allows voltage between the PV+ pin and the SW pin up to +45V. However, you should use an Schottky diode that has low saturation voltage. Power Supply, GND pin (V+, PV+ and GND) In line with switching element drive, current flows into the IC according to frequency. If the power supply impedance provided to the power supply circuit is high, it will not be possible to take advantage of IC performance due to input voltage fluctuation. Therefore insert a bypass capacitor close to the V+ pin – the GND pin connection in order to lower high frequency impedance. - 10 - Ver.2013-01-23 NJW4152 ApplicationNJW4152 Manual Technical Information 2. Additional and Protection Functions / Features Under Voltage Lockout (UVLO) The UVLO circuit operating is released above V+=4.5V(typ.) and IC operation starts. When power supply voltage is low, IC does not operate because the UVLO circuit operates. There is 100mV width hysteresis voltage at rise and decay of power supply voltage. Hysteresis prevents the malfunction at the time of UVLO operating and releasing. Soft Start Function (Soft Start) The output voltage of the converter gradually rises to a set value by the soft start function. The soft start time is 4ms (typ). It is defined with the time of the error amplifier reference voltage becoming from 0V to 0.75V. The soft start circuit operates after the release UVLO and/or recovery from thermal shutdown. The operating frequency is controlled with a low frequency, approximately 40% of the set value by the timing resistor, until voltage of the IN- pin becomes approximately 0.4V. 0.8V Vref, IN- pin Voltage FB pin Voltage OSC Waveform ON SW pin OFF UVLO(4.5V typ.) Release, Standby, Recover from Thermal Shutdow n Low Frequency Control V IN-=approx 0.4V Soft Start time: Tss=4ms(typ.) to V B=0.75V Steady Operaton Soft Start effective period to V B=0.8V Fig. 2. Startup Timing Chart Ver.2013-01-23 - 11 - NJW4152 NJW4152Application Manual Technical Information Description of Block Features (Continued) Over Current Protection Circuit (OCP) At when the switching current becomes ILIM or more, the overcurrent protection circuit is stopped the MOSFET output. The switching output holds low level down to next pulse output at OCP operating. The NJW4152 output returns automatically along with release from the over current condition because the OCP is pulse-by-pulse type. Fig.3. shows the timing chart of the over current protection detection. If voltage of the IN- pin becomes less than 0.4V, the oscillation frequency decreases to approximately 40% and the energy consumption is suppressed. FB pin Voltage OSC Waveform ON SW pin OFF Sw itching Current ILIM 0 Static Status Detect Overcurrent Static Status Fig. 3. Timing Chart at Over Current Detection Thermal Shutdown Function (TSD) When Junction temperature of the NJW4152 exceeds the 175°C*, internal thermal shutdown circuit function stops SW function. When junction temperature decreases to 145°C* or less, SW operation returns with soft start operation. The purpose of this function is to prevent malfunctioning of IC at the high junction temperature. Therefore it is not something that urges positive use. You should make sure to operate within the junction temperature range rated (150°C). (* Design value) ON/OFF Function (Standby Control) The NJW4152 stops the operating and becomes standby status when the ON/OFF pin becomes less than 0.5V. The ON/OFF pin internally pulls down with 480kΩ, therefore the NJW4152 becomes standby mode when the ON/OFF pin is OPEN. You should connect this pin to V+ when you do not use ON/OFF function. - 12 - Ver.2013-01-23 NJW4152 ApplicationNJW4152 Manual Technical Information Application Information Inductors Current Peak Current Ipk Large currents flow into inductor, therefore you must provide current capacity that does not saturate. Inductor (1) Continuous Conduction Mode Reducing L, the size of the inductor can be smaller. Current ∆IL However, peak current increases and adversely (2) Critical Mode affecting efficiency. (3) Continuous On the other hand, increasing L, peak current can 0 Conduction Mode be reduced at switching time. Therefore conversion Frequency tON tOFF fOSC efficiency improves, and output ripple voltage reduces. Above a certain level, increasing inductance windings increases loss (copper loss) due to the resistor Fig. 4. Inductor Current State Transition element. Ideally, the value of L is set so that inductance current is in continuous conduction mode. However, as the load current decreases, the current waveform changes from (1) CCM: Continuous Conduction Mode → (2) Critical Mode → (3) DCM: Discontinuous Conduction Mode (Fig. 4.). In discontinuous mode, peak current increases with respect to output current, and conversion efficiency tend to decrease. Depending on the situation, increase L to widen the load current area to maintain continuous mode. If the application needs maximum output current, the inductor ripple current should be set less than 20% to prevent operating the over current protection circuit at the minimum switching limiting current. Catch Diode When the switch element is in OFF cycle, power stored in the inductor flows via the catch diode to the output capacitor. Therefore during each cycle current flows to the diode in response to load current. Because diode's forward saturation voltage and current accumulation cause power loss, a Schottky Barrier Diode (SBD), which has a low forward saturation voltage, is ideal. An SBD also has a short reverse recovery time. If the reverse recovery time is long, through current flows when the switching transistor transitions from OFF cycle to ON cycle. This current may lower efficiency and affect such factors as noise generation. Input Capacitor Transient current flows into the input section of a switching regulator responsive to frequency. If the power supply impedance provided to the power supply circuit is large, it will not be possible to take advantage of the NJW4152 performance due to input voltage fluctuation. Therefore insert an input capacitor as close to the MOSFET as possible. Output Capacitor An output capacitor stores power from the inductor, and stabilizes voltage provided to the output. When selecting an output capacitor, you must consider Equivalent Series Resistance (ESR) characteristics, ripple current, and breakdown voltage. Also, the ambient temperature affects capacitors, decreasing capacitance and increasing ESR (at low temperature), and decreasing lifetime (at high temperature). Concerning capacitor rating, it is advisable to allow sufficient margin. Output capacitor ESR characteristics have a major influence on output ripple noise. A capacitor with low ESR can further reduce ripple voltage. Be sure to note the following points; when ceramic capacitor is used, the capacitance value decreases with DC voltage applied to the capacitor. Ver.2013-01-23 - 13 - NJW4152 NJW4152Application Manual Technical Information Application Information (Continued) Board Layout In the switching regulator application, because the current flow corresponds to the oscillation frequency, the substrate (PCB) layout becomes an important. You should attempt the transition voltage decrease by making a current loop area minimize as much as possible. Therefore, you should make a current flowing line thick and short as much as possible. Fig.5. shows a current loop at step-down converter. Especially, should lay out high priority the loop of CIN-SW-SBD that occurs rapid current change in the switching. It is effective in reducing noise spikes caused by parasitic inductance. NJW4152 Built-in SW V IN CIN NJW4152 Built-in SW L SBD COUT V IN CIN (a) Buck Converter SW ON L SBD COUT (b) Buck Converter SW OFF Fig. 5. Current Loop at Buck Converter Concerning the GND line, it is preferred to separate the power system and the signal system, and use single ground point. The voltage sensing feedback line should be as far away as possible from the inductance. Because this line has high impedance, it is laid out to avoid the influence noise caused by flux leaked from the inductance. Fig. 6. shows example of wiring at buck converter. Fig. 7 shows the PCB layout example. L PV + V IN V+ CIN V OUT SW SBD COUT RL (Bypass Capacitor) NJW4152 RFB RT RT CFB INR2 GND Separate Digital(Signal) GND from Pow er GND R1 To avoid the influence of the voltage drop, the output voltage should be detected near the load. Because IN- pin is high impedance, the voltage detection resistance: R1/R2 is put as much as possible near IC(IN-). Fig. 6. Board Layout at Buck Converter - 14 - Ver.2013-01-23 NJW4152 ApplicationNJW4152 Manual Technical Information Application Information (Continued) GNDOUT GND IN Power GND Area C IN1 C OUT SBD L VIN C IN2 ON/OFF To Signal GND VOUT RFB C FB RT RNF R1 C NF R2 Signal GND Area Feed back signal Connect Signal GND line and Power GND line on backside pattern Fig. 7 Layout Example (upper view) Ver.2013-01-23 - 15 - NJW4152 NJW4152Application Manual Technical Information Calculation of Package Power A lot of the power consumption of buck converter occurs from the internal switching element (Power MOSFET). Power consumption of NJW4152 is roughly estimated as follows. Input Power: Output Power: Diode Loss: NJW4152 Power Consumption: Where: VIN VOUT VF OFF duty PIN = VIN × IIN [W] POUT = VOUT × IOUT [W] PDIODE = VF × IL(avg) × OFF duty [W] PLOSS = PIN − POUT − PDIODE [W] : Input Voltage for Converter : Output Voltage of Converter : Diode's Forward Saturation Voltage : Switch OFF Duty IIN IOUT IL(avg) : Input Current for Converter : Output Current of Converter : Inductor Average Current Efficiency (η) is calculated as follows. η = (POUT ÷ PIN) × 100 [%] You should consider temperature derating to the calculated power consumption: PD. You should design power consumption in rated range referring to the power dissipation vs. ambient temperature characteristics (Fig. 8). MSOP8(VSP8) Package Power Dissipation vs. Ambient Temperature HSOP8 Package Power Dissipation vs. Ambient Temperature o o (Tj= ~150 C) At on 4 layer PC Board At on 2 layer PC Board 2500 (Tj= ~150 C) 1000 At on 4 layer PC Board At on 2 layer PC Board 800 D 2000 Power Dissipation P (mW) D Power Dissipation P (mW) 3000 Operating Temp Expand spec 1500 1000 General spec 500 0 600 400 200 0 0 25 50 75 100 125 o Ambient Temperature Ta ( C) 0 25 50 75 100 125 o Ambient Temperature Ta ( C) Mounted on glass epoxy board. (76.2×114.3×1.6mm:EIA/JDEC standard size, 2Layers) Mounted on glass epoxy board. (76.2×114.3×1.6mm:EIA/JDEC standard size, 4Layers), internal Cu area: 74.2×74.2mm Fig. 8. Power Dissipation vs. Ambient Temperature Characteristics - 16 - Ver.2013-01-23 NJW4152 ApplicationNJW4152 Manual Technical Information Application Design Examples Step-Down Application Circuit IC : NJW4152GM1 Input Voltage : VIN=12V Output Voltage : VOUT=5V Output Current : IOUT=1A Oscillation frequency : fosc=700kHz Output Ripple Voltage : Vripple(P-P)=less than 20mV CIN2 0.1µF/50V CIN1 10µF/50V V IN=12V ONOFF High: ON Low: OFF (Standby) RT 27kΩ 4 RT 3 2 ON/OFF V + 1 PV + NJW4152GM1 C1 open IN- FB GND SW 5 6 7 8 L 22µH/2.5A SBD RNF 3.3kΩ CNF 4,700pF COUT 4.7µF/6.3V CFB 220pF RFB 0Ω V OUT =5V R2 27kΩ R1 5.1kΩ IC Reference Qty. 1 L 1 CDRH8D28HPNP-220N D CIN1 CIN2 COUT CNF CFB C1 R1 R2, RT RNF RFB 1 1 1 1 1 1 0 1 2 1 1 CMS11 UMK325BJ106MM 0.1µF JMK212ABJ475KG 4,700pF 220pF ⎯ (Optional) 5.1kΩ 27kΩ 3.3kΩ 0Ω (Short) Ver.2013-01-23 Part Number NJW4152GM1 Description Internal 1A MOSFET SW.REG. IC Inductor 22µH, 2.5A(Ta=20°C) / 1.9A (Ta=100°C) Schottky Diode 40V, 2A Ceramic Capacitor 3225 10µF, 50V, X5R Ceramic Capacitor 1608 0.1µF, 50V, B Ceramic Capacitor 2012 4.7µF, 6.3V, X5R Ceramic Capacitor 1608 4,700pF, 50V, B Ceramic Capacitor 1608 220pF, 50V, CH Optional Resistor 1608 5.1kΩ, ±1%, 0.1W Resistor 1608 27kΩ, ±1%, 0.1W Resistor 1608 3.3kΩ, ±5%, 0.1W Resistor 1608 0Ω, 0.1W Manufacturer New JRC Sumida Toshiba Taiyo Yuden Std. Taiyo Yuden Std. Std. ⎯ Std. Std. Std. Std. - 17 - NJW4152 NJW4152Application Manual Technical Information Application Design Examples (Continued) Setting Oscillation Frequency From the Oscillation frequency vs. Timing Resistor Characteristic, RT=27 [kΩ], t=1.43[µs] at fosc=700kHz. Step-down converter duty ratio is shown with the following equation. Duty = VOUT + V F 5 + 0.4 × 100 = × 100 = 45 [%] 12 V IN Therefore, tON=0.64 [µs], tOFF=0.79 [µs] Peak Current: Ipk Inductance Current: ∆IL Output Current: IOUT 0 Period: t Frequency: fOSC=1/t tON tOFF Fig. 9. Inductor Current Waveform Selecting Inductance To assume maximum output current: 1A, and the inductor ripple current should be set not to exceed the minimum switching limiting current: ILIM=1.4A (min.). ∆IL is Inductance ripple current. When to ∆IL= output current 20%: ∆IL = 0.2 × IOUT = 0.2 × 1 = 0.2 [A] This obtains inductance L. VDS_RON is drop voltage by MOSFET on resistance. L= VIN − VDS − RON − VOUT 12 − 0.5 − 5 × tON = × 0.64 µ = 20.8 [ µH ] ⇒ 22[µH] ∆I L 0 .2 Inductance L is a theoretical value. The optimum value varies according such factors as application specifications and components. Fine-tuning should be done on the actual device. This obtains the peak current Ipk at switching time. Ipk = I OUT + ∆I L 0 .2 = 1+ = 1.1 [ A] 2 2 The current that flows into the inductance provides sufficient margin for peak current at switching time. In the application circuit, use L=22µH, 2.5A(Ta=20°C) / 1.9A (Ta=100°C). - 18 - Ver.2013-01-23 NJW4152 ApplicationNJW4152 Manual Technical Information Application Design Examples (Continued) Selecting the Input Capacitor The input capacitor corresponds to the input of the power supply. It is required to adequately reduce the impedance of the power supply. The input capacitor selection should be determined by the input ripple current and the maximum input voltage of the capacitor rather than its capacitance value. The effective input current can be expressed by the following formula. I RMS = I OUT × VOUT × (V IN − VOUT ) V IN [ A] In the above formula, the maximum current is obtained when VIN = 2 × VOUT, and the result in this case is IRMS = IOUT (MAX) ÷ 2. When selecting the input capacitor, carry out an evaluation based on the application, and use a capacitor that has adequate margin. Selecting the Output Capacitor The output capacitor is an important component that determines output ripple noise. Equivalent Series Resistance (ESR), ripple current, and capacitor breakdown voltage are important in determining the output capacitor. The output ripple noise can be expressed by the following formula. ESR = Vripple ( p − p ) ∆I L When selecting output capacitance, select a capacitor that allows for sufficient ripple current. The effective ripple current that flows in a capacitor (Irms) is obtained by the following equation. I rms = ∆I L 0.2 = = 58 [ mArms ] 2 3 2 3 Consider sufficient margin, and use a capacitor that fulfills the above spec. In the application circuit, use COUT=4.7µF/6.3V. Setting Output Voltage The output voltage VOUT is determined by the relative resistances of R1, R2. The current that flows in R1, R2 must be a value that can ignore the bias current that flows in ER AMP. ⎛ 27k ⎞ ⎛ R2 ⎞ VOUT = ⎜ + 1⎟ × 0.8 = 5.04 [V ] + 1⎟ × V B = ⎜ R 1 ⎝ 5.1k ⎠ ⎝ ⎠ Ver.2013-01-23 - 19 - NJW4152 NJW4152Application Manual Technical Information Compensation design example A switching regulator requires a feedback circuit for acquiring a stable output. Because the frequency characteristics of the application change according to the inductance, output capacitor, and so on, the compensation constant should ideally be determined in such a way that the maximum band is acquired while the necessary phase for stable operation is maintained. These compensation constants play an important role in the adjustment of the NJW4152 when mounted in an actual unit. Finally, select the constants while performing measurement, in consideration of the application specifications. Pole Gain -20dB/dec Phase 0° -45° -90° fP/10 fP 10fP Frequency Pole +20dB/dec Gain Zero +90° Phase Feedback and Stability Basically, the feedback loop should be designed in such a way that the open loop phase shift at the point where the loop gain is 0 dB is less than -180°. It is also important that the loop characteristics have margin in consideration of ringing and immunity to oscillation during load fluctuations. With the NJW4152, the feedback circuit can be freely designed, enabling the arrangement of the poles and zeros which is important for loop compensation, to be optimized. +45° 0° fZ/10 fZ 10fZ Frequency Zero The characteristics of the poles and zeros are shown in Fig. 10. Poles: The gain has a slope of -20 dB/dec, and the phase shifts -90°. Zeros: The gain has a slope of +20 dB/dec, and the phase shift +90°. Fig. 10. Characteristics of Pole and Zero If the number of factors constituting poles is defined as “n”, the change in the gain and phase will be “n”-fold. This also applies to zeros as well. The poles and zeros are in a reciprocal relationship, so if there is one factor for each pole and zero, they will cancel each other. Configuration of the compensation circuit PV VIN + LC Gain Buffer SW L VOUT RESR CFB R2 COUT ER⋅AMP PWM CFB Vref =0.8V RFB IN- FB R1 CNF RNF C1(option) Fig. 11. Compensation Circuit Configuration - 20 - Ver.2013-01-23 NJW4152 ApplicationNJW4152 Manual Technical Information Compensation Design (Continued) Poles and zeros due to the inductance and output capacitor Double poles fP(LC) are generated by the inductance and output capacitor. Simultaneously, single zeros fZ(ESR) are generated by the output capacitor and ESR. Each pole and zero is expressed by the following formula. f Z(ESR ) = 1 fP(LC ) = 2πC OUTR ESR 1 2π LC OUT If the ESR of the output capacitor is high, fZ(ESR) will be located in the vicinity of fP(LC). In an application such as this, the zero fZ(ESR) compensates the double poles fP(LC), resulting in a tendency for stability to be readily maintained. However, if the ESR of the output capacitor is low, fZ(ESR) shifts to the high region, and the phase is shifted -180° by fP(LC).The NJW4152 compensation circuit enables compensation to be realized by using zeros fZ1 and fZ2. Gain (dB) Poles and zeros due to error amplifier The single poles and zeros generated by the error amplifier LC Gain are obtained using the following formula. Zero Pole 1 fP1 = 1 fZ1 = ⎛ R1 R2 ⎞ Loop 2πCNF A V ⎜ ⎟ 2πCNFRNF Gain ⎝ R1 + R2 ⎠ (Av: Amplifier Open Loop Gain=80dB) fZ 2 = 1 2πCFBR2 fP 2 = Double pole -40dB/dec 0dB frequency * Gain increase due to Zero 1 R1 R2 ⎞ ⎛ 2πC FB ⎜ R FB + ⎟ R1 + R2 ⎠ ⎝ 1 fP 3 = 2πC1 R NF -20dB/dec Compensation Gain (Option) fZ1 and fZ2 are located on both sides of fP(LC). Because the inductance and output capacitor vary, they are each set using the following as a rough guide. fP(LC) × 0.5-fold – 0.9-fold fP(LC) × 1.1-fold – 2.0-fold fP1 fZ1 or fZ2 fP(LC) fP2 fP3 fZ(ESR) Fig12. Loop Gain examples There is also a method in which fZ1 and fZ2 are located at positions lower than even fP(LC). Because there is a tendency for the phase shift to increase and the gain to rise, it can be expected that the response will improve. However, there is a tendency for the phase margin to become insufficient, so care is necessary. fP1 creates poles in the low frequency region due to the Miller effect of the error amplifier. The stability becomes better as fP1 becomes lower. On the other hand, the frequency characteristics do not improve, so the response is adversely affected. fP1 is set using a frequency gain of 20 dB for fP(LC) as a rough guide. If the open loop gain of the error amplifier is made 80 dB, design is carried out using fP1 < fP(LC) ÷ 103 (= 60 dB) as a rough guide. Above several 100 kHz, various poles are generated, so the upper limit of the frequency range where the loop gain is 0 dB is set to fifth (1/5) to tenth (1/10) of oscillation frequency. The fZ(ESR) in the high frequency region sometimes causes a loop gain to be generated (See Fig.12 Loop Gain “). Using fP2 and fP3, perform adjustment with the NJW4152 mounted in an actual unit, so as to adequately reduce the loop gain in the high frequency region. Ver.2013-01-23 - 21 - NJW4152 NJW4152Application Manual Technical Information ■Application Characteristics :NJW4152GM1-A ● At VOUT=5.0V setting (R1=5.1kΩ, R2=27kΩ, CFB=220pF, RFB=0Ω) Efficiency vs. Output Current Output Voltage vs. Output Current o (V) f=700kHz L=22µH V =6V IN V =12V IN V =18V IN V =24V IN 1 (Ta=25 C) 5.2 OUT 100 90 80 70 60 50 40 30 20 10 0 Output Voltage V Efficiency η (%) o (VOUT=5.0V, Ta=25 C) 5.1 5.05 5 VIN=6V,12V, 18V, 24V 4.95 4.9 4.85 4.8 10 100 1000 Output Current IOUT (mA) f=700kHz L=22µH 5.15 1 10 100 1000 Output Current IOUT (mA) ● At VOUT=3.3V setting (R1=5.1kΩ, R2=16kΩ, CFB=220pF, RFB=0Ω) Efficiency vs. Output Current Output Voltage vs. Output Current o (VOUT=3.3V, Ta=25 C) (V) f=700kHz L=22µH V =5V IN V =12V IN V =18V IN V =24V IN 1 (Ta=25 C) 3.36 OUT 100 90 80 70 60 50 40 30 20 10 0 Output Voltage V Efficiency η (%) o 3.32 3.3 VIN=5V,12V, 18V, 24V 3.28 3.26 3.24 10 100 1000 Output Current IOUT (mA) f=700kHz L=22µH 3.34 1 10 100 1000 Output Current IOUT (mA) ● At VOUT=1.5V setting (R1=30kΩ, R2=27kΩ, CFB=220pF, RFB=10kΩ) Efficiency vs. Output Current Output Voltage vs. Output Current - 22 - o (VOUT=1.5V, Ta=25 C) (V) f=700kHz L=22µH V =5V IN V =12V IN V =18V IN V =24V IN 1 (Ta=25 C) 1.56 OUT 100 90 80 70 60 50 40 30 20 10 0 10 100 1000 Output Current IOUT (mA) Output Voltage V Efficiency η (%) o f=700kHz L=22µH 1.54 1.52 1.5 VIN=5V,12V, 18V, 24V 1.48 1.46 1.44 1 10 100 1000 Output Current IOUT (mA) Ver.2013-01-23 NJW4152 MEMO [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2013-01-23 - 23 -