NJM2573

NJM2573
LOW VOLTAGE 3ch VIDEO AMPLIFIER WITH LPF
 GENERAL DESCRIPTION
The NJM2573 is a Low Voltage 3ch Video Amplifier with LPF.
Internal 75 driver is easy to connect TV monitor directly.
The NJM2573 corresponds to a clamp and bias inputs, and
selection of a clamp/ bias is possible for one circuit, and it
corresponds to various video signals.
FEATURES
 Operating Voltage
 Input type
 PACKAGE OUTLINE
NJM2573V
2.8 to 5.5V
Vin1: CLAMP
Vin2: CLAMP/ BIAS
Vin3: BIAS
 Internal LPF
 Internal 6dB amplifier
 Internal 75 Driver Circuit (2-system drive)
 Internal Power Saving Circuit
 Bipolar Technology
 Package Outline
SSOP14

BLOCK DIAGRAM
+
+
V
V
6dB
Vin1
75 driver
Vout1
LPF
CLAMP
Vsag1
6dB
Vin2
CLAMP/BIAS
SW
75 driver
Vout2
LPF
Vsag2
CLAMP
BIAS
6dB
Vin3
75 driver
Vout3
LPF
BIAS
GND
Power Save
GND
Ver.9
-1-
NJM2573
PIN CONFIGURATION
SSOP14
1
14
2
13
3
12
4
11
5
10
6
9
7
8
1. Vsag1
+
2. V 1
3. Vin1
4. Power Save
5. Vin2
6. GND1
7. Vin3
8. CLAMP/BIAS SW
9. Vout3
10. GND2
11. Vout2
12. Vsag2
+
13. V 2
14. Vout1
Ver.9
-2-
NJM2573
ABSOLUTE MAXIMUM RATINGS (Ta=25C)
PARAMETER
SYMBOL
+
Supply Voltage
V
Power Dissipation
PD
Operating Temperature Range
Topr
Storage Temperature Range
Tstg
RATINGS
7.0
300
-40 to +85
-40 to +125
UNIT
V
mW
C
C
+
ELECTRICAL CHARACTERISTICS (V =3.0V,RL=150,Ta=25C)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
2.8
3.0
5.5
V
No Signal
-
18.0
26.0
mA
-
60
90
µA
Operating Voltage
Vopr
Operating Current
ICC
Operating Current
at Power Save
Isave
Power Save Mode
Vomv
f=1kHz,THD=1%, CLAMP Input
2.2
2.4
-
Vom
RGB
f=1kHz,THD=1%, BIAS Input
1.4
2.2
-
6.0
6.4
6.8
-0.5
0.0
+0.5
-
-2.0
-
-
-12
-
-
-65
-
dB
-
0.2
-
%
-
0.2
-
deg
-
+60
-
dB
-
-40
-
dB
VthPH
1.8
-
V
VthPL
0
-
0.3
Maximum Output
Voltage Swing
Voltage Gain
Gv
Gfy4.5M
Low Pass Filter
Characteristic
Gfy8M
Gfy16M
Cross talk
CT
Differential Gain
DG
Differential Phase
DP
S/N Ratio
SNv
2nd. Distortion
Hv
SW Change
Voltage High Level
SW Change
Voltage Low Level
Vp-p
Vin=100kHz, 1.0Vp-p,Sin Signal (CLAMP)
Vin=100kHz 0.7Vp-p,Sin Signal (BIAS)
Vin=4.5MHz/100kHz, 1.0Vp-p(CLAMP)
Vin=4.5MHz/100kHz, 0.7Vp-p(BIAS)
Vin=8MHz/100kHz, 1.0Vp-p(CLAMP)
Vin=8MHz/100kHz, 0.7Vp-p(BIAS)
Vin=16MHz/100kHz, 1.0Vp-p(CLAMP)
Vin=16MHz/100kHz, 0.7Vp-p(BIAS)
Vin=4.43MHz, 1.0Vp-p,Sin Signal (CLAMP)
Vin=4.43MHz 0.7Vp-p,Sin Signal (BIAS)
(CLAMP) Vin=1.0Vp-p
Input 10step Video Signal
(CLAMP) Vin=1.0Vp-p
Input 10step Video Signal
(CLAMP) Vin=1.0Vp-p,100% White Video Signal
(BIAS) Vin=0.7Vp-p,100% Red field Signal
(CLAMP) Vin=1.0Vp-p, 3.58MHz,
Sin Signal, RL=75
(BIAS) Vin=0.7Vp-p, 3.58MHz,
Sin Signal, RL=75
dB
dB
+
V
CONTROL TERMINAL
PARAMETER
Power Save
CLAMP/BIAS SW
STATUS
NOTE
H
Power Save: ON
L
Power Save: OFF
OPEN
Power Save: OFF
H
BIAS
L
CLAMP
OPEN
CLAMP
Ver.9
-3-
NJM2573
 TEST CIRCUIT (SSOP14)
V+
0.1µF
+
10µF
33µF
+
33µF
1
Vsag1
Vout1 14
2
V+1
3
Vin1
4
Power Save
Vout2 11
5
Vin2
GND2 10
6
GND1
Vout3
9
7
Vin3
C/B SW
8
75Ω
75Ω
+
OUT1-1 OUT1-2
V+2
13
0.1µF
IN1
+
33µF
NJM2573V
Vsag2 12
+
75Ω
33µF
0.1µF
IN2
+
75Ω
75Ω
+
OUT2-1 OUT2-2
75Ω
10µF
0.1µF
IN3
+
75Ω
75Ω
+
OUT3-1 OUT3-2
75Ω
Ver.9
-4-
NJM2573
 APPLICATION CIRCUIT (VIN2: CLAMP)
(1) Standard circuit
(2) SAG correction unused circuit
V+
0.1µF
+
V+
10µF
0.1µF
+
10µF
33µF
+
33µF
1
Vsag1
Vout1 14
75Ω
+
OUT1
1
Vsag1
2
V +1
3
Vin1
4
Power Save
470µF 75Ω
Vout1 14
OUT1
+
C1
2
V +1
3
Vin1
V+2
13
0.1µF
IN1
33µF
NJM2573V
Vsag2 12
IN1
75Ω
4
Power Save
Vout2 11
Vin2
470µF 75Ω
OUT2
(CLAMP)
0.1µF
GND2 10
IN2
10µF
GND1
7
Vin3
Vout3
9
C/B SW
8
+
5
Vin2
GND2 10
6
GND1
Vout3
9
7
Vin3
C/B SW
8
75Ω
75Ω
10µF
OUT3
0.1µF
IN3
OUT2
+
Vout2 11
(CLAMP)
75Ω
6
Vsag2 12
75Ω
+
0.1µF
5
NJM2573V
75Ω
C1
IN2
13
0.1µF
+
33µF
V +2
75Ω
OUT3
+
0.1µF
IN3
75Ω
75Ω
(3) Two-line driving circuit
V+
0.1µF
+
10µF
33µF
+
100µF
1
Vsag1
Vout1 14
+
C1
2
V+1
V+2
3
Vin1
4
Power Save
OUT2
75Ω
13
0.1µF
IN1
OUT1
75Ω
33µF
NJM2573V
Vsag2 12
+
75Ω
100µF
Vout2 11
+
C1
0.1µF
IN2
5
Vin2
GND2 10
6
GND1
Vout3
75Ω
75Ω
OUT1
OUT2
(CLAMP)
75Ω
10µF
9
+
OUT1
75Ω
OUT2
75Ω
0.1µF
7
IN3
Vin3
C/B SW
8
75Ω
(1) Standard circuit
The SAG correction reduces output coupling capacitor values.
The capacitor of C1 (33µF) is recommended for the portable application.
However, the 33µF capacitor may deteriorate SAG, and lose synchronization by luminance fluctuation.
Adjust the C1 value, checking the waveform containing a lot of low frequency components like a bounce
waveform (In case of worst condition). Change the capacitor of C1 into a large value to improve SAG.
(2) SAG correction unused circuit
Cancel the SAG correction to improve lost synchronization.
Connect the coupling capacitor after connecting the Vout pin and Vsag pin. The recommended value is 470µF or
more.
(3) Two-line driving circuit
The NJM2573 drives two-line load of 150Ω.
The capacitance value of C1 should be 100µF or more, because SAG is deteriorated than a standard circuit.
Ver.9
-5-
NJM2573
EQUIVALENT CIRCUIT
PIN No.
PIN NAME
FUNCTION
INSIDE EQUIVALENT CIRCUIT
V+
1
12
Vsag1
Vsag2
Vsag
Sag compensation
ｃ
8.8k
750
GND
2
13
+
V1
+
V2
Power Supply
+
V
270
3
VIN1
Clamp input
270
Vin1
ｃ
GND
V+
SW
4
Power Save
32k
ｃ
Power save
48k
GND
+
V
5
Vin2
Clamp/Bias input
270
270
20k
270
Vin2
ｃ
GND
6
10
GND1
GND2
GND
-
Ver.9
-6-
NJM2573
PIN No.
PIN NAME
FUNCTION
INSIDE EQUIVALENT CIRCUIT
V+
20k
7
Vin3
Bias input
270
Vin3
ｃ
GND
SW
32k
ｃ
8
CLAMP/
BIAS SW
Clamp/Bias switch
48k
GND
+
V
9
Vout3
8.8k
Bias output
Vout3
ｃ
GND
V+
11
14
Vout2
Vout1
Clamp/Bias output
Clamp output
8.8k
750
Vout
ｃ
GND
 APPLICATION
When the power supply voltage is not impressing, don’t impress voltage to the control terminal.
Ver.9
-7-
NJM2573
 APPLICATION
 SAG correction circuit
SAG correction circuit is a circuit to correct for low-frequency attenuation by high-pass filter consisting of the
output coupling capacitance and load resistance. Low-frequency attenuation raises the sag in the vertical period of
the video signal.
Capacitor for Vsag (Csag) is connected to the negative feedback of the amplifier. This Csag increase the low
frequency gain to correct for the attenuation of low frequency gain.
Example SAG collection circuit
Vout
Cout
Vsag
Csag
resistance:RL
Vout1
Example of not using sag compensation circuit
resistance:RL
Vout
Cout
Vout1
Vsag
Waveform of Vout terminal and Vout1 terminal
using SAG correction circuit
Waveform of Vout
Waveform of Vout1
1Vertical period
not using SAG correction circuit
Waveform of Vout
Waveform of Vout1
1Vertical period
Ver.9
-8-
NJM2573
SAG correction circuit generates a low frequency component signal amplified to Vout terminal.
Changes of the luminance signal will be low-frequency components, if you want to output a large signal luminance
changes. Therefore, generate correction signal of change of a luminance signal to Vout pin.
At this time, signal is over the dynamic range of Vout pin. This may cause a lack of sync signal, and waveform
distortion.
Please see diagram below (green waveform), if you want to output large changes of a signal luminance, such as
100% white video signal and black signal. Thus, output signal exceed dynamic range of Vout pin and may be the
signal lack.
Input signal
Waveform of Vout
The sync signal is missing because exceed the
dynamic range of Vout.
Dynamic range of Vout
Waveform of Vout1
< Countermeasure for waveform distortion >
1. Please using small value the Sag compensation capacitor (VSAG).
It can ensure the dynamic range by using small value the capacitor (VSAG). It because of low-frequency
variation of Vout pin is smaller. However, the output (VOUT) must be use large capacitor for this reason sag
characteristics become exacerbated.
2. Please do not use the sag correction circuit.
Signal can output within dynamic range for reason it does not change the DC level of the output terminal.
However, the output (VOUT) must be use large capacitor for this reason sag characteristics become
exacerbated.
Ver.9
-9-
NJM2573
< Dual drive at using SAG correction circuit >
Using sag correction circuit at dual drive circuit is below. Dual drives are less load resistance. Thus, the cut-off
frequency of HPF that is composed of the output capacitor and load resistance will be small. Therefore, the sag
characteristics deteriorate.
Please size up to the output capacitor (Vout) for not to deteriorate the sag characteristics.
< Dual drive at not using SAG correction circuit >
We recommended two-example dual drive circuit with not use sag correction circuit. Please change the
configuration to be used according to the situation. Please configure to meet the following conditions. Then you can
adjust the characteristics of each configuration.
Cout  Cout 1  Cout 2
Cout 1  Cout 2
(A) In case of using one output capacitor
(B) In case of using two output capacitors
Ver.9
- 10 -
NJM2573
Csag=33uF
Cout=330uF
Cout=220uF
Cout=100uF
Cout=47uF
Cout=33uF
< Using SAG correction circuit >
Input signal: bounce signal (IRE0%, IRE100%, 30Hz), resistance=150
Waveform: yellow: input signal, green: Vout signal, purple: Vout1signal
Csag=10uF
Csag=22uF
Ver.9
- 11 -
NJM2573
Csag=33uF
Cout=1000uF
Cout=470uF
Cout=330uF
Cout=220uF
Cout=100uF
Input signal: bounce signal (IRE0%, IRE100%, 30Hz), resistance=75
Waveform: yellow: input signal, green: Vout signal, purple: Vout1signal
Csag=10uF
Csag=22uF
Ver.9
- 12 -
NJM2573
Cout=1000uF
Cout=470uF
Cout=330uF
Cout=220uF
Cout=100uF
< Not using SAG correction circuit >
Input signal: bounce signal (IRE0%, IRE100%, 30Hz), resistance=150
Waveform: yellow: input signal, green: Vout signal, purple: Vout1signal
RL=75
RL=150
Ver.9
- 13 -
NJM2573
Csag=33uF
Cout=330uF
Cout=220uF
Cout=100uF
Cout=47uF
Cout=33uF
< Using SAG correction circuit >
Input signal: Black to White100%, resistance150
Waveform: yellow: input signal, green: Vout signal, purple: Vout1signal
Csag=10uF
Csag=22uF
Ver.9
- 14 -
NJM2573
Csag=33uF
Cout=330uF
Cout=220uF
Cout=100uF
Cout=47uF
Cout=33uF
Input signal: White100% to Black, resistance150
Waveform: yellow: input signal, green: Vout signal, purple: Vout1signal
Csag=10uF
Csag=22uF
Ver.9
- 15 -
NJM2573
Csag=33uF
Cout=330uF
Cout=220uF
Cout=100uF
Cout=47uF
Cout=33uF
< Using SAG correction circuit >
Input signal: Black to White100%, resistance=75
Waveform: yellow: input signal, green: Vout signal, purple: Vout1signal
Csag=10uF
Csag=22uF
Ver.9
- 16 -
NJM2573
Csag=33uF
Cout=330uF
Cout=220uF
Cout=100uF
Cout=47uF
Cout=33uF
Input signal: White100% to Black, resistance=75
Waveform: yellow: input signal, green: Vout signal, purple: Vout1signal
Csag=10uF
Csag=22uF
Ver.9
- 17 -
NJM2573
Clamp circuit
1. Operation of Sync-tip-clamp
Input circuit will be explained. Sync-tip clamp circuit (below the clamp circuit) operates to keep a sync tip of the
minimum potential of the video signal. Clamp circuit is a circuit of the capacitor charging and discharging of the
external input Cin. It is charged to the capacitor to the external input Cin at sync tip of the video signal. Therefore,
the potential of the sync tip is fixed.
And it is discharged charge by capacitor Cin at period other than the video signal sync tip. This is due to a
small discharge current to the IC.
In this way, this clamp circuit is fixed sync tip of video signal to a constant potential from charging of Cin and
discharging of Cin at every one horizontal period of the video signal.
The minute current be discharged an electrical charge from the input capacitor at the period other than the
sync tip of video signals. Decrease of voltage on discharge is dependent on the size of the input capacitor Cin.
If you decrease the value of the input capacitor, will cause distortion, called the H sag. Therefore, the input
capacitor recommend on more than 0.1uF.
signal input
Cin
charge
current
Vin
Clamp circuit
diccharge
current
< Clamp circuit >
A. Cin is large
B. Cin is small (H sag experience)
clamp potential
clamp potential
charge period
discharge period
charge period
charge period
discharge period
charge period
< Waveform of input terminal >
2. Input impedance
The input impedance of the clamp circuit is different at the capacitor discharge period and the charge period.
The input impedance of the charging period is a few k. On the other hand, the input impedance of the
discharge period is several M. Because is a small discharge-current through to the IC.
Thus the input impedance will vary depending on the operating state of the clamp circuit.
3. Impedance of signal source
Source impedance to the input terminal, please lower than 200. A high source impedance, the signal may be
distorted. If so, please to connect a buffer for impedance conversion.
Ver.9
- 18 -
NJM2573
TYPICAL CHARACTERISTICS
Voltage Gain vs. Frequency
Vin=1.0Vpp
+
V vs Icc
32
10
30
0.0
28
26
Gv[dB]
Icc[mA]
-10
-20
24
22
20
1ch
2ch_clamp
2ch_bias
3ch
-30
18
16
-40
10
5
10
6
10
7
10
8
2
3
4
5
6
7
8
+
Frequency[Hz]
V [V]
+
+
V vs Isave
V vs Vomc
300
8
Vom2B
Vom3
7
250
6
Vomc[Vpp]
Isave[uA]
200
150
100
5
4
3
2
50
1
0
2
3
4
5
6
7
0
8
2
+
3
4
5
V [V]
V [V]
V vs Vomv
V vs Gv
6
7
8
+
+
+
8
8
Gv1
Gv2C
Gv2B
Gv3
7
7.5
6
Gv[dB]
Vomv[Vpp]
7
5
4
6.5
3
6
2
5.5
1
Vom1
Vom2C
0
5
2
3
4
5
+
V [V]
6
7
8
2
3
4
5
6
7
8
+
V [V]
Ver.9
- 19 -
NJM2573
+
+
V vs Gfy
V vs Gfy
4.5M
8M
2
2
Gf4.5_1
Gf4.5_2C
Gf4.5_2B
Gf4.5_3
1.5
1
0
Gfy [dB]
Gfy
4.5M
0
8M
[dB]
-2
0.5
-4
-0.5
-6
Gf8_1
Gf8_2C
Gf8_2B
Gf8_3
-1
-8
-1.5
-2
-10
2
3
4
5
6
7
8
2
3
4
5
+
6
7
8
+
V [V]
V [V]
+
+
V vs Gfy
V vs DG
16M
0
5
-5
DG1
DG2C
4
-10
DG[%]
-15
Gfy
16M
[dB]
3
2
Gf16_1
Gf16_2C
Gf16_2B
Gf16_3
-20
1
-25
0
-30
2
3
4
5
6
7
2
8
3
4
5
6
7
8
6
7
8
+
+
V [V]
V [V]
V vs DP
V vs CTave
+
+
5
-40
DP1
DP2C
4
-50
CTave[dB]
DP[deg]
-60
3
2
-70
-80
1
-90
-100
0
2
3
4
5
+
V [V]
- 20 -
6
7
8
2
3
4
5
+
V [V]
Ver.9
NJM2573
+
+
V vs SNv
V vs Hv
-20
100
-30
90
-40
80
Hv[dB]
SNv[dB]
-50
70
-70
SN1
SN2C
SN2B
SN3
60
-60
Hv1
Hv2C
Hv2B
Hv3
-80
50
-90
-100
40
2
3
4
5
6
7
2
8
3
4
6
V [V]
V [V]
V vs VthHL
T vs Icc
+
7
8
32
3
VthPSH
VthPSL
VthC/BH
VthC/BL
2.5
30
28
2
26
Icc[mA]
VthHL[V]
5
+
+
1.5
24
22
1
20
18
0.5
16
0
2
3
4
5
6
7
-60
8
-40
-20
0
20
40
60
80
100
120
o
+
T [ C]
V [V]
T vs Isave
T vs Vomc
100
8
Vom2B
Vom3
7
80
60
Vomc[Vpp]
Isave[uA]
6
40
5
4
3
2
20
1
0
-60
-40
-20
0
20
40
o
T [ C]
60
80
100
120
0
-60
-40
-20
0
20
40
60
80
100
120
T [oC]
Ver.9
- 21 -
NJM2573
T vs Gv
T vs Vomv
8
8
Vom1
Vom2C
7
Gv1
Gv2C
Gv2B
Gv3
7.5
6
7
Gv[dB]
Vomv[Vpp]
5
4
6.5
3
6
2
5.5
1
0
-60
-40
-20
0
20
40
60
80
100
5
120
-60
o
T [ C]
-40
-20
0
20
40
60
80
100
120
T [o C]
T vs Gfy
T vs Gfy
4.5M
8M
2
2
Gf4.5_1
Gf4.5_2C
Gf4.5_2B
Gf4.5_3
1.5
1
0
Gfy [dB]
Gfy
0
-4
8M
4.5M
[dB]
-2
0.5
-0.5
-6
Gf8_1
Gf8_2C
Gf8_2B
Gf8_3
-1
-8
-1.5
-2
-10
-60
-40
-20
0
20
40
60
80
100
120
-60
-40
-20
0
20
40
60
80
100
120
o
o
T [ C]
T [ C]
T vs Gfy
T vs DG
16M
0
5
-5
DG1
DG2C
4
-10
DG[%]
-15
Gfy
16M
[dB]
3
2
Gf16_1
Gf16_2C
Gf16_2B
Gf16_3
-20
1
-25
-30
-60
-40
-20
0
20
40
o
T [ C]
60
80
100
120
0
-60
-40
-20
0
20
40
60
80
100
120
T [oC]
Ver.9
- 22 -
NJM2573
T vs DP
T vs CTave
5
-40
DP1
DP2C
4
-50
CTave[dB]
DP[deg]
-60
3
2
-70
-80
1
-90
0
-60
-100
-40
-20
0
20
40
60
80
100
-60
120
-40
-20
0
20
40
60
80
100
120
o
o
T [ C]
T [ C]
T vs SNv
T vs Hv
100
-20
-30
90
-40
80
Hv[dB]
SNv[dB]
-50
70
-70
SN1
SN2C
SN2B
SN3
60
Hv1
Hv2C
Hv2B
Hv3
-60
-80
50
-90
40
-100
-60
-40
-20
0
20
40
60
80
100
120
o
-60
-40
-20
0
20
40
60
80
100
120
T [oC]
T [ C]
T vs VthHL
3
VthPSH
VthPSL
VthC/BH
VthC/BL
2.5
VthHL[V]
2
1.5
1
0.5
0
-60
-40
-20
0
20
40
T [oC]
60
80
100
120
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.9
- 23 -