P4C174 HIGH SPEED 8K X 8 CACHE TAGE STATIC RAM FEATURES High Speed Address-To-Match - 8 ns Maximum Access Time Data Retention at 2V for Battery Backup Operation High-Speed Read-Access Time Advanced CMOS Technology – 8/10/12/15/20/25 ns (Commercial) – 15/20/25 ns (Military) Open Drain MATCH Output Reset Function 8-Bit Tag Comparison Logic Automatic Powerdown During Long Cycles Low Power Operation Package Styles Available — 28 Pin 300 mil DIP — 28 Pin 300 mil Plastic SOJ Single Power Supply — 5V±10% DESCRIPTION The P4C174 is a 65,536 bit high speed cache tag static RAM organized as 8K x 8. The CMOS memory has equal access and cycle times. Inputs are fully TTL-compatible. The cache tag RAMs operate from a single 5V±10% power supply. An 8-bit data comparator with a MATCH output is included for use as an address tag comparator in high speed cache applications. The reset function provides the capability to reset all memory locations to a LOW level. The MATCH output of the P4C174 reflects the comparison result between the 8-bit data on the I/O pins and Functional Block Diagram the addressed memory location. 8K Cache lines can be mapped into 1M-Byte address spaces by comparing 20 address bits organized as 13-line address bits and 7-page address bits. Low power operation of the P4C174 is enhanced by automatic powerdown when the memory is deselected or during long cycle times. Also, data retention is maintained down to VCC = 2.0. Typical battery backup applications consume only 30 µW at VCC = 3.0V. Pin Configuration DIP (C5, P5), SOJ (J5) Document # SRAM118 REV 4 Revised November 2014 P4C174 - HIGH SPEED 8K X 8 CACHE TAG STATIC RAM Maximum Ratings(1) Sym RECOMMENDED OPERATING CONDITIONS Parameter Value Unit V Grade(2) Ambient Temp GND VCC 0°C to 70°C 0V 5.0V ± 10% -55°C to +125°C 0V 5.0V ± 10% VCC Power Supply Pin with Respect to GND -0.5 to +7 VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 to VCC + 0.5 V TA Operating Temperature -55 to +125 °C TBIAS Temperature Under Bias -55 to +125 °C Sym Parameter TSTG Storage Temperature -65 to +150 °C CIN Input Capacitance COUT Output Capacitance Commercial Military PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Conditions Typ Unit VIN = 0V 5 pF VOUT = 0V 7 pF DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Sym Parameter P4C174 Test Conditions Min Max Unit VIH Input High Voltage 2.2 VCC + 0.5 V VIL Input Low Voltage -0.5(3) 0.8 V VHC CMOS Input High Voltage VCC - 0.2 VCC + 0.5 V VLC CMOS Input Low Voltage -0.5(3) 0.2 V VCD Input Clamp Diode Voltage VCC = Min, IIN = -18 mA -1.2 V VOL Output Low Voltage (TTL Load) IOL = +8 mA, VCC = Min 0.4 V VOH Output High Voltage (TTL Load) IOH = -4 mA, VCC = Min Input Leakage Current VCC = Max, VIN = GND to VCC ILI ILO Output Leakage Current ISB1 Standby Power Supply Current (CMOS Input Levels) MILITARY -10 V +10 µA -5 +5 -10 +10 COMMERCIAL -5 +5 MILITARY — 25 COMMERCIAL — 5 COMMERCIAL VCC = Max, CE = VIH, VOUT = GND to VCC CE ≥ VHC, VCC = Max, f = 0, MILITARY µA Outputs Open mA VIN ≤ VLC or VIN ≥ VHC Notes: 1)Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Maximum rating conditions for extended periods may affect reliability. Document # SRAM118 REV 4 2.4 2)Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3)Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4)This parameter is sampled and not 100% tested. Page 2 P4C174 - HIGH SPEED 8K X 8 CACHE TAG STATIC RAM DATA RETENTION CHARACTERISTICS (P4C174 Military Temperature Only) Sym Parameter Test Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR† Min Typ* VCC= 2.0V 3.0V Max VCC= 2.0V 3.0V 2.0 VIN ≥ VCC -0.2V or VIN ≤ 0.2V Operation Recovery Time V 10 CE ≥ VCC -0.2V, Unit 15 600 900 µA 0 ns tRC§ ns * TA = +25°C § tRC = Read Cycle Time † This Parameter is guaranteed but not tested DATA RETENTION WAVEFORM POWER DISSIPATION CHARACTERISTICS VS. SPEED Sym Parameter Temperature Range Commercial ICC -8 -10 -12 200 180 170 -15 -20 -25 Unit 155 150 mA 160 155 mA Dynamic Operating Current* Military 170 * VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH. Document # SRAM118 REV 4 Page 3 P4C174 - HIGH SPEED 8K X 8 CACHE TAG STATIC RAM AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym -8 Parameter Min -10 Max Min -12 Max Min -15 Max Min -20 Max Min -25 Max Min Max Unit tRC Read Cycle Time tAA Address Access Time tOH Address Change to Output Change tAC Chip Enable LOW to Output Valid tLZ Chip Enable LOW to Output LOW-Z(5) tHZ Chip Enable HIGH to Output HIGHZ(5) 5 5 5 8 8 10 ns tOE Output Enable LOW to Output Valid 5 6 6 8 10 12 ns tOLZ Output Enable LOW to Output LOWZ(5) tOHZ Output Enable HIGH to Output HIGHZ(5) tPU Chip Enable LOW or Address Change to Powerup tPUPD 8 10 8 12 10 3 3 8 3 3 0 5 0 0 20 5 20 20 25 20 3 25 8 0 ns 10 0 20 20 ns ns 0 5 ns ns 3 0 0 ns 3 15 0 0 20 3 3 0 25 15 12 5 20 3 3 0 Powerup to Powerdown 12 10 3 15 ns ns 25 ns TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(6,7) tRC(8) ADDRESS tAA OE tOE tOLZ CE tOH (5) tOHZ(5) tAC tLZ(5) tHZ (5) DATA OUT TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(6) tRC(8) ADDRESS tOH DATA OUT PREVIOUS DATA VALID Document # SRAM118 REV 4 tAA DATA VALID Page 4 P4C174 - HIGH SPEED 8K X 8 CACHE TAG STATIC RAM TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(2,3) tRC(8) CE tAC tLZ tHZ(5) (5) DATA VALID DATA OUT tPU tPUPD HIGH IMPEDANCE VCC SUPPLY CURRENT(5) Notes: 5) Transition is measured ±200 mV from steady state voltage with Output Load B. This parameter is sampled, not 100% tested. 6) CE is LOW, OE is LOW, WE is HIGH for READ cycle. CE or WE must be HIGH during address transitions. 7) All address lines are valid no later than the transition of CE to LOW. 8) READ cycle time is measured from the last valid address to the first transitioning address. 9) Powerup occurs as a result of any of the following conditions: a) Falling edge of CE. b) Falling edge of WE (CE active). c) Any address line transition (CE active). d) Any Data line transition (CE and WE active). This device automatically powers down after TPUPD has elapsed from any of the prior conditions. Power dissipation is therefore a function of cycle rate, not CE pulse width. Document # SRAM118 REV 4 10) CE is LOW, WE is LOW for WRITE cycle. CE or WE must be HIGH during address transitions. 11) WRITE cycle time is measured from the last valid address to the first transitioning address. 12) OE is LOW for this WRITE cycle to show TWZ and TOW. Page 5 P4C174 - HIGH SPEED 8K X 8 CACHE TAG STATIC RAM AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, 0°C to +70°C) -8 Sym Parameter Min -10 Max Min -12 Max Min -15 Max Min -20 Max Min -25 Max Min Max Unit tWC Write Cycle Time 8 10 12 15 20 20 ns tCW Chip Enable LOW to End of Write 7 9 10 12 15 15 ns tAS Address Valid to Beginning of Write 0 0 0 0 0 0 ns tAW Address Valid to End of Write 7 9 10 12 15 15 ns tAH End of Write to Address Change 0 0 0 0 0 0 ns tWP Write Pulse Width 7 9 10 12 15 15 ns tDW Data Valid to End of Write 6 6 6 7 10 10 ns tDH End of Write to Data Change 0 0 0 0 0 0 ns tOW Write Enable HIGH to Output LOW-Z(5) 0 0 0 0 0 0 ns tWZ Write Enable LOW to Output HIGH-Z(5) 4 4 4 5 7 7 ns TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(10) tWC(11) ADDRESS tCW CE tAW tWP tAH WE tAS tDW tDH DATA VALID DATA IN tWZ(5) DATA OUT(12) tOW(5) DATA UNDEFINED HIGH IMPEDANCE Timing Waveform of Write Cycle No. 2 (CE Controlled)(10) tWC(11) ADDRESS tAS tCW CE tAH tAW WE tWP tDW DATA IN DATA OUT Document # SRAM118 REV 4 tDH DATA VALID HIGH IMPEDANCE Page 6 P4C174 - HIGH SPEED 8K X 8 CACHE TAG STATIC RAM AC CHARACTERISTICS—MATCH CYCLE (VCC = 5V ± 10%, 0°C to +70°C) Sym Parameter -8 Min -10 Max 8 Min -12 Max 10 Min -15 Max 12 Min -20 Max Max Min tADM Address Valid to MATCH Valid tADMH Address Change to MATCH Change tCEM Chip Enable LOW to MATCH Valid 7 8 8 10 10 15 ns tCEMHI Chip Enable HIGH to MATCH HIGH 7 8 8 10 10 15 ns tOEMHI Output Enable LOW to MATCH HIGH 7 9 10 12 15 20 ns tWEMHI Write Enable LOW to MATCH HIGH 7 9 10 12 15 20 ns tDAM Data Valid to MATCH Valid 7 9 10 13 15 15 ns tDAMH Data Change to MATCH Change 3 3 0 12 3 0 15 3 0 0 25 Unit Match Cycle Time 10 20 Max tMC 8 15 Min -25 ns 20 25 3 3 0 ns ns 0 ns MATCH TIMING tMC tADMH ADDRESS tADM CE tCEM tCEMHI OE tOEMHI WE tWEMHI RESET tRMHI DATA VALID READ DATA OUT VALID MATCH DATA IN tDAM MATCH MATCH tDAMH MATCH VALID NO MATCH Document # SRAM118 REV 4 Page 7 P4C174 - HIGH SPEED 8K X 8 CACHE TAG STATIC RAM AC CHARACTERISTICS—RESET CYCLE (VCC = 5V ± 10%, 0°C to +70°C) -8 -10 -12 -15 -20 -25 Sym Parameter tRRC Reset Cycle Time 35 40 45 50 50 60 ns tRP Reset Pulse Width 8 10 12 12 15 15 ns tRPU Reset LOW to Powerup 0 0 0 0 0 0 ns tRPD Reset LOW to Powerdown tRMHI Reset LOW to MATCH HIGH 0 tRIX Reset LOW to Inputs Ignored 0 tRIR Reset LOW to Inputs Recognized tPUR Powerup to RESET LOW Min Max Min 35 8 Min 40 0 10 0 35 8 Max Max 45 0 10 0 40 10 Min Min 50 0 12 0 45 12 Max Min 50 0 15 0 50 15 Max 0 Unit 60 ns 20 ns 0 50 20 Max ns 60 25 ns ns RESET TIMING tPUR VCC POWERUP 4.5V tRRC tRP RESET INPUTS (A, D, CE, OE, WE) tRIR tRIx NExT CYCLE PRIOR CYCLE VCC SUPPLY CURRENT tRPD tRPU tRMHI MATCH Document # SRAM118 REV 4 Page 8 P4C174 - HIGH SPEED 8K X 8 CACHE TAG STATIC RAM AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise and Fall Times < 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2 TRUTH TABLE (X = don't care; L = VIL; H = VIH) WE CE OE CLEAR MATCH I/O Function X X X L H — Reset All Bits To Low X H X H H High-Z H L H H L DIN No MATCH H L H H H DIN MATCH H L L H H DOUT Memory Read L L X H H DIN Memory Write Document # SRAM118 REV 4 Deselect Chip Page 9 P4C174 - HIGH SPEED 8K X 8 CACHE TAG STATIC RAM OUTPUT LOAD A OUTPUT LOAD B OUTPUT LOAD C ORDERING INFORMATION Document # SRAM118 REV 4 Page 10 P4C174 - HIGH SPEED 8K X 8 CACHE TAG STATIC RAM SIDEBRAZED DUAL IN-LINE PACKAGE C5 Pkg # # Pins 28 (300 mil) Symbol Min Max A - 0.225 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 1.485 E 0.240 0.310 eA 0.300 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.070 S1 0.005 - S2 0.005 - SOJ SMALL OUTLINE IC PACKAGE Pkg # J5 # Pins 28 (300 mil) Symbol Min Max A 0.120 0.148 A1 0.078 - b 0.014 0.020 C 0.007 0.011 D 0.700 0.730 e 0.050 BSC E 0.292 0.300 E1 0.335 0.347 E2 0.262 0.272 Q 0.025 - Document # SRAM118 REV 4 Page 11 P4C174 - HIGH SPEED 8K X 8 CACHE TAG STATIC RAM PLASTIC DUAL IN-LINE PACKAGE P5 Pkg # # Pins 28 (300 mil) Symbol Min Max A - 0.210 A1 - b 0.014 0.023 b2 0.045 0.070 C 0.008 0.014 D 1.345 1.400 E1 0.270 0.300 E 0.300 0.380 e 0.100 BSC eB - 0.430 L 0.115 0.150 α 0° 15° Document # SRAM118 REV 4 Page 12 P4C174 - HIGH SPEED 8K X 8 CACHE TAG STATIC RAM REVISIONS DOCUMENT NUMBER SRAM 118 DOCUMENT TITLE P4C174 HIGH SPEED 8Kx8 CACHE TAG STATIC RAM REV ISSUE DATE ORIGINATOR OR 1997 DAB New Data Sheet A Oct-2005 JDB Changed logo to Pyramid B Nov-2005 JDB Corrected error in Selection Guide C Aug-2006 JDB Updated SOJ package information 4 Nov-2014 JDB Updated Truth Table; new Datasheet formatting Document # SRAM118 REV 4 DESCRIPTION OF CHANGE Page 13