P4C116/P4C116L ULTRA HIGH SPEED 2K x 8 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Common Data I/O High Speed (Equal Access and Cycle Times) – 10/12/15/20/25/35 ns (Commercial) – 12/15/20/25/35 ns (Industrial) – 15/20/25/35 ns (Military) Fully TTL Compatible Inputs and Outputs Low Power Operation Output Enable Control Function Single 5V±10% Power Supply Produced with PACE II TechnologyTM Standard Pinout (JEDEC Approved) – 24-Pin 300 mil DIP, SOIC, SOJ – 24-Pin 600 mil DIP – 24-Pin Solder Seal Flat Pack – 24-Pin Rectangular LCC (300 x 400 mils) – 28-Pin Square LCC (450 x 450 mils) – 32-Pin Rectangular LCC (450 x 550 mils) – 40-Pin Square LCC (480 x 480 mils) DESCRIPTION The P4C116/P4C116L are 16,384-bit ultra high-speed static RAMs organized as 2K x 8. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V±10% tolerance power supply. Current drain is typically 10 µA from a 2.0V supply. permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption. The P4C116 is available in 24-pin 300 and 600 mil DIP, SOJ and SOIC packages, a solder seal flatpack and 4 different LCC packages (24, 28, 32, and 40 pin). Access times as fast as 10 nanoseconds are available, Functional Block Diagram Pin ConfigurationS DIP (C4, C12, D4, P4), SOJ (J4), SOIC (S4) SOLDER SEAL FLAT PACK (FS-1) SIMILAR LCC configurations at end of datasheet Document # SRAM110 REV C Revised May 2009 P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS Maximum Ratings(1) Sym Parameter RECOMMENDED OPERATING CONDITIONS Value Unit V Grade(2) Ambient Temp GND VCC 0°C to 70°C 0V 5.0V ± 10% Industrial -40°C to +85°C 0V 5.0V ± 10% Military -55°C to +125°C 0V 5.0V ± 10% VCC Power Supply Pin with Respect to GND -0.5 to +7 VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 to VCC + 0.5 V TA Operating Temperature -55 to +125 °C TBIAS Temperature Under Bias -55 to +125 °C TSTG Storage Temperature -65 to +150 °C Sym Parameter Commercial CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) PT Power Dissipation 1.0 W CIN Input Capacitance IOUT DC Output Current 50 mA COUT Output Capacitance Conditions Typ Unit VIN=0V 5 pF VOUT=0V 7 pF DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Sym Parameter P4C116 Test Conditions P4C116L Unit Min Max Min Max VCC + 0.5 2.2 VCC + 0.5 V 0.8 V VCC + 0.5 V 0.2 V VIH Input High Voltage 2.2 VIL Input Low Voltage -0.5 VHC CMOS Input High Voltage VLC CMOS Input Low Voltage VCD Input Clamp Diode Voltage VCC = Min, IIN = -18 mA -1.2 -1.2 V VOL Output Low Voltage (TTL Load) IOL = +8 mA, VCC = Min 0.4 0.4 V VOH Output High Voltage (TTL Load) IOH = - 4 mA, VCC = Min ILI Input Leakage Current VCC = Max, VIN = GND to VCC ILO Output Leakage Current ISB Standby Power Supply Current (TTL Input Levels) ISB1 Standby Power Supply Current (CMOS Input Levels) (3) VCC - 0.2 -0.5 VCC = Max, CE = VIH, VOUT = GND to VCC CE ≥ VIH, VCC = Max, f = Max, Outputs Open CE ≥ VHC, VCC = Max, f = 0, (3) 0.8 VCC + 0.5 0.2 2.4 -0.5 (3) VCC - 0.2 -0.5 (3) 2.4 V -10 +10 -5 +5 -5 +5 N/A N/A -10 +10 -5 +5 IND/COM -5 +5 N/A N/A MIL — 30 — 20 MIL µA IND/COM MIL µA mA IND/COM — 20 — N/A MIL — 15 — 1 Outputs Open VIN ≤ VLC or VIN ≥ VHC mA IND/COM — 10 — N/A N/A = Not applicable Document # SRAM110 REV C Page 2 P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS DATA RETENTION CHARACTERISTICS (P4C116L Military Temperature Only) Sym Parameter Test Conditions Min Typ* VCC= 2.0V Max VCC= 3.0V 2.0V Unit 3.0V VDR VCC for Data Retention 2.0 V ICCDR Data Retention Current CE ≥ VCC -0.2V, tCDR Chip Deselect to Data Retention Time VIN ≥ VCC -0.2V 0 ns tR† Operation Recovery Time or VIN ≤ 0.2V tRC§ ns 10 15 600 900 µA * TA = +25°C § tRC = Read Cycle Time † This Parameter is guaranteed but not tested DATA RETENTION WAVEFORM POWER DISSIPATION CHARACTERISTICS VS. SPEED Sym ICC Parameter Dynamic Operating Current* Temperature Range -10 -12 -15 -20 -25 -35 Unit Commercial 180 170 160 155 150 140 mA Industrial N/A 180 170 160 155 150 mA Military N/A N/A 170 160 155 150 mA * VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH. AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym Parameter -10 Min -12 Max Max 12 Min -20 Max Max Max Max 10 12 15 20 25 35 ns tAC Chip Enable Access Time 10 12 15 20 25 35 ns tOH Output Hold from Address Change 2 2 2 2 2 2 ns tLZ Chip Enable to Output in Low Z 2 2 2 2 3 3 ns tHZ Chip Disable to Output in High Z 5 6 7 8 10 15 ns tOE Output Enable Low to Data Valid 6 8 10 10 15 20 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down 6 0 7 0 10 0 8 0 12 0 9 0 15 35 Unit Address Access Time 0 25 Min tAA 0 20 Min -35 Read Cycle Time 0 15 Min -25 tRC Document # SRAM110 REV C 10 Min -15 0 12 0 20 ns ns 15 0 20 ns ns 25 ns Page 3 P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5) TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED) Notes: 1.Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Maximum rating conditions for extended periods may affect reliability. 2.Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3.Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. Document # SRAM110 REV C 4.This parameter is sampled and not 100% tested. 5.WE is HIGH for READ cycle. 6.CE is LOW and OE is LOW for READ cycle. 7.ADDRESS must be valid prior to, or coincident with CE transition LOW. 8.Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9.Read Cycle Time is measured from the last valid address to the first transitioning address. Page 4 P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym Parameter -10 Min -12 Max Min -15 Max Min -20 Max Min -25 Max Min -35 Max Min Max Unit tWC Write Cycle Time 10 12 15 20 25 35 ns tCW Chip Enable Time to End of Write 8 10 12 15 18 25 ns tAW Address Valid to End of Write 8 10 12 15 18 25 ns tAS Address Setup Time 0 0 0 0 0 0 ns tWP Write Pulse Width 8 10 12 15 18 20 ns tAH Address Hold Time 0 0 0 0 0 0 ns tDW Data Valid to End of Write 7 8 10 12 15 20 ns tDH Data Hold Time 0 0 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 6 0 7 0 8 0 10 0 15 0 15 0 ns ns TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(10,11) Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show tWZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state Document # SRAM110 REV C 13. Write Cycle Time is measured from the last valid address to the first transitioning address. Page 5 P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS Timing Waveform of Write Cycle No. 2 (CE Controlled)(10) AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2 Mode CE OE WE I/O Power Standby H X X High Z Standby DOUT Disabled L H H High Z Active Read L L H DOUT Active Write L X L High Z Active Figure 1. Output Load Figure 2. Thevenin Equivalent Note: Because of the ultra-high speed of the P4C116/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). * including scope and test fixture. Document # SRAM110 REV C Page 6 P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS LCC PIN CONFIGURATIONS 24-Pin LCC (L8) 28-Pin LCC (L5-1) 32-Pin LCC (L6) 40-Pin LCC (L10) Document # SRAM110 REV C Page 7 P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS ORDERING INFORMATION Document # SRAM110 REV C Page 8 P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS SIDEBRAZED DUAL IN-LINE PACKAGE C4 Pkg # # Pins 24 (300 mil) Symbol Min Max A - 0.200 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 1.280 E 0.220 0.310 eA 0.300 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.060 S1 0.005 - S2 0.005 - SIDEBRAZED DUAL IN-LINE PACKAGE Pkg # C12 # Pins 24 (600 mil) Symbol Min Max A - 0.232 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 1.290 E 0.500 0.610 eA 0.600 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.060 S1 0.005 - S2 0.005 - Document # SRAM110 REV C Page 9 P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS CERDIP DUAL INLINE PACKAGE D4 Pkg # # Pins 24 (300 mil) Symbol Min Max A - 0.200 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 1.280 E 0.220 0.310 eA 0.300 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.060 S1 0.005 - S2 0° 15° Pkg # FS-1 # Pins 24 SOLDER SEAL FLATPACK Symbol Min Max A 0.045 0.115 b 0.015 0.022 b1 0.015 0.019 c 0.004 0.009 c1 0.004 0.006 D - 0.640 E 0.350 0.420 E1 - 0.450 E2 0.180 - E3 0.030 - e 0.050 BSC k 0.008 0.015 L 0.250 0.370 Q 0.026 0.045 S1 0.000 - M - 0.002 N 24 Document # SRAM110 REV C Page 10 P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS SOJ SMALL OUTLINE IC PACKAGE J4 Pkg # # Pins 24 (300 mil) Symbol Min Max A 0.128 0.148 A1 0.082 - b 0.016 0.020 C 0.007 0.010 D 0.620 0.630 e 0.050 BSC E 0.335 BSC E1 E2 Q 0.292 0.300 0.267 BSC 0.025 - Pkg # L5-1 # Pins 28 SQUARE LEADLESS CHIP CARRIER Symbol Min Max A 0.060 0.075 A1 0.050 0.065 B1 0.022 0.028 D/E 0.442 0.460 D1/E1 0.300 BSC D2/E2 0.150 BSC D3/E3 - 0.460 e 0.050 BSC h 0.040 REF j 0.020 REF L 0.045 0.055 L1 0.045 0.055 L2 0.075 0.095 ND 7 NE 7 Document # SRAM110 REV C Page 11 P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS Pkg # L10 # Pins 40 SQUARE LEADLESS CHIP CARRIER Symbol Min Max A 0.060 0.080 A1 0.050 0.075 B1 0.015 0.025 D/E 0.475 0.492 D1/E1 0.360 BSC D2/E2 0.180 BSC D3/E3 - 0.492 e 0.040 BSC h R = .0075 j 0.026 REF L 0.030 0.050 L1 0.030 0.050 L2 0.080 0.090 ND 10 NE 10 Pkg # L6 # Pins 32 RECTANGULAR LEADLESS CHIP CARRIER Symbol Min Max A 0.060 0.075 A1 0.050 0.065 B1 0.022 0.028 D 0.442 0.458 D1 0.300 BSC D2 0.150 BSC D3 - 0.458 E 0.540 0.560 E1 0.400 BSC E2 0.200 BSC E3 - 0.558 e 0.050 BSC h 0.040 REF j 0.020 REF L 0.045 0.055 L1 0.045 0.055 L2 0.075 0.095 ND 7 NE 9 Document # SRAM110 REV C Page 12 P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS Pkg # L8 # Pins 24 RECTANGULAR LEADLESS CHIP CARRIER Symbol Min Max A 0.064 0.076 A1 0.054 0.066 B1 0.022 0.028 D 0.292 0.308 D1 0.200 BSC D2 0.100 BSC D3 - 0.308 E 0.392 0.408 E1 0.300 BSC E2 0.150 BSC E3 - 0.408 e 0.050 BSC h 0.025 REF j 0.015 REF L 0.040 0.050 L1 0.040 0.050 L2 0.077 0.093 ND 5 NE 7 Pkg # P4 PLASTIC DUAL IN-LINE PACKAGE # Pins 24 (300 Mil) Symbol Min Max A - 0.210 A1 0.015 - b 0.014 0.022 b2 0.045 0.070 C 0.008 0.014 D 1.230 1.280 E1 0.240 0.280 E 0.280 0.325 e 0.100 BSC eB - 0.430 L 0.115 0.160 α 0° 15° Document # SRAM110 REV C Page 13 P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS SOIC/SOP SMALL OUTLINE IC PACKAGE Pkg # S4 # Pins 24 (300 Mil) Symbol Min Max A 0.093 0.104 A1 0.004 0.012 b2 0.013 0.020 C 0.009 0.012 D 0.598 0.614 e 0.050 BSC E 0.291 0.299 H 0.394 0.419 h 0.010 0.029 L 0.016 0.050 α 0° 8° Document # SRAM110 REV C Page 14 P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS REVISIONS DOCUMENT NUMBER SRAM 110 DOCUMENT TITLE P4C116 / P4C116L ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS REV ISSUE DATE ORIGINATOR OR 1997 DAB New Data Sheet A Oct-2005 JDB Changed logo to Pyramid B Feb-2009 JDB Added Industrial Temperature Range C May-2009 JDB Added 300 mil CERDIP and 600 mil sidebrazed packages Document # SRAM110 REV C DESCRIPTION OF CHANGE Page 15