Multi-Octave Practical Power Amplifier Realization using GaN on SiC WMG: Broadband PAs for Wireless Communications D. Runton, T. Driver, K. Krishnamurthy, M. LeFevre, K. Shallal Agenda • Motivation • RFMD GaN Technology • PA Design Topology Overview • PA Design Methodologies • Design Examples • Summary Motivation Milcom and Public Mobile Radio Amplifiers PMR Portable Radio Market Drivers • • • • Improved battery life / reliability Multi-standards for inter-operability Wide-band architecture Leverage COTS components Why GaN? JTRS Radio • Higher efficiency – Reduce heatsink requirements, smaller size – Increase battery life • Wide bandwidth – Replace 3 or more amplifiers with 1 amplifier Power Frequency Limit Property Si GaAs GaN Eg (eV) 1.1 1.4 3.4 vs (10 7 cm/s) 0.7 0.8 2.5 Pmax Eg4 v 2s F2 Power Bandwidth Limit • High power density (V, I) enables high impedance • Low pF/W enables broadband Wideband HPA’s covering multiple communication bands LDMOS LDMOS LDMOS Fhigh Flow Fo QL ln() Transistor Parameters 2500 2.2 mm device Vgs: +1V to -4V Ids (mA) 2000 1500 1000 500 0 0 10 20 30 40 50 60 Vds (V) 40 GMax (dB) Gain (dB) 30 |H(2,1)| (dB) 20 10 Parameter Value Units Id-max 1000 mA/mm Peak gm 225 mS/mm Vp -3.5 V Vbr(GD) >450 V ft 11 GHz fmax 18 GHz Power Density 7.5 W/mm Peak Power 16.5 W Peak Drain Eff 71 % Optimum load 31.4+j46.1 W [1] Class AB Bias: Vds=48V, Ids = 20 mA/mm 0 ft fmax [2] frequency = 2.14 GHz -10 .1 1 10 Frequency (GHz) 100 Broadband Topologies Topology Advantages Disadvantages Resistive FB - lumped implementation - good S22 - Output not designed for Zopt - Tuning Zload affects gain flatness and S11 - Rf Pdiss / leakage issues RLC Lossy Match - Simple/lumped design - output optimized for Zopt - Input optimized for gain - All-pass network at input implies excellent S11 - Lumped circuit, so flatness thermal design is critical Distributed Amp - best bandwidth and gain - dissipation spread out - Zload optimization for each cell is complicated - poor efficiency - implementation feasibility issues Internal Design Match Topology and Design • Input Match options as shown above • Use standard DOE design principles • Output – no matching • Provides most flexibility Max Gain (dB) Max Gain (dB) 18 17 16 15 14 13 12 dB(SParam_PassiveMatch_PE1D278C..S(1,1)) dB(SParam_PassiveMatch_PE1D278B..S(1,1)) dB(SParam_PassiveMatch_PE1D278A..S(1,1)) dB(SParam_PassiveMatch_PE1D2789..S(1,1)) SParam_PassiveMatch_SE1D278C..MaxGain1 SParam_PassiveMatch_SE1D278B..MaxGain1 SParam_PassiveMatch_SE1D278A..MaxGain1 SParam_PassiveMatch_SE1D2789..MaxGain1 • Takes advantage of GaN high impedances 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 freq, GHz -5 7 Passive Model, S11 (dB) Input Return Loss, S11 -10 -15 -20 -25 -30 -35 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 freq, GHz Internal Design Simulation Methodology • Design Methodology • Design/Simulate Input circuitry • Assume Ideal Match (choose load impedance) Practical Output Matching Transformer Balun Lumped Element 20 0 15 -5 10 -10 5 -15 0 0.0 0.5 1.0 1.5 -20 2.0 freq, GHz • Uses 6.6mm device periphery • Designed for 25Ω source and load impedance • frequency target is 20-1000MHz • Multi-chip module approach with GaAs passive die and GaN HEMT active die. • Minimizes SiC die area as the matching circuits are large at low GHz frequencies and below. Output Power (dBm) 5 50 80 47 70 44 60 41 50 38 40 35 30 32 20 29 10 26 Gain (dB), PAE (%) 25 dB(S(2,2)) dB(S(1,1)) dB(S(2,1)) Design Example 45W, 20-1000MHz 0 14 17 20 23 26 29 32 Pin (dBm) Performance • Vdq = 50V, Idq = 130mA • Bandwidth: 20 – 1000 MHz • Gain: 17.5±1 dB • Input return loss: < 11 dB • Output power: 50.3 W at 512 MHz • PAE: 70% at 512 MHz Balun Matching • Two 25W matched unit amplifiers are combined together. • Broadband 45W amplifiers are first designed for operating in a 25W system. • Two such PAs are combined using a broadband 1:1 Balun at input and output to convert the differential 25W impedance to a 50W system. • Gate bias feeds isolated through a resistor, and connected together. • The high-Q bias feed inductors at drain of each device are connected together. • 300W ferrite (at 100 MHz) at the drain bias feed to extend low frequency performance. Balun Design • Broadband coiled balun is formed by winding a rigid coax around a ferrite rod • Coiling increases self-inductances and the ferrite improves low frequency cut-off • Advances in low-loss ferrites make them suitable for GHz range • A 43 material ferrite rod from Fair-Rite Corp with 5mm diameter is used - provides high permeability at low frequency and low loss at high frequency • 50Ω coax with 0.22dB/ft loss, that can handle 124W at 500MHz is used • The center and outer conductor are connected to unbalanced signal and ground at one end and to the differential balanced signal at the other. • The ferrite forces equal and opposing current at the inner and outer conductor and isolates the 180º signal from the input ground at low frequency • For high frequency isolation the coax length is quarter wave long at the upper cut-off frequency. • This results in a 4 turn coil for the chosen ferrite diameter. Balun Performance Measured performance • Insertion loss (back-back) : 0.34 dB • Insertion loss per balun : 0.17 dB • Return loss: better than 20 dB 90W PA Module CW Performance Vdq = 50V, Idq = 265mA • • • • Frequency: 100 – 1000 MHz Gain over band: 15.1 – 16.3 dB Output power: 82 – 107.5 W Efficiency: 51.9 – 73.8 % Design Example 80W Module, 100-800MHz Small Signal Sweep dB(S(2,1)) 55 54 53 52 51 50 49 48 47 46 45 1.2E9 1.1E9 1.0E9 9.0E8 8.0E8 7.0E8 6.0E8 5.0E8 4.0E8 3.0E8 2.0E8 1.0E8 0.0 RFfreq • Uses 15.5mm device periphery • designed for 50W source, 12.5W load impedance • frequency target is 100-800MHz • Multi-chip module approach with GaAs passive die and GaN HEMT active die. • Minimizes SiC die area as the matching circuits are large at low GHz frequencies and below. 18 0 17 -5 16 -10 15 -15 14 -20 13 -25 12 -30 11 -35 0.1 0.3 0.5 0.7 0.9 dB(S(2,2)) dB(S(1,1)) Pout (dBm) Output Power 1.0 freq, GHz Simulated Performance • Vdq = 48V, Idq = 300mA • Frequency: 100 – 800 MHz • Gain: 11±1 dB • Input return loss: < 11 dB • Output power: 80W across the band • PAE: >50% across the band Transformer Matching • Single 50W matched amplifier • Broadband 80W amplifier is designed for operating with a 50W input impedance. • Amplifier is designed based on ideal 12.5W output impedance. • The challenge is to create this impedance • The PA drives a broadband 4:1 transformer to convert the 12.5W impedance to a 50W system. Transformer Match XMB0220B5050 Features: • • • • • • 30-1000 MHz 4:1 Transformer (50Ω to 12.5 Ω) Broadband Defense Applications High Power > 100W Very Low Loss < 0.5dB 80W PA Module CW Performance Vdq = 48V, Idq = 300mA (class-AB) Performance • Frequency: 100 – 800 MHz • Gain: >10dB • Input return loss: <-12 dB • Output power: 80W • Efficiency: 52.5 – 57.7% Design Example Unmatched FETs Lumped Element Match • Single 50W matched amplifier • Broadband design “generally” hitting target impedances. • The challenge is to create this impedance • Determine Target Impedances • Actual impedance from loadpull • Non-linear model simulation results Z0= 10Ω Wirebond model Efficiency 2.0GHz Pin = 35dBm 4 56 48 60 54 64 1 52 Unit Cells with manifold model 5648 54 60 60 52 56 50 46 0 50 2 64 Z0(gamma_ld1_imag) 605 2 3 50 56 48 -1 4 5 Eff Meas 6 7 8 Z0(gamma_ld1_real) Eff Sim 9 10 Package Model 11 Data Point Lumped Element Topology L+C Match uStrip+C Match strip strip strip Q=1. 0 VSWR=1. 7 30W PA Module 700-2400MHz Simulations Simulated Performance • Frequency: 700 – 2400 MHz • Gain: >10dB • Input return loss: <-12 dB • Output power: 30W • Efficiency: >25% Output Impedance S11 Match to 50Ω 30W PA Module CW Performance 2.0pF 0.4pF 1.0pF 2.7pF Performance • Frequency: 700 – 2400 MHz • Gain: >10dB • Input return loss: <-12 dB • Output power: 30W • Efficiency: >28% Combination Matching • Two 25W matched unit amplifiers are combined together. • Broadband 100W peak power amplifiers are first designed for operating in a 6.25W system. • Two such PAs are combined using a broadband 4:1 Transformer followed by a balun to convert the differential 25W impedance to a 50W system. • Gate bias feeds isolated through a resistor, and connected together. • The high-Q bias feed inductors at drain of each device are connected together. 100W PA Module 30-512MHz Simulations Freq (MHz) Pin (W) Zload Zs PAE (%) Pdel (W) 30 31 7+j0 13 + j 4.7 41 52 65 31 8+j0 9+j9 43.6 51.7 100 31 7+j0 9 + j 7.4 44 52 225 31 8.4 +j 0 7+j6 50 52 380 31 7+j1 2 + j 4.1 52 52.5 512 31 7+j3 2.6 +j 2.7 55 52 Design Target • Frequency: 30 – 512 MHz • Gain: >16dB • Input return loss: <-7 dB • Output power: 100W PEP • Efficiency: >18% • Determine Target Impedances • Actual impedance from loadpull • Non-linear model simulation result • Notice Zload is almost purely real at 7-8Ω • This drives 4:1 topology at 6.25Ω per side 100W PA Module 30-512MHz Simulations Simulated Performance • Frequency: 30 – 512 MHz • Gain: >16dB • Input return loss: <-7 dB • Output power: 100W PEP • Efficiency: >18% 100W PA Module 2-tone Performance Performance • Frequency: 30 – 700 MHz • Gain: >16dB • Input return loss: <-7 dB • Output power: 100W PEP • Efficiency: >18% Summary • Emerging SDR architectures require wideband, high power amplifiers with high efficiency, compact size and low cost • GaN-on-SiC technology adoption continues for high power commercial and military applications • Demonstrations include: • 90W (dual device module), 100–1000 MHz, >51% drain efficiency • 80W (single device), 100-800MHz, >51% drain efficiency • 30W (single device), 700-2400MHz, >28% drain efficiency • 100W peak power (dual device), 30-700MHz, >18% drain efficiency