Preliminary Datasheet RJF0609JSP R07DS1066EJ0100 Rev.1.00 May 10, 2013 60V - 1.5V Silicon N Channel Thermal FET Power Switching Description This FET has the over temperature shut-down capability sensing to the junction temperature. This FET has the built-in over temperature shut-down circuit in the gate area. And this circuit operation to shut-down the gate voltage in case of high junction temperature like applying over power consumption, over current etc.. Features • • • • • • • • Logic level operation (4 V Gate drive). Built-in the over temperature shut-down circuit. High endurance capability against to the short circuit. Latch type shut down operation (need 0 voltage recovery). Built-in the current limitation circuit. High density mounting Power supply voltage applies 12 V and 24 V. AEC-Q101 Compliant Outline RENESAS Package code: PRSP0008DD-D (Package name: SOP-8 (FP-8DAV)) 8 5 7 6 7 3 1 2 5 6 4 2 Latch Circuit 4 Current Limitation Circuit Gate Resistor Temperature Sensing Circuit 8 Gate Resistor Gate Shut-down Circuit MOS1 Temperature Sensing Circuit 1 Latch Circuit MOS2 Current Limitation Circuit 1, 3 Source 2, 4 Gate 5, 6, 7, 8 Drain Gate Shut-down Circuit 3 Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Drain to source voltage VDSS 60 Gate to source voltage VGSS 16 Gate to source voltage VGSS –2.5 Drain current ID Note4 1.5 Body-drain diode reverse drain current IDR 1.5 Avalanche current IAP Note 3 1.5 Avalanche energy EAR Note 3 9.6 Channel dissipation Pch Note 1 1 Channel dissipation Pch Note 2 1.5 Channel temperature Tch 150 Storage temperature Tstg –55 to +150 Notes: 1. 1 Drive operation : When using the glass epoxy board (FR4 40 × 40 × 1.6 mm), PW ≤ 10 s 2. 2 Drive operation : When using the glass epoxy board (FR4 40 × 40 × 1.6 mm), PW ≤ 10 s 3. Tch = 25°C, Rg ≥ 50 Ω 4. It provides by the current limitation lower bound value. R07DS1066EJ0100 Rev.1.00 May 10, 2013 Unit V V V A A A mJ W W °C °C Page 1 of 7 RJF0609JSP Preliminary Typical Operation Characteristics (Ta = 25°C) Item Input voltage Symbol VIH VIL Input current (Gate non shut down) Input current (Gate shut down) Shut down temperature Gate operation voltage Drain current (Current limitation value) IIH1 IIH2 IIL IIH(sd)1 IIH(sd)2 Tsd Vop ID limt Min 3.5 — — — — — — — 3.5 1.5 Typ — — — — — 0.8 0.35 175 — — Max — 1.2 100 50 1 — — — 12 — Unit V V μA μA μA mA mA °C V A Test Conditions Vi = 8 V, VDS = 0 Vi = 3.5 V, VDS = 0 Vi = 1.2 V, VDS = 0 Vi = 8 V, VDS = 0 Vi = 3.5 V, VDS = 0 Channel temperature VGS = 5 V, VDS = 10 V Note 5 Notes: 5. Pulse test Electrical Characteristics (Ta = 25°C) Item Drain current Symbol Min Typ Max Unit ID1 ID2 ID3 — — — — 5.4 10 — — A mA A V VGS = 3.5 V, VDS = 10 V Note 6 VGS = 1.2 V, VDS = 10 V VGS = 12 V, VDS = 10 V Note 6 ID = 10 mA, VGS = 0 IG = 800 μA, VDS = 0 IG = –100 μA, VDS = 0 VGS = 8 V, VDS = 0 VGS = 3.5 V, VDS = 0 VGS = 1.2 V, VDS = 0 VGS =– 2.4 V, VDS = 0 VGS = 8 V, VDS = 0 VGS = 3.5 V, VDS = 0 Drain to source breakdown voltage V(BR)DSS — — 1.5 60 Gate to source breakdown voltage V(BR)GSS V(BR)GSS IGSS1 IGSS2 IGSS3 IGSS4 IGS(OP)1 IGS(OP)2 IDSS 16 –2.5 — — — — — — — — — — — — — 0.8 0.35 — — — 100 50 1 –100 — — 10 V V μA μA μA μA mA mA μA Gate to source cutoff voltage Forward transfer admittance VGS(off) |yfs| Static drain to source on state resistance RDS(on) RDS(on) 1.1 1.0 — — — 2.2 208 142 2.1 — 350 263 V S mΩ mΩ Output capacitance Turn-on delay time Rise time Turn-off delay time Fall time Body-drain diode forward voltage Coss td(on) tr td(off) tf VDF trr — — — — — — — 265 0.55 1.88 3.9 3.7 0.82 71 — — — — — — — pF μs μs μs μs V ns tos1 tos2 — — 1.02 0.59 — — ms ms Gate to source leak current Input current (shut down) Zero gate voltage drain current Body-drain diode reverse recovery time Over load shut down Note 7 operation time Test Conditions VDS = 32 V, VGS = 0 Ta = 125°C ID = 1 mA, VDS = –0 V ID = 0.7 A, VDS = 10 V Note 6 ID = 0.7 A, VGS = 4 V Note 6 ID = 0.7 A, VGS = 10 V Note 6 VDS = 10 V, VGS = 0, f = 1MHz ID= 0.7 A, VGS = 10 V RL = 43 Ω IF = 1.5 A, VGS = 0 IF = 1.5 A, VGS = 0 diF/dt = 50 A/μs VGS = 5 V, VDD = 16 V VGS = 5 V, VDD = 24 V Notes: 6. Pulse test 7. Including the junction temperature rise of the over loaded condition. R07DS1066EJ0100 Rev.1.00 May 10, 2013 Page 2 of 7 RJF0609JSP Preliminary Main Characteristics Power vs. Temperature Derating Maximum Safe Operation Area 100 Test condition. When using the glass epoxy board. (FR4 40 x 40 x 1.6 mm), (PW ≤ 10s) 3.0 Drain Current ID (A) Channel Dissipation Pch (W) 4.0 2.0 2D 1.0 1D rive riv rO er Op per era atio tio 50 PW = 1 ms 1 150 DC 0.1 ati on PW Operation in this area is limited RDS(on) 0.01 0.1 200 10 Op er n 100 Thermal shut down operation area 10 n 0 0 Ta = 25°C 1 shot Pulse 1 Driver Operation 1 ≤1 0s N ote ms 8 10 100 Drain to Source Voltage VDS (V) Ambient Temperature Ta (°C) Note 8: When using the glass epoxy board. (FR4 40 x 40 x 1.6 mm) Typical Output Characteristics 1.5 5V 6V 8V 10 V 4 Pulse Test VDS = 10 V Pulse Test 4V VGS = 3.5 V 3 2 1 Drain Current ID (A) Drain Current ID (A) 5 Typical Transfer Characteristics 1.0 Tc = 150°C 0.5 25°C −40°C 2 4 6 8 10 1 2 3 4 5 Drain to Source Voltage VDS (V) Gate to Source Voltage VGS (V) Drain Source Saturation Voltage vs. Gate to Source Voltage Static Drain to Source On State Resistance vs. Drain Current 300 Pulse Test 200 0.75 A 100 0.5 A 0 0 ID = 0.25 A 2 4 6 8 Gate to Source Voltage VGS (V) R07DS1066EJ0100 Rev.1.00 May 10, 2013 10 Static Drain to Source On State Resistance RDS(on) (mΩ) Drain to Source Saturation Voltage VDS(on) (mV) 0 0 0 1000 Pulse Test VGS = 4 V 100 10 V 10 0.1 1 10 Drain Current ID (A) Page 3 of 7 Preliminary Body-Drain Diode Reverse Recovery Time Static Drain to Source On State Resistance vs. Temperature 1000 400 ID = 0.25 A, 0.5 A, 0.75 A 300 VGS = 4 V 200 ID = 0.25 A, 0.5 A, 0.75 A 100 10 V Pulse Test 0 −50 −25 0 25 50 Reverse Recovery Time trr (ns) Static Drain to Source On State Resistance RDS(on) (mΩ) RJF0609JSP 75 100 125 150 1 10 Switching Characteristics Typical Capacitance vs. Drain to Source Voltage 10000 td(off) Capacitance C (pF) Switching Time t (μs) 10 0.1 Reverse Drain Current IDR (A) tf tr 1 td(on) VGS = 10 V, VDD = 30 V PW = 300 μs, duty ≤ 1 % 0.1 0.1 1 VGS = 0 f = 1 MHz 1000 Coss 100 10 10 0 10 20 30 40 50 60 Drain Current ID (A) Drain to Source Voltage VDS (V) Reverse Drain Current vs. Source to Drain Voltage Gate to Source Voltage vs. Shutdown Time of Load-Short Test Gate to Source Voltage VGS (V) 2.0 Reverse Drain Current IDR (A) di / dt = 50 A /μs VGS = 0 Case Temperature Tc (°C) 10 Pulse Test 1.5 1.0 5V 0.5 VGS = 0 V 0 100 0.2 0.4 0.6 0.8 1.0 1.2 Source to Drain Voltage VSD (V) R07DS1066EJ0100 Rev.1.00 May 10, 2013 16 14 12 VDD = 16 V 10 8 6 24 V 4 2 0 0.1 1 10 Shutdown Time of Load-Short Test Pw (ms) Page 4 of 7 RJF0609JSP Preliminary Shutdown Case Temperature vs. Gate to Source Voltage Shutdown Case Temperature Tc (°C) Forward transfer admittance |yfs| (S) Forward transfer admittance vs. Drain Current 10 Ta = –40°C 25°C 1 150°C VDS = 10 V Pulse Test 0.1 0.1 1 10 200 180 160 140 120 ID = 0.2 A 100 0 2 6 8 10 Gate to Source Voltage VGS (V) Drain Current ID (A) Normalized Transient Thermal Impedance γs (t) 4 Normalized Transient Thermal Impedance vs. Pulse Width (1 Drive Operation) 10 1 D=1 0.5 0.1 0.1 0.05 0.2 0.02 0.01 θch-f(t) = γs (t) · θch - f θch-f = 125°C/W, Ta = 25°C When using the glass epoxy board (FR4 40 x 40 x 1.6 mm) 0.01 0.001 1s t ho pu lse PDM D= PW T PW T 0.0001 10 μ 100 μ 1m 10 m 100 m 1 10 100 1000 10000 Normalized Transient Thermal Impedance γs (t) Pulse Width PW (S) Normalized Transient Thermal Impedance vs. Pulse Width (Operatioon of 2 devices; allowable value per device) 10 1 D=1 0.5 0.2 0.1 0.1 0.05 0.02 0.01 θch-f(t) = γs (t) · θch - f θch-f = 166°C/W, Ta = 25°C When using the glass epoxy board (FR4 40 x 40 x 1.6 mm) 0.01 0.001 1 o sh tp uls e PDM D= PW T PW T 0.0001 10 μ 100 μ 1m 10 m 100 m 1 10 100 1000 10000 Pulse Width PW (S) R07DS1066EJ0100 Rev.1.00 May 10, 2013 Page 5 of 7 RJF0609JSP Preliminary Switching Time Test Circuit Waveform 90% Vout Monitor Vin Monitor D.U.T. Vin RL 10% 10% Vout Vin 10V 50 Ω VDD = 30 V 90% td(on) Avalanche Test Circuit VDS Monitor 10% tr 90% tf td(off) Avalanche Waveform L EAR = 1 2 L • IAP2 • V(BR)DSS V(BR)DSS – VDD IAP Monitor V(BR)DSS Rg Vin 10 V D. U. T IAP VDD ID 50 Ω 0 R07DS1066EJ0100 Rev.1.00 May 10, 2013 VDS VDD Page 6 of 7 RJF0609JSP Preliminary Package Dimensions JEITA Package Code P-SOP8-3.95 x 4.9-1.27 RENESAS Code PRSP0008DD-D Previous Code FP-8DAV MASS[Typ.] 0.085g F Package Name SOP-8 *1 D bp 1 c *2 E Index mark HE 5 8 4 Z Terminal cross section (Ni/Pd/Au plating) * 3 bp x M NOTE) 1. DIMENSIONS "*1(Nom)" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. e Reference Symbol A1 A L1 L y Detail F D E A2 A1 A bp b1 c c1 HE e x y Z L L1 Dimension in Millimeters Min Nom Max 4.90 5.3 3.95 0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 5.80 6.10 6.20 1.27 0.25 0.1 0.75 0.40 0.60 1.27 1.08 Ordering Information Orderable Part Number RJF0609JSP-00-J0 Note: Quantity 2500 pcs/reel Shipping Container Taping The symbol of 2nd "-" is occasionally presented as "#". R07DS1066EJ0100 Rev.1.00 May 10, 2013 Page 7 of 7 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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