QFNs-st A JCET Company Quad Flat No-Lead Package (Stand-off Terminal) HIGHLIGHTS •Saw singulated, stand-off terminal version • Square or rectangular body sizes • Leads on 4 sides of the body (QFN) • 25-50mm stand off • Multi row lead design options • Thin package thickness options: 0.80 & 1.0mm • In-strip testing ready FEATURES • Body sizes: 6 x 6mm to 15 x 15mm • Pin counts from 52L up to 700L • Lead pitch: 0.40 and 0.50 with other options available • High I/O configurations available (up to 700L, multi row) • Custom I/O configuration options available • Available in gold or copper wirebond versions • Use of compression molding for long wire lengths • 0.80mm and 1.0mm thickness options • Leadframes are pre-plated (PPF) • Green materials set • Excellent thermal and electrical performance • Full in-house package and leadframe design capability • Full in-house assembly and test capability • Full in-house electrical, thermal and mechanical simulation and measurement capability APPLICATIONS • Computing and Storage DESCRIPTION STATS ChipPAC’s Quad Flat No-Lead Stand-off Terminal (QFNs-st) package features a significantly higher number of I/O terminal pads than traditional QFN packages. Whereas QFP and QFN packages require 0.4mm pitch to accommodate more I/O, QFNs-st can accommodate more I/O with a more relaxed terminal pitch by virtue of allowing multiple rows. QFNs-st has the flexibility to accommodate multiple rows of terminals with either fixed or variable pitch which, in turn, enables board routing for various applications, thereby extending the application and pin count range of this cost effective QFN type package. The QFNs-st is a leadframe based, plastic encapsulated, chip scale packaging solution in molded array format (saw singulated). An exposed die pad coupled with extremely low RLC provides excellent electrical and thermal performance enhancements, and is especially suited for wireless, handheld portable, computing and storage applications. QFNs-st is available in various body sizes and thicknesses, has a green/lead-free bill of materials and can be mounted by conventional SMT equipment. Board level reliability and drop test have been proven for both mobile and computing applications. TEST SERVICES • Telecommunications • RF • Product Engineering support • Analog and Linear • Probe capability • Logic • Program generation/conversion • Drop Ship available • ASICs and DSP www.cj-elec.com www.statschippac.com QFNs-st A JCET Company Quad Flat No-Lead Package (Stand-off Terminal) THERMAL PERFORMANCE, θja (°C/W) Body Size (mm) Die Size (mm) Air Flow (m/s) VQFNs-st-dr 7 x 7 x 0.8 3.8 x 3.9 NC VQFNs-st-mr 11.5 x 11.5 x 0.8 5.9 x 5.7 NC Package Note: Die Power (W) Ambient Temperature (°C) TT (ºC) θJA (ºC/W) jJT (ºC/W) jJB (ºC/W) 52.2 52.1 27.2 0.15 12.3 43.64 43.55 18.6 0.09 4.5 TJ (ºC) 1.0 25 PACKAGE CONFIGURATIONS ELECTRICAL PERFORMANCE Electrical parasitic data is highly dependent on the package layout and wire properties. 3D electrical simulation can be used on the specific package design to provide the best prediction of electrical behavior. Electrical characterization available upon request. Please contact your STATS ChipPAC Technical Program Manager. SPECIFICATIONS Body Size (mm) 6.0x6.0 7.0x7.0 Die Thickness Wire Gold: Copper: 125-350µm 18-33µm (0.7-1.3mils) diameter 18-33µm (0.7-1.3mils) diameter 8.0x8.0 Matte Tin, preplated Ni/Pd/Au Laser Tape & Reel, tube, JEDEC tray 9.0x9.0 Contact STATS ChipPAC for availability. Lead Finish Marking Packing Options RELIABILITY Moisture Sensitivity Level Temperature Cycling High Temp Storage Pressure Cooker Test Temperature/Humidity Test 10.0x10.0 JEDEC MSL 3 –65°C/150°C, 1000 cycles 150°C, 1000 hrs 121°C, 100% RH, 2 atm, 168 hrs 85°C/85% RH, 1000 hrs 11.0x11.0 11.5x11.5 CROSS-SECTION 2 row QFNs-st 12.0x12.0 13.0x13.0 Au/Pd Plated Terminals shown 4 row QFNs-st 14.0x14.0 15.0x15.0 Global Offices 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 Lead Pitch=0.40mm Lead Pitch=0.50mm Lead Pitch=0.65mm Leads Max Pad Size* Leads Max Pad Size Leads Max Pad Size 92 120 136 NA NA 116 156 184 208 220 132 180 216 248 268 156 216 264 308 340 172 240 296 348 388 196 276 344 408 460 204 288 360 428 484 212 300 376 448 508 236 336 424 508 580 252 360 456 548 628 276 396 504 608 700 3.7 2.7 1.7 NA NA 4.9 3.9 2.9 1.9 0.9 5.7 4.7 3.7 2.7 1.7 6.9 5.9 4.9 3.9 2.9 7.7 6.7 5.7 4.7 3.7 8.9 7.9 6.9 5.9 4.9 9.3 8.3 7.3 6.3 5.3 9.7 8.7 7.7 6.7 5.7 10.9 9.9 8.9 7.9 6.9 11.7 10.7 9.7 8.7 7.7 12.9 11.9 10.9 9.9 8.9 76 104 120 NA NA 92 128 152 172 180 108 152 184 212 228 124 176 216 252 276 140 200 248 292 324 156 224 280 332 372 164 236 296 352 396 172 248 312 372 420 188 272 344 412 468 204 296 376 452 516 220 320 408 492 564 3.9 2.9 1.9 NA NA 4.6 3.6 2.6 1.6 0.6 5.9 4.9 3.9 2.9 1.9 6.9 5.9 4.9 3.9 2.9 7.9 6.9 5.9 4.9 3.9 8.9 7.9 6.9 5.9 4.9 9.4 8.4 7.4 6.4 5.4 9.9 8.9 7.9 6.9 5.9 10.9 9.9 8.9 7.9 6.9 11.9 10.9 9.9 8.9 7.9 12.9 11.9 10.9 9.9 8.9 52 68 NA NA NA 60 80 88 NA NA 76 104 120 132 NA 84 116 136 152 NA 100 136 164 188 200 116 164 200 232 252 116 164 200 232 252 124 176 216 252 276 140 200 248 292 324 148 212 264 312 348 164 236 296 352 396 3.2 1.9 NA NA NA 3.9 2.6 1.3 NA NA 5.2 3.9 2.6 1.3 NA 5.8 4.5 3.2 1.9 NA 7.1 5.8 4.5 3.2 1.9 8.4 7.1 5.8 4.5 3.2 8.4 7.1 5.8 4.5 3.2 9.1 7.8 6.5 5.2 3.9 10.4 9.1 7.8 6.5 5.2 11.0 9.7 8.4 7.1 5.8 12.3 11.0 9.7 8.4 7.1 * Maximum paddle size calculated using minimum lead edge to paddle edge distance of 0.150mm. For recommended value of 0.200mm, decrease maximum paddle size value by 0.100mm. All paddle sizes in mm. Au/Pd Plated Terminals shown Corporate Office Rows 10 Ang Mo Kio St. 65, #04-08/09 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 USA 510-979-8000 CHINA 86-21-5976-5858 KOREA 82-32-340-3114 SWITZERLAND 41-21-8047-200 The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Pte. Ltd. Trademark registered in United States. Singapore company registration number 199407932D. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice. ©Copyright 2016. STATS ChipPAC Pte. Ltd. All rights reserved. Apr 2016