RENESAS M5M5T5636UG-22

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI LSIs
January 14, 2003 Rev.0.7
M5M5T5636UG – 25,22,20
Preliminary
Notice: This is not final specification.
Some parametric limits are subject to change.
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
DESCRIPTION
APPLICATION
The M5M5T5636UG is a family of 18M bit synchronous SRAMs
organized as 524288-words by 36-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Mitsubishi's SRAMs are
fabricated with high performance, low power CMOS technology,
providing greater reliability. M5M5T5636UG operates on 2.5V
power/ 1.8V I/O supply or a single 2.5V power supply and are
2.5V CMOS compatible.
High-end networking products that require high bandwidth, such
as switches and routers.
FEATURES
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 250, 225, and 200 MHz
• Fast access time: 2.6, 2.8, 3.2 ns
• Single 2.5V -5% and +5% power supply VDD
• Separate VDDQ for 2.5V or 1.8V I/O
• Individual byte write (BWa# - BWd#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• CKE# pin to enable clock and suspend operations
• Internally self-timed, registers outputs eliminate the need
to control G#
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• Three chip enables for simple depth expansion
• JTAG boundary scan support
FUNCTION
Synchronous circuitry allows for precise cycle control
triggered by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs,
all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,
BWd#) and Read/Write (W#). Write operations are controlled by
the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#)
inputs. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK)
and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the
SRAM in the power-down state.The Linear Burst order (LBO#) is
DC operated pin. LBO# pin will allow the choice of either an
interleaved burst, or a linear burst.
All read, write and deselect cycles are initiated by the ADV
LOW input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
Package
165(11x15) bump BGA
Body Size (13mm x 15mm)
Bump Pitch 1.0mm
PART NAME TABLE
Part Name
Access
Cycle
Active Current
(max.)
Standby Current
(max.)
M5M5T5636UG - 25
2.6ns
4.0ns
560mA
30mA
M5M5T5636UG - 22
2.8ns
4.4ns
500mA
30mA
M5M5T5636UG - 20
3.2ns
5.0ns
440mA
30mA
1/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
BUMP LAYOUT(TOP VIEW)
165bump-BGA
1
2
3
4
5
6
7
8
9
10
11
A
NC
A7
E1#
BWc#
BWb#
E3#
CKE#
ADV
A17
A8
NC
B
NC
A6
E2
BWd#
BWa#
CLK
W#
G#
A18
A9
NC
C
DQPc
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQPb
D
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
E
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
F
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
G
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
H
MCH
MCH
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
J
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
K
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
L
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
M
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
N
DQPd
NC
VDDQ
VSS
NC
NC
MCH
VSS
VDDQ
NC
DQPa
P
NC
NC
A5
A3
TDI
A1
TDO
A15
A13
A11
NC
R
LBO#
NC
A4
A2
TMS
A0
TCK
A16
A14
A12
A10
Note1. MCH means "Must Connect High". MCH should be connected to HIGH.
2/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
BLOCK DIAGRAM
VDD
A0
A1
A2~18
VDDQ
19
19
17
ADDRESS
REGISTER
A1'
A1
D1
LINEAR/
Q1
D0
INTERLEAVED
BURST
COUNTER
Q0
A0
A0'
LBO#
CLK
CKE#
19
WRITE ADDRESS
REGISTER1
WRITE ADDRESS
REGISTER2
19
ZZ
ADV
BYTE2
WRITE
DRIVERS
BYTE3
WRITE
DRIVERS
MEMORY
ARRAY
BYTE4
WRITE
DRIVERS
W#
36
G#
256Kx36
OUTPUT BUFFERS
AND
DATA COHERENCY
CONTROL LOGIC
OUTPUT SELECT
WRITE REGISTRY
OUTPUT REGISTERS
BWa#
BWb#
BWc#
BWd#
BYTE1
WRITE
DRIVERS
INPUT
INPUT
REGISTER1
REGISTER0
DQa
DQPa
DQb
DQPb
DQc
DQPc
DQd
DQPd
READ
LOGIC
E1#
E2
E3#
VSS
Note2. The BLOCK DIAGRAM does not include the Boundary Scan logic. See Boundary Scan chapter.
Note3. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION
and timing diagrams for detailed information.
3/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
PIN FUNCTION
Pin
Function
Name
A0~A18
Synchronous
Address
Inputs
These inputs are registered and must meet the setup and hold times around the rising edge of
CLK. A0 and A1 are the two least significant bits (LSB) of the address field and set the internal
burst counter if burst is desired.
BWa#, BWb#,
BWc#, BWd#
Synchronous
Byte Write
Enables
These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and
must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be
asserted on the same cycle as the address. BWs are associated with addresses and apply to
subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc#
controls DQc, DQPc pins; BWd# controls DQd, DQPd pins.
CLK
Clock Input
This signal registers the address, data, chip enables, byte write enables
and burst control inputs on its rising edge. All synchronous inputs must
meet setup and hold times around the clock's rising edge.
E1#
Synchronous
Chip Enable
This active LOW input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW).
E2
Synchronous
Chip Enable
This active High input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW). This input can be used for memory depth expansion.
E3#
Synchronous
Chip Enable
This active Low input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW). This input can be used for memory depth expansion.
G#
Output Enable
This active LOW asynchronous input enable the data I/O output drivers.
ADV
Synchronous
Address
Advance/Load
CKE#
Synchronous
Clock Enable
When HIGH, this input is used to advance the internal burst counter, controlling burst access after
the external address is loaded. When HIGH, W# is ignored. A LOW on this pin permits a new
address to be loaded at CLK rising edge.
This active LOW input permits CLK to propagate throughout the device. When HIGH, the device
ignores the CLK input and effectively internally extends the previous CLK cycle. This input must
meet setup and hold times around the rising edge of CLK.
This active HIGH asynchronous input causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When active, all other inputs are ignored. When this
pin is LOW or NC, the SRAM normally operates.
ZZ
Snooze
Enable
W#
Synchronous
Read/Write
This active input determines the cycle type when ADV is LOW. This is the only means for
determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice
versa) other than by loading a new address. A LOW on the pin permits BYTE WRITE operations
and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs
occur if all byte write enables are LOW.
DQa,DQPa,DQb,DQPb
DQc,DQPc,DQd,DQPd
Synchronous
Data I/O
Byte “a” is DQa , DQPa pins; Byte “b” is DQb, DQPb pins; Byte “c” is DQc, DQPc pins; Byte “d” is
DQd,DQPd pins. Input data must meet setup and hold times around CLK rising edge.
Burst Mode
Control
This DC operated pin allows the choice of either an interleaved burst or a linear burst. If this pin is
HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input
leak current to this pin.
VDD
VDD
Core Power Supply
VSS
VSS
Ground
VDDQ
I/O buffer Power supply
LBO#
VDDQ
TDI
Test Data Input
TDO
Test Data Output
TCK
Test Clock
TMS
Test Mode Select
MCH
Must Connect High
These pins should be connected to HIGH
No Connect
These pins are not internally connected and may be connected to ground.
NC
These pins are used for Boundary Scan Test.
4/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
DC OPERATED TRUTH TABLE
Name
Input Status
LBO#
HIGH or NC
LOW
Operation
Interleaved Burst Sequence
Linear Burst Sequence
Note4. LBO# is DC operated pin.
Note5. NC means No Connection.
Note6. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.
BURST SEQUENCE TABLE
Interleaved Burst Sequence (when LBO# = HIGH or NC)
Operation
A18~A2
First access, latch external address
Second access(first burst address)
Third access(second burst address)
Fourth access(third burst address)
A1,A0
A18~A2
latched A18~A2
latched A18~A2
latched A18~A2
0,1
0,0
1,1
1,0
0,0
0,1
1,0
1,1
1,0
1,1
0,0
0,1
1,1
1,0
0,1
0,0
Linear Burst Sequence (when LBO# = LOW)
Operation
A18~A2
A1,A0
First access, latch external address
A18~A2
0,0
0,1
1,0
1,1
Second access(first burst address)
latched A18~A2
0,1
1,0
1,1
0,0
Third access(second burst address)
latched A18~A2
1,0
1,1
0,0
0,1
Fourth access(third burst address)
latched A18~A2
1,1
0,0
0,1
1,0
Note7. The burst sequence wraps around to its initial state upon completion.
TRUTH TABLE
Address
E1#
E2
E3#
ZZ
ADV
W#
BWx#
G#
CKE#
CLK
DQ
H
X
X
X
L
X
X
X
H
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
L
L
L
L->H
High-Z
None
L->H
High-Z
None
L->H
High-Z
None
Deselect Cycle
Deselect Cycle
Deselect Cycle
X
X
X
L
H
X
X
X
L
L->H
High-Z
None
Continue Deselect Cycle
L
X
L
X
H
X
H
X
L
X
L
X
L
L
L
L
L
H
L
H
H
X
H
X
X
X
X
X
L
L
H
H
L
L
L
L
L->H
Q
External
L->H
Q
Next
L->H
High-Z
External
L->H
High-Z
Next
L
X
L
X
H
X
H
X
L
X
L
X
L
L
L
L
L
H
L
H
L
X
L
X
L
L
H
H
X
X
X
X
L
L
L
L
L->H
D
External
L->H
D
Next
L->H
High-Z
None
L->H
High-Z
Next
X
X
X
L
X
X
X
X
H
L->H
-
Current
used
Operation
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Dummy Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
NOP/Write Abort, Begin Burst
Write Abort, Continue Burst
Ignore Clock edge, Stall
X
High-Z
None
X
X
X
H
X
X
X
X
X
Snooze Mode
Note8. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL.
Note9. BWx#=H means all Synchronous Byte Write Enables (BWa#,BWb#,BWc#,BWd#) are HIGH. BWx#=L means one or more
Synchronous Byte Write Enables are LOW.
Note10. All inputs except G# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
STATE DIAGRAM
F,L,X
Deselect
F,L,X
T,L,H
T,L,L
X,H,X
Read
Begin
Burst
T,L,H
X,H,X
T,L,H
Write
Begin
Burst
T,L,L
T,L,H
X,H,X
X,H,X
Read
Continue
Burst
T,L,L
Key
F,L,X
T,L,H
T,L,L
T,L,L
Write
Continue
Burst
X,H,X
Input Command Code
f
Current State
Transition
Next State
Note11. The notation "x , x , x" controlling the state transitions above indicate the state of inputs E, ADV and W# respectively.
Note12. If (E1# = L and E2 = H and E3# = L) then E="T" else E="F".
Note13. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL; “T” = input “true”; “F” = input “false”.
6/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
WRITE TRUTH TABLE
W#
BWa#
BWb#
BWc#
BWd#
H
X
X
X
X
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
Function
Read
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
Write Abort/NOP
L
H
H
H
H
Note14. “H”=input VIH; “L”=input VIL; “X”=input VIH or VIL.
Note15. All inputs except G# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VDDQ
VI
VO
PD
TOPR
TSTG(bias)
TSTG
Parameter
Conditions
Power Supply Voltage
I/O Buffer Power Supply Voltage
Input Voltage
Output Voltage
Maximum Power Dissipation (VDD)
Operating Temperature
Storage Temperature(bias)
With respect to VSS
Ratings
Unit
-1.0*~3.6
-1.0*~3.6
-1.0~VDDQ+1.0**
-1.0~VDDQ+1.0**
1050
0~70
-10~85
-55~125
V
Storage Temperature
Note16.* This is –1.0V when pulse width≤2ns, and –0.5V in case of DC.
** This is –1.0V~VDDQ+1.0V when pulse width≤2ns, and –0.5V~VDDQ+0.5V in case of DC.
V
V
V
mW
°C
°C
°C
7/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=2.375~2.625V, unless otherwise noted)
Limits
Symbol
Parameter
VDD
Power Supply Voltage
VDDQ
I/O Buffer Power Supply Voltage
VIH
Condition
Max
2.375
2.625
VDDQ = 2.5V
2.375
2.625
VDDQ = 1.8V
1.7
1.95
VDDQ = 2.375~2.625V
1.7
High-level Input Voltage
0.65*VDDQ
VDDQ = 1.7~1.95V
VIL
Unit
Min
VDDQ = 2.375~2.625V
-0.3*
Low-level Input Voltage
VDDQ = 1.7~1.95V
VDDQ+0.3*
0.7
0.35*VDDQ
VOH
High-level Output Voltage
IOH = -2.0mA
VOL
Low-level Output Voltage
IOL = 2.0mA
0.4
Input Leakage Current except ZZ
and LBO#
VI = 0V ~ VDDQ
10
Input Leakage Current of LBO#
VI = 0V ~ VDDQ
100
Input Leakage Current of ZZ
VI = 0V ~ VDDQ
100
Off-state Output Current
VI (G#) ≥ VIH, VO = 0V ~ VDDQ
4.0ns cycle(250MHz)
560
Power Supply Current : Operating
Device selected;
Output Open
VI≤VIL or VI≥VIH
ZZ≤VIL
4.4ns cycle(225MHz)
500
5.0ns cycle(200MHz)
440
Device
deselected
VI≤VIL or VI≥VIH
ZZ≤VIL
4.0ns cycle(250MHz)
260
4.4ns cycle(225MHz)
220
5.0ns cycle(200MHz)
180
ILI
ILO
ICC1
ICC2
Power Supply Current : Deselected
VDDQ-0.4
Device deselected; Output Open
VI≤VSS+0.2V or VI≥VDDQ-0.2V
CLK frequency=0Hz, All inputs static
Snooze mode
Snooze Mode Standby Current
ICC4
ZZ≥VDDQ-0.2V, LBO#≥VDD-0.2V
Device selected;
4.0ns cycle(250MHz)
Output Open
ICC5
Stall Current
CKE#≥VIH
4.4ns cycle(225MHz)
VI≤VSS+0.2V or
5.0ns cycle(200MHz)
VI≥VDDQ-0.2V
Note17.*VILmin is –1.0V and VIH max is VDDQ+1.0V in case of AC(Pulse width≤2ns).
Note18."Device Deselected" means device is in power-down mode as defined in the truth table.
ICC3
CMOS Standby Current
(CLK stopped standby mode)
V
V
V
V
V
10
V
µA
µA
mA
mA
30
mA
30
mA
180
160
mA
140
8/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
CAPACITANCE
Symbol
Parameter
CI
CO
Limits
Conditions
Input Capacitance
Min
Typ
Unit
6
8
VI=GND, VI=25mVrms, f=1MHz
Input / Output(DQ) Capacitance
Note19.This parameter is sampled.
Max
VO=GND, VO=25mVrms, f=1MHz
pF
pF
THERMAL RESISTANCE
4-Layer PC board mounted (70x70x1.6mmT)
Symbol
Parameter
θJA
Limits
Conditions
Thermal Resistance Junction Ambient
Min
Typ
Max
28.31
20.32
3.95
Air velocity=0m/sec
Air velocity=2m/sec
θJC
Thermal Resistance Junction to Case
Note20.This parameter is sampled.
Unit
°C/W
°C/W
°C/W
AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=2.375~2.625V, unless otherwise noted)
(1)MEASUREMENT CONDITION
Input pulse levels ········································ VIH=VDDQ, VIL=0V
Input rise and fall times ······························· faster than or equal to 1V/ns
Input timing reference levels ······················· VIH=VIL=0.5*VDDQ
Output reference levels ·······························VIH=VIL=0.5*VDDQ
Output load ·················································· Fig.1
30pF
(Including wiring and JIG)
Q
ZO=50Ω
50Ω
VT=0.5*VDDQ
Fig.1 Output load
Input
Waveform
VDDQ / 2
toff
tplh
Output
Waveform
Input
Waveform
VDDQ / 2
VDDQ / 2
Fig.2 Tdly measurement
tphl
Vh
Output
Waveform
(toff)
Vl
ton
Vh-(0.2(Vh-Vz)) Vz+(0.2(Vh-Vz))
Vz
0.2(Vz-Vl)
Vz-(0.2(Vz-Vl))
(ton)
Fig.3 Tri-State measurement
Note21.Valid Delay Measurement is made from the VDDQ/2 on the input waveform to the VDDQ/2 on the output waveform.
Input waveform should have a slew rate of faster than or equal to 1V/ns.
Note22.Tri-state toff measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20%
from its initial to final Value VDDQ/2.
Note:the initial value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table.
Note23. Tri-state ton measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20%
from its initial Value VDDQ/2 to its final Value.
Note:the final value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table.
Note24.Clocks,Data,Address and control signals will be tested with a minimum input slew rate of faster than or equal to 1V/ns.
9/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(2)TIMING CHARACTERISTICS
Symbol
Parameter
Clock
tKHKH
Clock cycle time
tKHKL
Clock HIGH time
tKLKH
Clock LOW time
Output times
tKHQV
Clock HIGH to output valid
tKHQX
Clock HIGH to output invalid
tKHQX1
Clock HIGH to output in LOW-Z
tKHQZ
Clock HIGH to output in High-Z
tGLQV
G# to output valid
tGLQX1
G# to output in Low-Z
tGHQZ
G# to output in High-Z
Setup Times
tAVKH
Address valid to clock HIGH
tckeVKH
CKE# valid to clock HIGH
tadvVKH
ADV valid to clock HIGH
tWVKH
Write valid to clock HIGH
Byte write valid to clock HIGH (BWa#~BWd#)
tBVKH
Enable valid to clock HIGH (E1#,E2,E3#)
tEVKH
Data In valid clock HIGH
tDVKH
Hold Times
Clock HIGH to Address don’t care
tKHAX
tKHckeX
Clock HIGH to CKE# don’t care
tKHadvX
Clock HIGH to ADV don’t care
tKHWX
Clock HIGH to Write don’t care
tKHBX
tKHEX
tKHDX
ZZ
tZZS
tZZREC
Clock HIGH to Byte Write don’t care
(BWa#~BWb#)
Clock HIGH to Enable don’t care (E1#,E2,E3#)
Clock HIGH to Data In don’t care
250MHz
-25
Min
Max
Limits
225MHz
-22
Min
Max
200MHz
-20
Min
Max
4.0
1.5
1.5
4.4
1.6
1.6
5.0
1.8
1.8
2.6
1.5
1.5
1.5
2.6
2.6
0.0
2.8
1.5
1.5
1.5
2.8
2.8
0.0
2.6
ns
ns
ns
3.2
1.5
1.5
1.5
3.2
3.2
0.0
2.8
Unit
3.2
ns
ns
ns
ns
ns
ns
ns
0.8
0.8
0.8
0.8
0.8
0.8
0.8
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.2
1.2
1.2
1.2
1.2
1.2
1.2
ns
ns
ns
ns
ns
ns
ns
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
0.5
0.5
0.5
ns
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ZZ standby
2*tKHKH
2*tKHKH
ZZ recovery
2*tKHKH
2*tKHKH
Note25.All parameter except tZZS, tZZREC in this table are measured on condition that ZZ=LOW fix.
Note26.Test conditions is specified with the output loading shown in Fig.1 unless otherwise noted.
Note27. tKHQX1, tKHQZ, tGLQX1, tGHQZ are sampled.
Note28.LBO# is static and must not change during normal operation.
2*tKHKH
2*tKHKH
ns
ns
10/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(3)READ TIMING
tKHKH
CLK
tKHKL
tKLKH
tckeVKH
tKHckeX
CKE#
tEVKH
tKHEX
E#
tadvVKH
tKHadvX
ADV
tWVKH
tKHWX
W#
BWx#
tAVKH
ADD
tKHAX
A1
A2
A3
tKHQX1
DQ
tGLQV
Q(A1)
tKHQV
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
tGHQZ
tKHQX
Q(A2)
Q(A3)
Q(A3+1)
tKHQZ
tGLQX1
G#
Read A1
Read A2
Burst Read
A2+1
Stall
Burst Read Burst Read Burst Read
A2+2
A2+3
A2
Deselect
Continue
Deselect
Read A3
Burst Read Burst Read Burst Read
A3+1
A3+2
A3+3
DON'T CARE
UNDEFINED
Note29.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An.
Note30. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW.
Note31.ZZ is fixed LOW.
11/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(4)WRITE TIMING
tKHKH
CLK
tKHKL
tKLKH
tckeVKH
tKHckeX
CKE#
tEVKH
tKHEX
E#
tadvVKH
tKHadvX
ADV
tWVKH
tKHWX
W#
tBVKH
tKHBX
BWx#
tAVKH
ADD
tKHAX
A1
A2
A3
A4
tDVKH
tKHDX
DQ
D(A1)
D(A2)
D(A2+1)
D(A2+3)
D(A2)
D(A3)
D(A4)
D(A4+1)
G#
Write A1
Write A2
Burst Write
A2+1
NOP
Burst Write
A2+3
Write A2
Write A3
NOP
Write A4
Burst Write
A4+1
Stall
Burst Write Burst Write
A4+2
A4+3
DON'T CARE
UNDEFINED
Note32.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An.
Note33. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW.
Note34.ZZ is fixed LOW.
12/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(5)READ/WRITE TIMING
tKHKH
CLK
tKHKL
tKLKH
tckeVKH
tKHckeX
CKE#
tEVKH
tKHEX
E#
tadvVKH
tKHadvX
ADV
tWVKH
tKHWX
W#
tBVKH
tKHBX
BWx#
tAVKH
ADD
tKHAX
A1
A2
A2
A3
A3
A4
A5
tDVKH
tKHQX1
tKHDX
DQ
Q(A1)
tKHQV
D(A2)
Q(A2)
D(A3)
D(A3+1)
Q(A3)
Q(A3+1)
D(A4)
Q(A5)
tKHQV
G#
Read A1
Write A2
Read A2
Write A3
Burst Write
A3+1
Read A3
Burst Read
A3+1
Deselect
Write A4
Stall
Read A5
Burst Read Burst Read
A5+1
A5+2
DON'T CARE
UNDEFINED
Note35.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An.
Note36. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW.
Note37.ZZ is fixed LOW.
13/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(6)SNOOZE MODE TIMING
CLK
tZZS
tZZREC
ZZ
All Inputs
(except ZZ)
DESELECT or READ only
Q
Snooze Mode
14/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
JTAG PORT OPERATION
Overview
The JTAG Port on this SRAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface
standard (commonly referred to as JTAG), but dose not implement all of the function required for 1149.1 compliance. The JTAG Port
interfaces with conventional CMOS logic level signaling.
Disabling the JTAG port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. To
assure normal operation of the SRAM with the JTAG Port unused, the TCK, TDI and TMS pins may be left floating or tied to High. The
TDO pin should be left unconnected.
JTAG Pin Description
Test Clock (TCK)
The TCK input is clock for all TAP events. All inputs are captured on the rising edge of TCK and the Test Data Out (TDO) propagates
from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP Controller state machine. An undriven TMS
input will produce the same result as a logic one input level.
Test Data In (TDI)
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between the TDI and TDO pins.
the register placed between the TDI and TDO pins is determined by the state of the TAP Controller state machine and the instruction
that is currently loaded in the TAP Instruction Resister (refer to the TAP Controller State Diagram). An undriven TDI Input will produce
the same result as a logic one input level.
Test Data Out (TDO)
The TDO output is active depending on the state of the TAP Controller state machine. Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed between the TDI and TDO pins.
Note:
This device dose not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS
is held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up.
JTAG Port Registers
Overview
The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequence of 1s and
0s applied to TMS as TCK is strobed. Each of TAP Registers are serial shift registers that capture serial input data on the rising edge of
TCK and push serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP Controller when it is moved into the Run-Test/Idle, or the
various data register states. Instructions are 3 bits long. The Instruction Resister can be loaded when it is placed between the TDI and
TDO pins. The Instruction Resister is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is
placed in Test-Logic-Reset state.
15/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
Bypass Register
The Bypass resister is a single-bit register that can be placed between the TDI and TDO pins. It allows serial test data to be passed
through the SRAM's JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the SRAM's input or I/O pins. The
flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pins. The relationship
between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the SRAM's I/O ring when the controller is in the
Capture-RD state and then is placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instruction can be used to activate the Boundary Scan Register.
Identification (ID) Register
The ID register is a 32-bit register that is loaded with a device and vender specific 32-bit code when the controllers put in the
Capture-DR state with the IDCODE Instruction loaded in the Instruction Register. The code is loaded from 32-bit on-chip ROM. It
describes various attributes of the SRAM (see page 20). The register is then placed between the TDI and TDO pins when the controller
is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach the TDO pin when shifting begins.
TAP Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; standard (Public) instructions, and device specific (Private)
instructions. Some public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in
prescribed ways. The TAP Controller in this device is not fully 1194.1-compliant because some of the mandatory 1149.1 instructions are
not fully implemented. The TAP on this device may be used to monitor all input and I/O pads. This device will not perform INTEST or
PRELOAD portion of the SAMPLE/PRELOAD command.
When the TAP controller is placed in the Shift-IR state, the Instruction Register is placed between the TDI and TDO pins. In this state
the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at the TDO output). For all
instructions, the TAP executes newly loaded instructions only when the controller is moved to the Update-IR state. The TAP Instruction
Set for this device is listed in the following table.
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register, the Bypass Register is placed between the TDI and TDO pins. This
occurs when the TAP Controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the
Instruction Register, moving the TAP Controller into the Capture-DR state loads the data in the SRAM's input and I/O buffers into the
Boundary Scan Register. Because the SRAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to
capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results cannot be expected. SRAM input signals must be stabilized for long
enough to meet the TAP's input data capture set-up plus hold time (tTS plus tTH). The SRAM's clock inputs need not be paused for any
other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to the Shift-DR state
then places the Boundary Scan Register between the TDI and TDO pins. Because the PRELOAD portion of the command is not
implemented in this device, moving the controller to the Update-DR state with the SAMPLE/PRELOAD instruction loaded in the
Instruction Register has the same effect as the Pause-DR command. This functionality is not Standard 1149.1 compliant.
16/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the Instruction Register is loaded with all logic
0s. EXTEST is not implemented in the TAP Controller, and therefore this device is not compliant to the 1149.1 Standard. When the
EXTEST instruction is loaded into the Instruction Register, the device responds as if the SAMPLE/PRELOAD instruction has been
loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST place the SRAM
outputs in a High-Z state.
IDCODE
The IDCODE instruction cause the ID ROM to be loaded into the ID register when the controller is in the Capture-DR state and places
the ID Register between the TDI and TDO pins in the Shift-DR state. The IDCODE instruction is the default instruction loaded in at
power-up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the Instruction Register, all SRAM outputs are forced to an inactive drive state (High-Z) and the
Boundary Scan Register is placed between the TDI and TDO pins when the TAP Controller is moved to the Shift-DR state.
RFU
These instructions are reserved for future use. Do not use these instructions.
JTAG TAP BLOCK DIAGRAM
Bypass Register
0
Instruction Register
2 1 0
TDI
Identification Register
TDO
31 30 29 . . . . . . . . 2 1 0
Boundary Scan Register
.. .............. .. 2 1 0
TMS
TCK
Test Access Port (TAP) Controller
17/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
BOUNDARY SCAN ORDER
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Bump
8P
8R
9P
9R
10P
10R
11R
11N
11M
10M
10L
11L
10K
11K
10J
11J
11H
7N
11G
10G
11F
10F
11E
10E
11D
10D
11C
Pin Name
A15
A16
A13
A14
A11
A12
A10
DQPa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
MCH
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
Bit
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Bump
10A
10B
9A
9B
8A
8B
7A
7B
6B
6A
5B
5A
4A
4B
3B
3A
2A
2B
1C
1D
2D
1E
2E
1F
2F
1G
2G
Pin Name
A8
A9
A17
A18
ADV
G#
CKE#
W#
CLK
E3#
Bwa#
BWb#
BWc#
BWd#
E2
E1#
A7
A6
DQPc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
Bit
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Bump
1H
2H
2J
1J
2K
1K
1L
2L
1M
2M
1N
1R
3R
3P
4R
4P
6P
6R
Pin Name
MCH
MCH
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
LBO#
A4
A5
A2
A3
A1
A0
18/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
JTAG TAP CONTROLLER STATE DIAGRAM
Test-Logic-Reset
1
0
Run-Test/Idle
1
Select-DR-Scan
0
1
Select-IR-Scan
0
1
0
1
Capture-DR
0
Capture-IR
0
Shift-DR
Shift-IR
0
1
1
0
1
1
Exit1-DR
Exit1-IR
0
0
Pause-DR
Pause-IR
0
1
Exit2-DR
0
0
1
Exit2-IR
1
0
1
Update-DR
1
1
Update-IR
0
1
0
TAP CONTROLLER DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=2.375~2.625V, unless otherwise noted)
Limits
Min
Max
Test Port Input High Voltage
0.65*VDDQ
VDDQ+0.3 **
VIHT
Test Port Input Low Voltage
-0.3 **
0.35*VDDQ
VILT
Test Port Output High Voltage
IOH=-100µA
VDDQ-0.1
VOHT
Test Port Output Low Voltage
IOL=+100µA
0.1
VOLT
TMS, TCK and TDI Input Leakage Current
-10
10
IINT
TDO Output Leakage Current
Output Disable, VOUT=0V~VDDQ
-10
10
IOLT
Note38. **Input Undershoot/Overshoot voltage must be -1V<Vi<VDDQ+1V with a pulse width not to exceed 20% tTCK.
Symbol
Parameter
Condition
Unit
V
V
V
V
µA
µA
19/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
TAP CONTROLLER AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=2.375~2.625V, unless otherwise noted)
(1)MEASUREMENT CONDITION
Input pulse levels ········································ VIH=VDDQ, VIL=0V
Input rise and fall times ······························· faster than or equal to 1V/ns
Input timing reference levels ······················· VIH=VIL=0.5*VDDQ
Output reference levels ·······························VIH=VIL=0.5*VDDQ
Output load ·················································· Fig.4
30pF
(Including wiring and JIG)
Q
ZO=50Ω
50Ω
VT=0.5*VDDQ
Fig.4 Output load
(2)TIMING CHARACTERISTICS
Symbol
Limits
Min
Max
20
50
20
20
10
10
20
Parameter
tTF
tTKC
tTKH
tTKL
tTS
tTH
tTKQ
TCK Frequency
TCK Cycle Time
TCK High Pulse Width
TCK Low Pulse Width
TDI, TMS setup time
TDI, TMS hold time
TCK Low to TDO valid
Unit
MHz
ns
ns
ns
ns
ns
ns
(3) TIMING
tTKC
tTKH
tTKL
TCK
tTS tTH
TMS
tTS tTH
TDI
tTKQ
TDO
20/24
Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
JTAG TAP INSTRUCTION SET SUMMARY
Instruction
Code
EXTEST
000
IDCODE
001
SAMPLE-Z
010
RFU
011
SAMPLE/PRELOAD
100
RFU
RFU
BYPASS
101
110
111
Description
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
Preloads ID Register and places it between TDI and TDO
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all Data output drivers to High-Z
Do not use this instruction; Reserved for Future Use.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
This instruction dose not implement 1149.1 preload function and is therefore not 1149.1-compliant.
Do not use this instruction; Reserved for Future Use.
Do not use this instruction; Reserved for Future Use.
Places the BYPASS Register between TDI and TDO.
STRUCTURE OF IDENTIFICATION REGISTER
Revision
Device Information
Capacity
Function
VDD
Width
Gen.
JEDEC Vendor Code of MITSUBISHI
Bit No.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
M5M5T5636
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
MSB
0
1
LSB
Note39. Bit of Device Information “Gen.(Generation)” means
Bit No.
1st Generation
2nd Generation
3rd Generation
13
0
0
1
12
0
1
0
Note40. Bit of Device Information ”Width” means
Bit No.
X16
X18
X32
X36
X64
X72
16
0
0
0
0
1
1
15
0
0
1
1
0
0
14
0
1
0
1
0
1
Note41. Bit of Device Information ”Function” means
Bit No.
Network SRAM
PB
20
0
0
19
1
0
18
0
0
17
0
1
Note42. Bit of Device Information ”Capacity” means
Bit No.
1M or 1.15M
2M or 2.3M
4M or 4.5M
8M or 9M
16M or 18M
32M or 36M
24
0
0
0
0
0
0
23
0
0
0
1
1
1
22
0
1
1
0
0
1
21
1
0
1
0
1
0
Note43. Bit of Device Information ”VDD” means
Bit No.
3.3V
2.5V
1.8V
1.5V
27
0
0
0
0
26
0
0
1
1
25
0
1
0
1
21/24
Preliminary
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MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
PACKAGE OUTLINE
165(11x15) bump Ball Grid Array(BGA) Pin Pitch 1.00mm
Refer to JEDEC Standard MO-216, Variation CAB-1,
which can be seen at:
http://www.jedec.org/download/search/MO-216c.pdf
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Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
REVISION HISTORY
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
History
First revision
Changed VDD to VDDQ about specification associated with
VI / VO in electrical characteristics
Fixed WRITE TRUTH TABLE
and ABSOLUTE MAXIMUM RATINGS
ABSOLUTE MAXIMUM RATINGS
Changed TSTG from -65~150 to -55~125
Fixed THERMAL RESISTANCE
DC ELECTRICAL CHARACTERISTICS
Changed VIH limit from 0.65VDDQ to 1.7 at 2.5V VDDQ
Changed VIL limit from 0.35VDDQ to 0.7 at 2.5V VDDQ
Changed ICC1 limit from 400mA to 560mA at 250MHz(-25)
Changed ICC1 limit from 380mA to 500mA at 225MHz(-22)
Changed ICC1 limit from 360mA to 440mA at 200MHz(-20)
Changed ICC2 limit from 140mA to 260mA at 250MHz(-25)
Changed ICC2 limit from 110mA to 220mA at 225MHz(-22)
Changed ICC2 limit from 100mA to 180mA at 200MHz(-20)
Changed ICC5 limit from 70mA to 180mA at 250MHz(-25)
Changed ICC5 limit from 60mA to 160mA at 225MHz(-22)
Changed ICC5 limit from 50mA to 140mA at 200MHz(-20)
AC ELECTRICAL CHARACTERISTICS
Changed tKHQX limit from 0.5ns to 1.5ns at 250MHz(-25)
Changed tKHQX limit from 0.6ns to 1.5ns at 225MHz(-22)
Changed tKHQX limit from 0.7ns to 1.5ns at 200MHz(-20)
Changed tKHQX1 limit from 0.5ns to 1.5ns at 250MHz(-25)
Changed tKHQX1 limit from 0.6ns to 1.5ns at 225MHz(-22)
Changed tKHQX1 limit from 0.7ns to 1.5ns at 200MHz(-20)
Changed tKHQZ limit from 0.5ns to 1.5ns at 250MHz(-25)
Changed tKHQZ limit from 0.6ns to 1.5ns at 225MHz(-22)
Changed tKHQZ limit from 0.7ns to 1.5ns at 200MHz(-20)
Added Boundary Scan Order
DC ELECTRICAL CHARACTERISTICS
Changed ILI limit from 10uA to 100uA
(Input Leakage Current of ZZ and LBO#)
Changed Icc3 and Icc4 limit from 20mA to 30mA
(Standby Current)
Date
March 16, 2001
Advanced Information
March 30, 2001
Advanced Information
July 16, 2001
Advanced Information
March 28, 2002
Advanced Information
July 5, 2002
Preliminary
August 8, 2002
Preliminary
September 3, 2002
Preliminary
January 14, 2003
Preliminary
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Preliminary
M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility
that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due
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