RENESAS 7549_09

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April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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7549 Group
REJ03B0202-0202
Rev.2.02
Mar 31, 2009
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7549 Group is the 8-bit microcomputer based on the 740
family core technology.
The 7549 Group has an 8-bit timer, 16-bit timer, serial interface,
A/D converter, power-on reset circuit and the low voltage
detection circuit. Also, the Function set ROM is equipped.
FEATURES
• Basic machine-language instructions ..................................71
• The minimum instruction execution time ................... 0.25 µs
(at 8 MHz oscillation frequency, double-speed mode)
• Memory size
ROM ..................................... 2K, 4K, 6K bytes
RAM ........................................... 192/256 bytes
• Programmable I/O ports
I/O port............................................................19
Output port........................................................1
• Key-on wakeup .......................................................................8
• LED direct drive port..............................................................8
• Interrupts ............................................. 12 sources, 12 vectors
• Timers ....................................................................... 8-bit × 2
..................................................................................16-bit × 1
• Output compare ........................................................ 3 channel
• Input capture ............................................................. 1 channel
• Serial interface............................................................ 8-bit × 1
(UART or clock synchronous)
• A/D converter ............................ 10-bit resolution × 8-channel
• Clock generating circuit ..................................... Built-in type
(connect to external ceramic resonator or quartz-crystal oscillator,
32 kHz quartz-crystal oscillation available)
• High-speed on-chip oscillator ............................ Typ. : 4 MHz
• Low-speed on-chip oscillator .......................... Typ. : 250 kHz
• Watchdog timer ...................................................... 16-bit × 1
• Power-on reset circuit.......................................... Built-in type
• Low voltage detection circuit .............................. Built-in type
• Power source voltage
XIN oscillation frequency
(at ceramic resonator, in double-speed mode)
At 8 MHz ........................................ 4.5 to 5.5 V
At 2 MHz ........................................ 2.4 to 5.5 V
At 1 MHz ........................................ 2.2 to 5.5 V
XIN oscillation frequency
(at ceramic resonator, in high-speed mode)
At 8 MHz ........................................ 4.0 to 5.5 V
At 4 MHz ........................................ 2.4 to 5.5 V
At 1 MHz ........................................ 1.8 to 5.5 V
High-speed on-chip oscillator oscillation frequency
At 4 MHz......................................... 4.0 to 5.5 V
Low-speed on-chip oscillator oscillation frequency
At 250 kHz (typ. value at VCC = 5V).... 1.8 to 5.5 V
• Power dissipation ........................................................ 30 mW
• Operating temperature range ............................... -20 to 85°C
APPLICATION
Office automation equipment, factory automation equipment,
home electric appliances, consumer electronics, etc.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 1 of 81
7549 Group
PIN Configuration (top view)
1
24
P13/AN3/KEY3/T2OUT
P15/AN5/KEY5
2
23
P12/AN2/KEY2/CMP2
RESET
3
22
P11/AN1/KEY1/CMP1
21
P10/AN0/KEY0/CMP0
20
P31
19
P30
P16/AN6/KEY6
4
P17/AN7/KEY7
P20/XOUT/XCOUT
5
6
VSS
P21/XIN/XCIN
7
8
M37549G3/G2/G1FP
P14/AN4/KEY4
18
17
P06(LED6)/SCLK
16
P05(LED5)/TxD
VCC
9
CNVSS
10
15
P04(LED4)/RxD
P00(LED0)/INT0
11
14
P03(LED3)/CAP0
P01(LED1)/INT1
12
13
P02(LED2)
Package type: PRSP0024GA-A (24P2Q-A)
Fig 1.
P07(LED7)/SRDY
Pin configuration (PRSP0024GA-A type)
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 2 of 81
7549 Group
PIN Configuration (top view)
1
42
NC
NC
2
41
NC
NC
3
40
P13/AN3/KEY3/T2OUT
P14/AN4/KEY4
4
39
P12/AN2/KEY2/CMP2
P15/AN5/KEY5
5
38
P11/AN1/KEY1/CMP1
RESET
6
37
P10/AN0/KEY0/CMP0
P16/AN6/KEY6
7
36
P31
P17/AN7/KEY7
8
35
NC
9
34
P30
NC
NC
10
33
NC
32
NC
31
NC
30
P07(LED7)/SRDY
29
P06(LED6)/SCLK
NC
P20/XOUT/XCOUT
VSS
P21/XIN/XCIN
11
12
13
14
M37549RLSS
NC
VCC
15
28
P05(LED5)/TxD
CNVSS
16
27
P04(LED4)/RxD
P00(LED0)/INT0
17
26
P03(LED3)/CAP0
P01(LED1)/INT1
18
25
P02(LED2)
NC
19
24
NC
NC
20
23
NC
VSS
21
22
NC
Package type: 42S1M
Fig 2.
Pin configuration (42S1M type)
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 3 of 81
7549 Group
PERFORMANCE OVERVIEW
Table 1
Performance overview
Parameter
Function
Number of basic instructions
71
Instruction execution time
0.25 µs (Minimum instruction, oscillation frequency 8MHz, double-speed mode)
Oscillation frequency
8 MHz (Maximum)
Memory sizes
ROM
RAM
I/O port
Interrupts
M37549G1
2K bytes × 8 bits
M37549G2
4K bytes × 8 bits
M37549G3
6K bytes × 8 bits
M37549G1
192 bytes × 8 bits
M37549G2
256 bytes × 8 bits
M37549G3
256 bytes × 8 bits
P00-P07 I/O
1-bit × 8, LED direct drive ports
P10-P17 I/O
1-bit × 8
P20
Output
1-bit × 1
P21
I/O
1-bit × 1
P30, P31 I/O
1-bit × 2
Source
12 sources, 12 vectors
8-bit × 2, 16-bit × 1
Timer
Output compare
3-channel
Input capture
1 channel
Serial interface
8-bit × 1 (UART or clock synchronous)
A/D converter
10-bit resolution × 8 channel
Watchdog timer
16-bit × 1
Power-on reset circuit
Built-in
Low voltage detection circuit
Built-in
Clock generating circuit
Built-in (external ceramic resonator or quartz-crystal oscillator, external 32-kHz
quartz-crystal oscillator available) (built-in high/low-speed on-chip oscillator)
Function set ROM
area
Function set ROM
Function set ROM is assigned to address FFD816 to FFDA16.
Valid/invalid of low voltage detection circuit can be selected.
Oscillation mode can be selected.
Enable/disable of watchdog timer and STP instruction can be selected.
ROM code protect
ROM code protect is assigned to address FFDB16.
Read/write the built-in QzROM by serial programmer is disabled by setting “00”
to ROM code protect.
Double- at 8 MHz oscillation
speed
at 2 MHz oscillation
mode
at 1 MHz oscillation
4.5 to 5.5 V
at 8 MHz oscillation
4.0 to 5.5 V
at 4 MHz oscillation
2.4 to 5.5 V
at 1 MHz oscillation
1.8 to 5.5 V
Power source
voltage
(at high-speed onchip oscillator)
Double- at 4 MHz oscillation
speed
mode
4.0 to 5.5 V
Power source
voltage
(at low-speed onchip oscillator)
Double- at 250 kHz oscillation
speed
mode
1.8 to 5.5 V
Power source
voltage
(at ceramic
resonator)
Highspeed
mode
2.4 to 5.5 V
2.2 to 5.5 V
Power dissipation
30 mW (Typ.)
Operating temperature range
-20 to 85 °C
Device structure
CMOS silicon gate
Package
24-pin plastic molded SSOP (PRSP0024GA-A)
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 4 of 81
Fig 3.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
FUNCTIONAL BLOCK DIAGRAM
Page 5 of 81
P3(2)
0
I/O port P3
20 19
8 6
P2(2)
0
I/O port P2
A/D converter
(10)
ROM
Clock input Clock output
X IN /X CIN X OUT /X COUT
Clock
generating
circuit
Reset
Reset
Low voltage
detection circuit
Watchdog timer
Reset
Power-on reset circuit
RAM
P1(8)
PS
PC L
S
Y
X
A
I/O port P1
5 4 2 1 24 23 22 21
PC H
9
7
C P U
V CC
V SS
FUNCTIONAL BLOCK DIAGRAM (Package: PRSP0024GA-A)
Key-on wakeup
Compare
(16)
3
Reset input
RESET
SIO (8)
I/O port P0
18 17 16 15 14 13 12 11
P0(8)
Timer A(16)
Prescaler 12 (8)
10
CNV SS
Capture
(16)
INT 1
INT 0
Timer 2 (8)
Timer 1(8)
7549 Group
7549 Group
PIN DESCRIPTION
Table 2
Pin description
Pin
Name
Function
Function except a port function
VCC,VSS
Power source
Apply voltage of 1.8 to 5.5 V to Vcc, and 0 V to Vss.
CNVSS
CNVSS
Controls the operation mode of the chip. Connected to VSS.
RESET
P00(LED0)/INT0
P01(LED1)/INT1
Reset input
Reset input pin for active “L”
I/O port P0
Interrupt input pin
•8-bit I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
Capture input pin
•CMOS compatible input level
•CMOS 3-state output structure
Serial interface function pin
•Whether a built-in pull-up resistor is to be used or not
can be determined by program.
•High drive capacity for LED drive port can be
selected by program.
I/O port P1
Input pins
•8-bit I/O port.
•I/O direction register allows each pin to be individu- for A/D
converter
ally programmed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•Whether a built-in pull-up resistor is to be used or not
can be determined by program.
P02(LED2)
P03(LED3)/CAP0
P04(LED4)/RXD
P05(LED5)/TXD
P06(LED6)/SCLK
P07(LED7)/SRDY
P10/AN0/KEY0/CMP0
P11/AN1/KEY1/CMP1
P12/AN2/KEY2/CMP2
P13/AN3/KEY3/T2OUT
P14/AN4/KEY4
P15/AN5/KEY5
P16/AN6/KEY6
P17/AN7/KEY7
Key-input
(key-on
wake up
interrupt
input) pin
Compare
output
pin
Timer 2
output
pin
Pins XIN and XOUT, or pins XCIN
and XCOUT, can be used as clock
pins by connecting a ceramic
resonator, crystal oscillator, or 32
kHz crystal oscillator between
them. Alternately, an external
clock may be input to the
P20/XOUT/XCOUT pin. In this case,
the P21/XIN/XCIN pin can be used
as an I/O port.
P20/XOUT/XCOUT
P21/XIN/XCIN (Note)
I/O port P2
•2-bit I/O port. (P20/XOUT/XCOUT is only for output)
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•Function set ROM allows pins to be used as clock
pins.
P30, P31
I/O port P3
•2-bit I/O port.
•I/O direction register allows each pin to be individually programmed as either input or
output.
•CMOS compatible input level
•CMOS 3-state output structure
NOTE:
1. The oscillation circuit is built in the P20/XOUT/XCOUT pin and the P21/XIN/XCIN pin. When the Vcc of the microcomputer is lower than
the operation lower bound voltage even if these pins are used as I/O ports, the oscillation circuit is connected and undefined values
may be output from these pins.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 6 of 81
7549 Group
GROUP EXPANSION
Memory Size
• ROM size ........................................................ 2K to 6K bytes
• RAM size ..................................................... 192 to 256 bytes
Renesas plans to expand the 7549 group as follow:
Memory Type
Support for QzROM version and emulator MCU.
Packages
• PRSP0024GA-A .... 0.8 mm-pitch 24-pin plastic molded SSOP
• 42S1M ......................... 42-pin shrink ceramic PIGGY BACK
ROM size
(bytes)
6K
M37549G3
4K
M37549G2
M37549G1
2K
0
Fig 4.
192
256
RAM size
(bytes)
Memory expansion plan
Currently supported products are listed below.
Table 3
As of Mar. 2009
List of supported products
Part number
M37549G3-XXXFP
M37549G3FP
M37549G2-XXXFP
M37549G2FP
M37549G1-XXXFP
M37549G1FP
M37549RLSS
NOTE:
ROM size (bytes)
ROM size for User ()
RAM size
(bytes)
Package
6144
(6014)
256
PRSP0024GA-A
4096
(3966)
256
PRSP0024GA-A
2048
(1918)
192
PRSP0024GA-A
−
256
42S1M
1. ROM size includes the function set ROM.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 7 of 81
Remarks
QzROM version
QzROM version (blank)
QzROM version
QzROM version (blank)
QzROM version
QzROM version (blank)
Emulator MCU
7549 Group
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The MCU uses the standard 740 family instruction set. Refer to
the table of 740 family addressing modes and machine-language
instructions or the SERIES 740 <SOFTWARE> USER’S
MANUAL for details on each instruction set.
Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions cannot be used.
2. The MUL and DIV instructions can be used.
3. The WIT instruction can be used.
4. The STP instruction can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index register X (X), Index register Y (Y)]
Both index register X and index register Y are 8-bit registers. In
the index addressing modes, the value of the OPERAND is
added to the contents of register X or register Y and specifies the
real address.
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the
second OPERAND.
b7
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt
routines.
The lower eight bits of the stack address are determined by the
contents of the stack pointer. The upper eight bits of the stack
address are determined by the Stack Page Selection Bit. If the
Stack Page Selection Bit is “0”, then the RAM in the zero page is
used as the stack area. If the Stack Page Selection Bit is “1”, then
RAM in page 1 is used as the stack area.
The Stack Page Selection Bit is located in the SFR area in the
zero page. Note that the initial value of the Stack Page Selection
Bit varies with each microcomput er type. Al so some
microcomputer types have no Stack Page Selection Bit and the
upper eight bits of the stack address are fixed. The operations of
pushing register contents onto the stack and popping them from
the stack are shown in Figure 6.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
b0
A
b7
Accumulator
b0
X
b7
Index Register X
b0
Y
b7
Index Register Y
b0
S
b7
b15
b0
PCL
PCH
Stack Pointer
Program Counter
b7
b0
N V T B D I Z C Processor Status Register (PS)
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Fig 5.
740 Family CPU register structure
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 8 of 81
7549 Group
On-going Routine
Interrupt request
(Note)
M(S)←(PCH)
Store Return Address
on Stack
(S)←(S) − 1
Execute JSR
M(S)←(PCL)
Store Return
Address
on Stack
M(S)←(PCH)
(S)←(S) − 1
(S)←(S) − 1
M(S)←(PS)
M(S)←(PCL)
Store Contents of
Processor
Status Register on Stack
(S)←(S) − 1
(S)←(S) − 1
Interrupt
Service Routine
.....
Subroutine
I Flag “0” to “1”
Fetch the Jump Vector
.....
Execute RTI
Execute RTS
(S)←(S) + 1
Restore Return
Address
(S)←(S) + 1
Restore Contents of
Processor Status Register
(PS)←M(S)
(PCL)←M(S)
(S)←(S) + 1
(S)←(S) + 1
(PCL)←M(S)
(PCH)←M(S)
Restore Return
Address
(S)←(S) + 1
(PCH)←M(S)
Note : The condition to enable the interrupt → Interrupt enable bit is “1”
Interrupt disable flag is “0”
Fig 6.
Table 4
Register push and pop at interrupt generation and subroutine call
Push and pop instructions of accumulator or processor status register
Push instruction to stack
PHA
PHP
Accumulator
Processor status register
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 9 of 81
Pop instruction from stack
PLA
PLP
7549 Group
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of flags
which indicate the status of the processor after an arithmetic
operation. Branch operations can be performed by testing the
Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative
(N) flag. In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other
flags are undefined. Since the Index X mode (T) and Decimal
mode (D) flags directly affect arithmetic operations, they should
be initialized in the beginning of a program.
Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the
arithmetic logic unit (ALU) immediately after an arithmetic
operation. It can also be changed by a shift or rotate instruction.
Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic
operation or a data transfer is “0”, and cleared if the result is
anything other than “0”.
Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction. Interrupts are disabled
when the I flag is “1”.
When an interrupt occurs, this flag is automatically set to “1”
to prevent other interrupts from interfering until the current
interrupt is serviced.
Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the
ADC and SBC instructions can be used for decimal arithmetic.
Table 5
C flag
SEC
CLC
Z flag
−
−
I flag
SEI
CLI
[CPU mode register] CPUM
The CPU mode register contains the stack page selection bit.
This register is allocated at address 003B16.
b0
CPU mode register
(CPUM: address 003B16, initial value: 0016)
Processor mode bits
b1b0
0 0:
0 1:
1 0:
1 1:
Single-chip mode
Not available
Not available
Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Disable (returns “0” when read)
Fig 7.
Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory, e.g. the results of an
operation between two memory locations is stored in the
accumulator. When the T flag is “1”, direct arithmetic
operations and direct data transfers are enabled between
memory locations, i.e. between memory and memory,
memory and I/O, and I/O and I/O. In this case, the result of
an arithmetic operation performed on data in memory
location 1 and memory location 2 is stored in memory
location 1. The address of memory location 1 is specified by
index register X, and the address of memory location 2 is
specified by normal addressing modes.
Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one
byte of signed data. It is set if the result exceeds +127 to 128. When the BIT instruction is executed, bit 6 of the
memory location operated on by the BIT instruction is stored
in the overflow flag.
Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or
data transfer is negative. When the BIT instruction is
executed, bit 7 of the memory location operated on by the
BIT instruction is stored in the negative flag.
Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
b7
Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the
processor status register is always “0”. When the BRK
instruction is used to generate an interrupt, the processor
status register is pushed onto the stack with the break flag set
to “1”. The saved processor status is the only place where the
break flag is ever set.
Structure of CPU mode register
The processor mode bits can be written only once after releasing reset.
Always set them to “002”. After written, rewriting any data to these
bits is disabled because they are locked. (Emulator MCU is excluded.)
Also, the stack page selection bit (bit 2) is not locked.
In order to prevent error-writing to the processor mode bits (at
program runaway), write the CPU mode register at the start of
the program that runs after releasing reset.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 10 of 81
D flag
SED
CLD
B flag
−
−
T flag
SET
CLT
V flag
−
CLV
N flag
−
−
7549 Group
Memory
• Special Function Register (SFR) Area
The SFR area in the zero page contains control registers such as
I/O ports and timers.
• RAM
RAM is used for data storage and for a stack area of subroutine
calls and interrupts.
• ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
The user area includes the function set ROM area.
• Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
• Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function
registers (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
• Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be used
to specify memory addresses in the special page area. Access to
this area with only 2 bytes is possible in the special page
addressing mode.
• Function set ROM Area
[Renesas shipment test area]
Figure 8 shows the Assignment of Function set ROM area.
The random data are set to the Renesas shipment test areas
(addresses FFD416 to address FFD716).
Do not rewrite the data of these areas.
When the checksum is included in the user program, avoid
assigning it to these areas.
[Function set ROM data] FSROM0, FSROM1, FSROM2
Function set ROM data 0 to 2 (addresses FFD816 to FFDA16) are
used to set modes of peripheral functions.
By setting values to these areas, the operation mode of each
peripheral function are set after releasing reset.
Refer to the descriptions of peripheral functions for the details of
operation of peripheral functions.
• Clock generating circuit (page 46)
• Watchdog timer (page 42)
• Low voltage detection circuit (page 44)
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 11 of 81
[ROM code protect]
Address FFDB 16 of QzROM version is ROM code protect
address and cannot be used for programming. “0016” is written
into this address when selecting the protect bit write by using a
serial programmer and selecting protect enabled for writing
shipment by Renesas Technology corp.. When “0016” is set to
the ROM code protect address, the protect function is enabled, so
that reading or writing from/to the corresponding area is disabled
by a serial programmer.
As for the QzROM product in blank, the ROM code is protected by
selecting the protect bit write at ROM writing with a serial programmer.
As for the QzROM product shipped after writing, “0016” (protect
enabled) or “FF16” (protect disabled) is written into the ROM code
protect address when Renesas Technology corp. performs writing.
The writing of “0016” or “FF16” can be selected as ROM option setup
(“MASK option” written in the mask file converter) when ordering.
<Notes>
(1) Because the contents of RAM are indefinite at reset, set
initial values before using.
(2) Do not access to the reserved area.
(3) Random data is written into the Renesas shipment test area
and the reserved ROM area. Do not rewrite the data in these
areas. Data of these area may be changed without notice.
Accordingly, do not include these areas into programs such
as checksum of all ROM areas.
(4) The QzROM values in function set ROM data 0 to 2 set the
operating modes of the various peripheral functions after an
MCU reset is released. Do not fail to set the value for the
selected function. Bits designated with a fixed value of 1 or
0 must be set to the designated value.
7549 Group
User ROM area
000016
RAM area
RAM capacity
(bytes)
192
address
XXXX16
00FF16
256
013F16
SFR area
004016
010016
RAM
ROM area
ROM capacity
(bytes)
address
YYYY16
address
ZZZZ16
2048
F80016
F88016
4096
F00016
F08016
6144
E80016
E88016
XXXX16
Reserved area
044016
Disable
YYYY16
Function set ROM
Address
FFD416
FFD516
FFD616
FFD716
FFD816
FFD916
FFDA16
FFDB16
Zero page
Renesas shipment test area
Renesas shipment test area
Renesas shipment test area
Renesas shipment test area
Function set ROM data 0
Function set ROM data 1
Function set ROM data 2
ROM code protect
Reserved ROM area
(128 bytes)
ZZZZ16
ROM
FF0016
FFD416
Function set ROM area
Special page
FFDC16
Interrupt vector area
FFFE16
FFFF16
Fig 8.
Memory map diagram
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 12 of 81
Reserved ROM area
7549 Group
000016 Port P0 (P0)
000116 Port P0 direction register (P0D)
002016
Reserved
002116
Reserved
000216 Port P1 (P1)
000316 Port P1 direction register (P1D)
002216
Reserved
002316
Reserved
000416
Port P2 (P2)
002416
Reserved
000516
Port P2 direction register (P2D)
002516
Reserved
000616 Port P3 (P3)
000716 Port P3 direction register (P3D)
002616
Reserved
002716
Reserved
000816 Reserved
000916 Reserved
002816
Prescaler 12 (PRE12)
002916
Timer 1 (T1)
000A16 Reserved
000B16 Reserved
002A16
Timer 2 (T2)
002B16
Timer mode register (TM)
000C16 Port P0 drive capacity control register (DCCR)
000D16 Port P0 pull-up control register (PULL0)
002C16 Timer count source set register (TCSS)
002D16 Compare register re-load register (CMPR)
000E16 Port P1 pull-up control register (PULL1)
000F16 Key-on wakeup input selection register (KEYS)
002E16
Capture/Compare port register (CCPR)
002F16
Capture/Compare status register (CCSR)
001016 Capture/Compare register (low-order) (CRAL)
001116 Capture/Compare register (high-order) (CRAH)
003016
Compare interrupt source set register (CISR)
003116
Capture software trigger register (CSTR)
001216 Capture/Compare register RW pointer (CCRP)
001316 Compare output mode register (CMOM)
003216
Capture mode register (CAPM)
003316
Reserved
001416 Timer A (low-order) (TAL)
001516 Timer A (high-order) (TAH)
003416
AD control register (ADCON)
003516
AD conversion register (low-order) (ADL)
003616
AD conversion register (high-order) (ADH)
001716 Reserved
001816 Transmit/Receive buffer register (TB/RB)
003716
Clock mode register (CLKM)
003816
Oscillation stop detection register (CLKSTP)
001916 Serial I/O status register (SIOSTS)
001A16 Serial I/O control register (SIOCON)
003916
Watchdog timer control register (WDTCON)
003A16
Interrupt edge selection register (INTEDGE)
001B16 UART control register (UARTCON)
001C16 Baud rate generator (BRG)
003B16
CPU mode register (CPUM)
001616
Reserved
001D16 Reserved
001E16 Reserved
001F16 Reserved
Note 1: Do not access to the reserved addresses.
Fig 9.
Memory map of special function register (SFR)
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REJ03B0202-0202
Page 13 of 81
003C16 Interrupt request register 1 (IREQ1)
003D16 Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
7549 Group
b7
b0
Function set ROM data 0
(FSROM0: address FFD816)
Low voltage detection circuit valid bit
0: Low voltage detection circuit invalid
1: Low voltage detection circuit valid
Set “0” to this bit certainly.
Set “1” to this bit certainly.
Fig 10. Structure of Function set ROM data 0
b7
b0
Function set ROM data 1
(FSROM1: address FFD916)
Oscillation method selection bits (Note 1)
b1 b0
0 0: Clock pins not used (P20/XOUT and P21/XIN are used as
I/O ports)
0 1: Ceramic resonator or quarts-crystal oscillator
1 0: 32 kHz quarts-crystal oscillator
1 1: External clock input (P21/XIN pin is used as I/O port)
Low voltage detection circuit valid bit in the stop mode (Note 2)
0: Low voltage detection circuit invalid in the stop mode
1: Low voltage detection circuit valid in the stop mode
Set “0” to these bits certainly.
Set “1” to this bit certainly.
Notes 1: The P20/XOUT and P21/XIN pins build in an on-chip oscillator. Even if these pins are used
as I/O ports, the oscillator circuit is enabled when the MCU’s Vcc voltage drops below
the operation limit voltage. In this case these pins may output undefined values.
2: When the Low voltage detection circuit is set to be valid in the stop mode, the dissipation
current in the stop mode is increased.
Fig 11. Structure of Function set ROM data 1
b7
b0
Function set ROM data 2
(FSROM2: address FFDA16)
Watchdog timer source clock selection bit
0 : Low-speed on-chip oscillator/16
1 : φSOURCE/16
Watchdog timer disable bit
0 : Watchdog timer enabled
1 : Watchdog timer disabled
Watchdog timer H count source initial value
selection bit
0 : Initial value of bit 7 of WDTCON
after reset release is “0”
1 : Initial value of bit 7 of WDTCON
after reset release is “1”
STP instruction function selection bit
0 : System enters into the stop mode
at the STP instruction execution
1 : Internal reset occurs at the STP
instruction execution
Low-speed on-chip oscillator control bit
(Note 1)
0 : Stop of low-speed on-chip oscillator
disabled
1 : Stop of low-speed on-chip oscillator
enabled
Set “0” to these bits certainly.
Note 1: If “0” is set to this bit, it is not possible to write “1” to bit 0 in the clock
mode register. Also, the low-speed on-chip oscillator does not stop
even if in the stop mode.
Fig 12. Structure of Function set ROM data 2
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 14 of 81
7549 Group
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/
output direction of each pin. Each bit in a direction register
corresponds to one pin, and each pin can be set to be input or
output.
When “1” is set to the bit corresponding to a pin, this pin
becomes an output port. When “0” is set to the bit, the pin
becomes an input port.
When data is read from a pin set to output, not the value of the
pin itself but the value of port latch is read. Pins set to input are
floating, and permit reading pin values.
If a pin set to input is written to, only the port latch is written to
and the pin remains floating.
If the port P20 is used as output port, write “1” to the port P20
direction register after reset.
[Port P0 drive capacity control register] DCCR
By setting the Port P0 drive capacity control register (address
000C16), the drive capacity of the N-channel output transistor for
the port P0 can be selected.
b7
b0
Port P0 drive capacity control register
(DCCR: address 000C16, initial value: 0016)
Port P00 drive capacity selection bit
Port P01 drive capacity selection bit
Port P02 drive capacity selection bit
Port P03 drive capacity selection bit
Port P04 drive capacity selection bit
Port P05 drive capacity selection bit
Port P06 drive capacity selection bit
Port P07 drive capacity selection bit
0: weakness
1: strength
Fig 13. Structure of port P0 drive capacity control
register
b7
b0
Port P0 pull-up control register
(PULL0: address 000D16, initial value: 0016)
[Pull-up control registers] PULL0, PULL1
By setting the pull-up control registers (address 000D16 and
000E16), ports P0 and P1 can exert pull-up control by program.
However, this is valid only when the port direction registers are
set to input.
When they are set to output, setting “pull-up on” does not pull up
the ports.
P00 pull-up control bit
P01 pull-up control bit
P02 pull-up control bit
P03 pull-up control bit
P04 pull-up control bit
P05 pull-up control bit
P06 pull-up control bit
P07 pull-up control bit
0: Pull-up is disabled
1: Pull-up is enabled
Fig 14. Structure of port P0 pull-up control register
b7
b0
Port P1 pull-up control register
(PULL1: address 000E16, initial value: 0016)
P10 pull-up control bit
P11 pull-up control bit
P12 pull-up control bit
P13 pull-up control bit
P14 pull-up control bit
P15 pull-up control bit
P16 pull-up control bit
P17 pull-up control bit
0: Pull-up is disabled
1: Pull-up is enabled
Fig 15. Structure of port P1 control register
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REJ03B0202-0202
Page 15 of 81
7549 Group
Table 6
I/O port function table
Pin
Name
I/O format
Non-port function
SFRs related each pin
P00(LED0)/INT0
P01(LED1)/INT1
I/O port P0
CMOS compatible input
level
CMOS 3-state output
External interrupt input
Interrupt edge selection register
Port P0 drive capacity control register
Port P0 pull-up control register
P02(LED2)
Port P0 drive capacity control register
Port P0 pull-up control register
P03(LED3)/CAP0
Capture input
Capture/Compare port register
Port P0 drive capacity control register
Port P0 pull-up control register
P04(LED4)/RXD
Serial interface input/
output
Serial I/O control register
Port P0 drive capacity control register
Port P0 pull-up control register
P05(LED5)/TXD
Serial I/O control register
UART control register
Port P0 drive capacity control register
Port P0 pull-up control register
P06(LED6)/SCLK
Serial I/O control register
Port P0 drive capacity control register
Port P0 pull-up control register
P07(LED7)/SRDY
Serial I/O control register
Port P0 drive capacity control register
Port P0 pull-up control register
Compare output
Key input interrupt
A/D conversion input
Capture/Compare port register
Port P1 pull-up control register
Key-on wakeup input selection register
AD control register
P13/AN3/KEY3/T2OUT
Timer 2 output
Key input interrupt
A/D conversion input
Timer mode register
Port P1 pull-up control register
Key-on wakeup input selection register
AD control register
P14/AN4/KEY4
P15/AN5/KEY5
P16/AN6/KEY6
P17/AN7/KEY7
Key input interrupt
A/D conversion input
Port P1 pull-up control register
Key-on wakeup input selection register
AD control register
P10/AN0/KEY0/CMP0
P11/AN1/KEY1/CMP1
P12/AN2/KEY2/CMP2
P20/XOUT/XCOUT
I/O port P1
I/O port P2
CMOS 3-state output
Clock pin
Function set ROM data 1 (Note)
Clock mode register
Clock pin
Function set ROM data 1 (Note)
Clock mode register
I/O port P3
CMOS compatible input
level
CMOS 3-state output
P21/XIN/XCIN
P30
P31
NOTE:
1. Function set ROM data 1 is included in the function set ROM area.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 16 of 81
7549 Group
(2) Port P01
(1) Port P00
Pull-up control bit
Pull-up control bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
Drive capacity
control bit
Drive capacity
control bit
INT1 input
INT0 input
(4) Port P03
(3) Port P02
Pull-up control bit
Pull-up control bit
Direction
register
Data bus
Direction
register
Data bus
Port latch
Port latch
Drive capacity
control bit
Drive capacity
control bit
CAP0 input
(6) Port P05
(5) Port P04
Pull-up control bit
Pull-up control bit
Serial I/O enable bit
Receive enable bit
P05/TXD P-channel output disable bit
Serial I/O enable bit
Transmit enable bit
Direction
register
Data bus
Direction
register
Port latch
Data bus
Port latch
Drive capacity
control bit
Serial I/O input
Drive capacity
control bit
Serial I/O output
(8) Port P07
(7) Port P06
Serial I/O synchronous
clock selection bit
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O enable bit
Pull-up
control bit
Serial I/O mode selection bit
Serial I/O enable bit
SRDY output enable bit
Direction
register
Data bus
Pull-up control bit
Direction
register
Port latch
Data bus
Port latch
Drive capacity
control bit
Drive capacity
control bit
Serial I/O clock output
Serial I/O ready output
Serial I/O clock input
Note:
Fig 16. Block diagram of pins (1)
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 17 of 81
represents a parasitic diode.
No current flow is possible. Ensure that the input voltage
to each pin does not exceed the absolute maximum rating.
7549 Group
(9) Port P10, P11, P12
(10) Port P13
Pull-up control bit
Pull-up control bit
Direction
register
Data bus
Direction
register
Data bus
Port latch
Compare output
Compare output
port selection bit
Key input interrupt
Port latch
Timer2 output
P13/T2OUT output valid bit
Key input interrupt
Key-on wakeup input selection bit
A/D converter
input
Analog input pin selection bit
Key-on wakeup input selection bit
A/D converter
input
Analog input pin selection bit
(12) Port P20, P21
(11) Port P14 - P17
Pull-up control bit
(Note)
Direction
register
Data bus
Pull-up control at STP
P20/XOUT/XCOUT
Direction
register
Data bus
Port latch
Port latch
Clock input
Key input interrupt
Oscillation mode selection bit
(function set ROM data 1)
Key-on wakeup input selection bit
A/D converter
input
Analog input pin selection bit
P21/XIN/XCIN
Direction
register
(13) Port P30, P31
Data bus
Direction
register
Data bus
Port latch
Port latch
Note: Set to “1” the port P20 direction register.
(14) CNVss
(15) RESET
QzROM programming
power supply
Mode setting signal
input
Reset signal input
Note:
Fig 17. Block diagram of pins (2)
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 18 of 81
represents a parasitic diode.
No current flow is possible. Ensure that the input voltage
to each pin does not exceed the absolute maximum rating.
7549 Group
Termination of unused pins
• Termination of common pins
I/O ports:
Select an input port or an output port and follow
each processing method.
Output ports: Open.
Input ports: If the input level become unstable, through current
flow to an input circuit, and the power supply
current may increase.
Especially, when expecting low consumption
current (at STP or WIT instruction execution etc.),
pull-up or pull-down input ports to prevent
through current (built-in resistor can be used).
We recommend processing unused pins through a
resistor which can secure IOH (avg) or IOL (avg).
Because, when an I/O port or a pin which have an
output function is selected as an input port, it may
operate as an output port by incorrect operation
etc.
Table 7
Termination of unused pins
Pin
Termination
Perform termination of I/O port.
P00/INT0
P01/INT1
P02
P03
P04/RXD
P05/TXD
P06/SCLK
P07/SRDY
P10/AN0/KEY0/CMP0
P11/AN1/KEY1/CMP1
P12/AN2/KEY2/CMP2
P13/AN3/KEY3/T2OUT
P14/AN4/KEY4
P15/AN5/KEY5
P16/AN6/KEY6
P17/AN7/KEY7
P20/XOUT/XCOUT
Set the direction register to “1”,
and perform termination of output
port.
Perform termination of I/O port.
P21/XIN/XCIN
P30
P31
To use the built-in power-on reset
RESET
circuit, leave the RESET pin open.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 19 of 81
7549 Group
Interrupts
The 7549 group interrupts are vector interrupts with a fixed
priority scheme, and generated by 12 sources: 4 external, 7
internal, and 1 software.
The interrupt sources, vector addresses(1), and interrupt priority
are shown in Table 8.
Each interrupt except the BRK instruction interrupt has the
interrupt request bit and the interrupt enable bit. These bits and
the interrupt disable flag (I flag) control the acceptance of
interrupt requests. Figure 18 shows an interrupt control diagram.
Table 8
An interrupt requests is accepted when all of the following
conditions are satisfied:
• Interrupt disable flag.................................“0”
• Interrupt request bit...................................“1”
• Interrupt enable bit....................................“1”
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
Interrupt vector address and priority
Interrupt source
Priority
Vector addresses
(Note 1)
Highorder
Loworder
Interrupt request generating conditions
Remarks
Reset (Note 2)
1
FFFD16
FFFC16
At reset input
Non-maskable
Serial I/O receive
2
FFFB16
FFFA16
At completion of serial I/O data receive
Valid only when serial I/O is selected
Serial I/O transmit
3
FFF916
FFF816
At completion of serial I/O transmit shift or Valid only when serial I/O is selected
when transmit buffer is empty
INT0
4
FFF716
FFF616
At detection of either rising or falling edge External interrupt
of INT0 input
(active edge selectable)
INT1
5
FFF516
FFF416
At detection of either rising or falling edge External interrupt
of INT1 input
(active edge selectable)
Key-on wakeup
6
FFF316
FFF216
At falling of conjunction of input logical
level for port P1 (at input)
Capture
7
FFF116
FFF016
At detection of either rising or falling edge External interrupt
of Capture 0 input
(active edge selectable)
Compare
8
FFEF16
FFEE16
At compare matched
Timer A
9
FFED16
FFEC16
At timer A underflow
Timer 2
10
FFEB16
FFEA16
At timer 2 underflow
A/D conversion
11
FFE916
FFE816
At completion of A/D conversion
Timer 1
12
FFE716
FFE616
At timer 1 underflow
STP release timer underflow
Not used
13
FFE516
FFE416
14
FFE316
FFE216
15
FFE116
FFE016
16
FFDF16
FFDE16
17
FFDD16
FFDC16
At BRK instruction execution
Non-maskable software interrupt
BRK instruction
NOTES:
1. Vector addressed contain internal jump destination addresses.
2. Reset function in the same way as an interrupt with the highest priority.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 20 of 81
External interrupt (valid at falling edge)
Compare interrupt source is selected.
7549 Group
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Fig 18. Interrupt control
• Interrupt Disable Flag
The interrupt disable flag is assigned to bit 2 of the processor
status register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is
set to “0”, acceptance of interrupt requests is enabled. This flag is
set to “1” with the SET instruction and set to “0” with the CLI
instruction.
When an interrupt request is accepted, the contents of the
processor status register are pushed onto the stack while the
interrupt disable flag remains set to “0”. Subsequently, this flag
is automatically set to “1” and multiple interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
• Interrupt Request Bits
Once an interrupt request is generated, the corresponding
interrupt request bit is set to “1” and remains “1” until the request
is accepted . Wh en the request is accepted, th is bit is
automatically set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
• Interrupt Enable Bits
The interrupt enable bits control the acceptance of the
corresponding interrupt requests. When an interrupt enable bit is
set to “0”, the acceptance of the corresponding interrupt request
is disabled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
Rev.2.02 Mar 31, 2009
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Page 21 of 81
Interrupt acceptance
7549 Group
b7
b0
b7
b0
Interrupt edge selection register
(INTEDGE: address 003A16, initial value: 0016)
Interrupt control register 1
(ICON1: address 003E16, initial value: 0016)
INT0 interrupt edge selection bit
0: Falling edge active
1: Rising edge active
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
INT0 interrupt enable bit
INT1 interrupt enable bit
Key-on wake up interrupt enable bit
Capture interrupt enable bit
Compare interrupt enable bit
Timer A interrupt enable bit
0: Interrupts disabled
1: Interrupts enabled
INT1 interrupt edge selection bit
0: Falling edge active
1: Rising edge active
Not used (returns “0” when read)
b7
b0
b7
Interrupt request register 1
(IREQ1: address 003C16, initial value: 0016)
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
INT0 interrupt request bit
INT1 interrupt request bit
Key-on wake up interrupt request bit
Capture interrupt request bit
Compare interrupt request bit
Timer A interrupt request bit
0: No interrupt request issued
1: Interrupt request issued
b7
b0
Interrupt request register 2
(IREQ2: address 003D16, initial value: 0016)
Timer 2 interrupt request bit
A/D conversion interrupt request bit
Timer 1 interrupt request bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0: No interrupt request issued
1: Interrupt request issued
Fig 19. Structure of Interrupt-related registers
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 22 of 81
b0
Interrupt control register 2
(ICON2: address 003F16, initial value: 0016)
Timer 2 interrupt enable bit
A/D conversion interrupt enable bit
Timer 1 interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0: Interrupts disabled
1: Interrupts enabled
7549 Group
• Interrupt Request Generation, Acceptance, and Handling
Interrupts have the following three phases.
(i) Interrupt Request Generation
An interrupt request is generated by an interrupt source
(external interrupt signal input, timer underflow, etc.) and
the corresponding request bit is set to “1”.
(ii) Interrupt Request Acceptance
Based on the interrupt acceptance timing in each instruction
cycle, the interrupt control circuit determines acceptance
conditions (interrupt request bit, interrupt enable bit, and
interrupt disable flag) and interrupt priority levels for
accepting interrupt requests. When two or more interrupt
requests are generated simultaneously, the highest priority
interrupt is accepted. The value of interrupt request bit for
an unaccepted interrupt remains the same and acceptance is
determined at the next interrupt acceptance timing point.
(iii) Handling of Accepted Interrupt Request
The accepted interrupt request is processed.
Figure 20 shows the time up to execution in the interrupt
processing routine, and Figure 21 shows the interrupt sequence.
Figure 22 shows the timing of interrupt request generation,
interrupt request bit, and interrupt request acceptance.
• Interrupt Handling Execution
When interrupt handling is executed, the following operations
are performed automatically.
(1) Once the currently executing instruction is completed, an
interrupt request is accepted.
(2) The contents of the program counters and the processor
status register at this point are pushed onto the stack area in
order from 1 to 3.
1.High-order bits of program counter (PCH)
2.Low-order bits of program counter (PCL)
3.Processor status register (PS)
(3) Concurrently with the push operation, the jump address of
the corresponding interrupt (the start address of the interrupt
processing routine) is transferred from the interrupt vector to
the program counter.
(4) The interrupt request bit for the corresponding interrupt is
set to “0”. Also, the interrupt disable flag is set to “1” and
multiple interrupts are disabled.
(5) The interrupt routine is executed.
(6) When the RTI instruction is executed, the contents of the
registers pushed onto the stack area are popped off in the
order from 3 to 1. Then, the routine that was before running
interrupt processing resumes.
As described above, it is necessary to set the stack pointer and
the jump address in the vector area corresponding to each
interrupt to execute the interrupt processing routine.
Interrupt request
generated
Interrupt request
acceptance
Interrupt routine
starts
Interrupt sequence
Stack push and
Vector fetch
Main routine
*
0 to 16 cycles
7 cycles
7 to 23 cycles
* When executing DIV instruction
Fig 20. Time up to execution in interrupt routine
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Interrupt handling
routine
7549 Group
Push onto stack
Vector fetch
Execute interrupt
routine
φ
SYNC
RD
WR
Address bus
PC
S,SPS
Not used
Data bus
S-1,SPS S-2,SPS
PCH
PCL
BL
PS
BH
AL
AL,AH
AH
SYNC : CPU operation code fetch cycle
(This is an internal signal that cannot be observed from the external unit.)
BL, BH: Vector address of each interrupt
AL, AH: Jump destination address of each interrupt
SPS : “0016” or “0116”
([SPS] is a page selected by the stack page selection bit of CPU mode register.)
Fig 21. Interrupt sequence
Push onto stack
Vector fetch
Instruction cycle
Instruction cycle
Internal clock φ
SYNC
1
T1
2
IR1 T2
IR2 T3
T1 T2 T3 : Interrupt acceptance timing points
IR1 IR2 : Timings points at which the interrupt request bit is set to “1”.
Note : Period 2 indicates the last φ cycle during one instruction cycle.
(1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1.
(2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2.
The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt
requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2
separately.
Fig 22. Timing of interrupt request generation, interrupt request bit, and interrupt acceptance
<Notes>
The interrupt request bit may be set to “1” in the following cases.
<When switching external interrupt active edge>
• INT0 interrupt edge selection bit
(bit 0 of Interrupt edge selection register (address 003A16))
• INT1 interrupt edge selection bit
(bit 1 of Interrupt edge selection register)
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If it is not necessary to generate an interrupt synchronized with
these settings, take the following sequence.
(1)Set the corresponding enable bit to “0” (disabled).
(2)Set the interrupt edge selection bit (the active edge switch
bit) or the interrupt source bit.
(3)Set the corresponding interrupt request bit to “0” after one
or more instructions have been executed.
(4)Set the corresponding interrupt enable bit to “1” (enabled).
7549 Group
Key Input Interrupt (Key-On Wakeup)
A key-on wakeup interrupt request is generated by applying “L”
level to any pin of port P1 that has been set to input mode.
In other words, it is generated when the AND of input level goes
from “1” to “0”. An example of using a key input interrupt is
shown in Figure 23, where an interrupt request is generated by
pressing one of the keys provided as an active-low key matrix
which uses ports P10 to P13 as input ports.
Port PXx
“L” level output
*
P17 output
P16 output
Port P1 pull-up control register
Port P17
bit 7 = “0”
Direction register = “1”
**
Port P17
latch
Key input interrupt request
Falling edge
detection
Port P17 key-on wakeup
selection bit
Port P1 pull-up control register Port P16
bit 6 = “0”
Direction register = “1”
*
**
Port P16
latch
Falling edge
detection
Port P16 key-on wakeup
selection bit
*
P15 output
P14 output
Port P1 pull-up control register
Port P15
bit 5 = “0”
Direction register = “1”
**
Port P15
latch
Falling edge
detection
Port P15 key-on wakeup
selection bit
Port P1 pull-up control register Port P14
bit 4 = “0”
Direction register = “1”
*
**
Port P14
latch
Port P14 key-on wakeup
selection bit
*
P13 input
P12 input
P11 input
P10 input
Falling edge
detection
Port P1 pull-up control register
Port P13
bit 3 = “1”
Direction register = “0”
**
Port P13
latch
Port P1
Input read circuit
Falling edge
detection
Port P13 key-on wakeup
selection bit
Port P1 pull-up control register Port P12
bit 2 = “1”
Direction register = “0”
*
**
Port P12
latch
Falling edge
detection
Port P12 key-on wakeup
selection bit
Port P1 pull-up control register Port P11
bit 1 = “1”
Direction register = “0”
*
**
Port P11
latch
Falling edge
detection
Port P11 key-on wakeup
selection bit
Port P1 pull-up control register Port P10
bit 0 = “1”
Direction register = “0”
*
**
Port P10
latch
Falling edge
detection
Port P10 key-on wakeup
selection bit
* P-channel transistor for pull-up
** CMOS output buffer
Fig 23. Connection example when using key input interrupt and port P1 block diagram
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Page 25 of 81
7549 Group
[Key-on wakeup input selection register] KEYS
Either of enable or disable of key-on wakeup for pins P10 to P15
can be selected by the key-on wakeup input selection bit,
respectively.
b7
b0
Key-on wakeup input selection register
KEYS (000F16), initial value: 0016
Port P10 key-on wakeup input bit
Port P11 key-on wakeup input bit
Port P12 key-on wakeup input bit
Port P13 key-on wakeup input bit
Port P14 key-on wakeup input bit
Port P15 key-on wakeup input bit
Set “0” to these bits certainly
Fig 24. Structure of key input control register
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Page 26 of 81
0: Disable
1: Enable
7549 Group
Timers
The 7549 Group has two 8-bit timers (timer 1 and timer 2) and
one 16-bit timer (timer A).
Timer 1 and timer 2 share the same 8-bit prescaler (prescaler 12).
Each timer and prescaler has a separate timer latch and prescaler
latch.
The division ratio of every timer and prescaler is 1/(n+1), where
n is the value of the timer latch or prescaler latch.
The timers decrement at each count clock input. When the count
value reaches “0”, an underflow occurs at the next count pulse.
The value of the corresponding timer latch is reloaded into the
timer at underflow and counting is continued. When a timer
underflow occurs, the interrupt request bit corresponding to each
timer is set to “1”.
• Prescaler 12 (PRE12)
Prescaler 12 is an 8-bit prescaler that counts the signal selected
by the prescaler 12 count source selection bit. The count source
can be selected from φSOURCE/16 and XCIN input clock.
Writing to prescaler 12 writes the value to both the prescaler
latch and prescaler.
Reading from prescaler 12 reads the prescaler 12 count value.
The initial value is set to “FF16” after reset.
The division ratio of prescaler 12 is 1/(n+1), where n is the
setting value.
Prescaler 12 cannot stop counting by software.
• Timer 1 (T1)
Timer 1 is an 8-bit timer that counts the prescaler 12 output.
When Timer 1 underflows, the timer 1 interrupt request bit is set
to “1”.
Writing to timer 1 writes the value to both the timer 1 latch and
timer 1.
Reading from timer 1 reads the timer 1 count value. The initial
value is set to “0116” after reset.
The division ratio of timer 1 is 1/(m+1), where m is the setting
value. This gives that the division ratio of prescaler 12 and timer
1 is 1/((n+1) × (m+1)), where n is the prescaler 12 setting value
and m is the timer 1 setting value.
Timer 1 cannot stop counting by software.
• Timer 2 (T2)
Timer 2 is an 8-bit timer that counts the signal selected by the
timer 2 count source selection bit.
The count source can be selected from among φSOURCE/16,
/256, prescaler 12 output, and timer A output signal.
Timer 2 counts the selected count source and sets the timer 2
interrupt request bit to “1” at underflow.
When writing to timer 2, the value of the timer 2 write control bit
can be used to select a write to both the timer 2 latch and timer 2
or a write to only the timer 2 latch.
Reading from timer 2 reads the timer 2 count value.
Timer 2 starts counting from “FF16” after reset.
The division ratio of timer 2 is 1/(n+1), where n is the timer 2
setting value. Timer 2 stops when the timer 2 count stop bit is set
to “1”.
When the P13/T2OUT output valid bit is set to “1”, the polarity of
the waveform output from the P13/T2OUT pin can be inverted at
each timer 2 underflow. The output start level of the T2OUT pin
can be selected using the T2OUT polarity switch bit. When this
bit is set to 0, the output starts at “H” level. When this bit is set to
“1”, the output starts at “L” level.
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Page 27 of 81
• Notes
(1) Reading from and Writing to Timer 1 and 2 and Prescaler 12
If the timer/prescaler count source clock and φSOURCE are
different clocks, the timers and prescaler cannot be read or
written. Select the same clock to enable read and write
operations.
Note that timer 2 can be read and written even using a
different clock while its counting is stopped.
1Prescaler 12 and timer 1 cannot be read/written in the
following conditions:
Prescaler 12 count source: XCIN input clock
φSOURCE: Clock other than XCIN input clock
2Timer 2 cannot be read/written during counting in the
following conditions:
Timer 2 count source: Prescaler 12
Prescaler 12 count source: XCIN input clock
φSOURCE: Clock other than XCIN input clock
or
Timer 2 count source: Timer A underflow
Timer A count source: XCIN input clock
φSOURCE: Clock other than XCIN input clock
or
Timer 2 count source: Timer A underflow
Timer A count source: low-speed on-chip oscillator
output
φSOURCE: Clock other than low-speed on-chip
oscillator
(2) Count Source of Prescaler 12
The XCIN input clock can be selected as the prescaler count
source only if the 32 kHz quartz crystal oscillator is selected
by the oscillation method selection bit in FSROM1.
7549 Group
b7
b0
b7
Timer mode register
(TM: address 002B16, initial value: 0016)
b0
Timer count source set register
(TCSS: address 002C16, initial value: 0016)
Not used (return “0” when read)
Timer 2 count source selection bit
b1 b0
0 0 : φSOURCE/16
0 1 : φSOURCE/256
1 0 : Prescaler 12 output
1 1 : Timer A underflow signal
Timer 2 count stop bit
0: Count start
1: Count stop
P13/T2OUT output valid bit
0: Pulse output invalid (I/O port)
1: Pulse output valid
Timer A count source selection bit (Note 1)
b4 b3 b2
0 0 0 : φSOURCE/16
0 0 1 : φSOURCE/2
0 1 0 : φSOURCE/32
0 1 1 : φSOURCE/64
1 0 0 : φSOURCE/128
1 0 1 : φSOURCE/256
1 1 0 : Low-speed on-chip oscillator output
1 1 1 : XCIN input clock
(32 kHz quartz crystal oscillation)
Prescaler 12 count source selection bit
0 : φSOURCE/16
1 : XCIN input clock
(32 kHz quartz crystal oscillation)
Not used (return “0” when read)
T2OUT polarity selection bit
0: Start from “H” level
1: Start from “L” level
Timer 2 write control bit
0: Write to latch and timer simultaneously
1: Write to only latch
Timer A write control bit
0: Write to latch and timer simultaneously
1: Write to only latch
Timer A count stop bit
0: Count start
1: Count stop
Note 1: φSOURCE is the clock selected by bits 5 and 4 in the clock mode register (003716).
The timer count sources are not affected by bits 7 and 6, the CPU clock dividing
ratio select bits.
Not used (return “0” when read)
Fig 25. Structure of timer mode register
Fig 26. Structure of timer count source set register
Data bus
Prescaler 12 count
source selection bit
φSOURCE/16
XCIN input clock
(32 kHz quartz
crystal oscillation)
Prescaler 12 latch (8)
Timer 1 latch (8)
Prescaler 12 (8)
Timer 1 (8)
Timer 1
interrupt
request
Data bus
Timer 2 count
source selection bit
Timer 2 latch (8)
φSOURCE/16
φSOURCE/256
Timer 2 write
control bit
Timer A underflow
Timer 2
interrupt
request
Timer 2 (8)
Timer 2 count
stop bit
“1”
Q
Toggle flip-flop
P13/T2OUT
T2OUT polarity
selection bit
Port P13 latch
Port P13
direction
register
P13/T2OUT
output valid bit
Fig 27. Block diagram of timer 1 and timer 2
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 28 of 81
Q
T
R
“0”
P13/T2OUT output valid bit
7549 Group
Timer A (TA)
Timer A is a 16-bit timer and counts the signal selected by the
timer A count source selection bit.
The count source of Timer A can be selected from among
φSOURCE/2, /16, /32, /64, /128, /256, low-speed on-ship
oscillator clock, and XCIN input clock.
Timer A counts the selected count source and sets the timer A
interrupt request bit to “1”.
When writing to timer A, the setting value of the timer A write
control bit can be used to select a write to both the timer A latch
and timer or a write to only the timer A latch.
Reading from timer A reads the timer A count value.
Be sure to write to and read from the low-order and the higher
order of timer A in the following order:
• Read
Read the high-order of Timer A (TAH) first, and the loworder of Timer A (TAL) next. Always read both of the
registers.
• Write
Write to the low-order of Timer A (TAL) first and the
high-order of Timer A next. Always read both of the
registers.
Counting starts from “FFFF16” after reset.
The division ratio of timer A is 1/(n+1), where n is the timer A
setting value. Timer A stops when the timer A count stop bit is
set to “1”.
Timer A can be used as the timing timer for input capture and
output compare functions.
• Notes
(1) Timer Value Setting
When the timer A write control bit is set to “write to only latch”,
written data is written to only to the latch even when the timer is
stopped. To set the initial setting value when the timer is stopped,
select “Write to timer and latch simultaneously” beforehand.
(2) Reading from and Writing to Timer A
If the timer A count source clock and φSOURCE are different
clocks, timer A cannot be read or written during its counting.
Select the same clock or set timer A to stop counting to enable
read and write operations.
• Timer A cannot be read/written in the following conditions:
Timer A count source: XCIN input clock
φSOURCE: Clock other than XCIN input clock
or
Timer A count source: Low-speed on-chip oscillator output
φSOURCE: Clock other than low-speed on-chip oscillator
(3) Count Source of Timer A
The XCIN input clock can be selected as the count source of timer
A only if the 32 kHz quartz crystal oscillator is selected by the
oscillation method selection bit in FSROM1.
Data bus
φSOURCE/2
φSOURCE/16
φSOURCE/32
Timer A (low-order) latch (8)
Timer A (high-order) latch (8)
φSOURCE/64
Timer A write
control bit
φSOURCE/128
φSOURCE/256
Low-speed on-chip
oscillator output
XCIN input clock
(32 kHz quart
crystal oscillator)
Timer A (low-order) (8)
Timer A count
stop bit
Timer A
count source
selection bits
Fig 28. Block diagram of timer A
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REJ03B0202-0202
Page 29 of 81
Timer A (high-order) (8)
Timer A interrupt
request
Compare
Capture
7549 Group
Output compare
7549 group has 3-output compare channels. Each channel (0 to
2) has the same function and can be used to output waveform by
using count value of Timer A.
Three output compare channels share the registers with the input
capture (one channel), but their individual circuits operate
independently so that all the channels can be used at the same
time.
To use each compare channel, set “1” to the compare x (x = 0, 1,
2) output port selection bit and set the port direction register
corresponding to compare channel to output mode.
The compare value for each channel is set to the capture/compare
register (low-order) and capture/compare register (high-order).
Writing to the register for each channel is controlled by setting
value of capture/compare register RW pointer. Writing to each
register is in the following order;
1. Set the corresponding compare latch to the capture/compare
register RW pointer.
2. Write a value to the capture/compare register (low-order)
and capture/compare register (high-order). (It doesn’t care
even if either low-order or high-order is written early.)
3. Set “1” to the compare latch y (y = 00, 01, 10, 11, 20, 21)
re-load bit.
When “1” is set to the compare latch y re-load bit, the value set to
the compare register is loaded to compare latch when the next
timer underflow.
After loading, re-load bit is set to “0” automatically.
When the count value of timer A matches the compare latch
setting value, a trigger to the compare output circuit is generated.
The trigger can be enabled or disabled using the compare x
trigger enable bit. When the compare x trigger enable bit is set to
1, the output waveform from the port is as follows.
• When the value of the compare x output level latch is “0”
High level at compare latch x0 match
Low level at compare latch x1 match
• When the value of the compare x output level latch is “1”
Low level at compare latch x0 match
High level at compare latch x1 match
The output waveform does not change if the compare x trigger
enable bit is set to 0, so the port output remains fixed at high or
low level.
The compare output level of each channel can be confirmed by
reading the compare x output status bit.
Compare interrupt is available when match of each compare
channel and timer count value. The interrupt request from each
channel can be disabled or enabled by setting value of compare
latch y interrupt source bit.
• Notes
(1) If timer A is stopped, when a value is written to the capture/
compare register it is immediately transferred to the
compare latch. In addition, if timer A is stopped and the
compare x trigger enable bit is set to “1”, the output latch is
initialized.
(2) Do not write the same data to both of compare latch x0 and
x1.
(3) When setting value of the compare latch is larger than timer
setting value, compare match signal is not generated.
Accordingly, the output waveform is fixed to “L” or “H”
level.
However, when setting value of another compare latch is
smaller than timer setting value, this compare match signal
is generated. Accordingly, compare interrupt occurs.
(4) When the compare x trigger enable bit is cleared to “0”
(disabled), the match trigger to the waveform output circuit
is disabled, and the output waveform can be fixed to “L” or
“H” level.
However, in this case, the compare match signal is
generated.
Accordingly, compare interrupt occurs.
b7
b0
Capture/Compare register (low-order)
(CRAL: address 001016, initial value: 0016)
b7
b0
Capture/Compare register (high-order)
(CRAH: address 001116, initial value: 0016)
Fig 29. Structure of capture/compare register
b7
b0
Capture/Compare register RW pointer
(CCRP: address 001216, initial value: 0016)
Capture/Compare register RW pointer
b2 b1 b0
0 0 0 : Compare latch 00
0 0 1 : Compare latch 01
0 1 0 : Compare latch 10
0 1 1 : Compare latch 11
1 0 0 : Compare latch 20
1 0 1 : Compare latch 21
1 1 0 : Capture latch 00
1 1 1 : Capture latch 01
Not used (returns “0” when read)
Fig 30. Structure of capture/compare register RW
pointer
b7
b0
Compare register re-load register
(CMPR: address 002D16, initial value: 0016)
Compare latch 00, 01 re-load bit
0: Re-load disabled
1: Re-load at next underflow
Compare latch 10, 11 re-load bit
0: Re-load disabled
1: Re-load at next underflow
Compare latch 20, 21 re-load bit
0: Re-load disabled
1: Re-load at next underflow
Not used (returns “0” when read)
Fig 31. Structure of compare register re-load register
b7
b0
Capture/Compare port register
(CCPR: address 002E16, initial value: 0016)
Capture 0 input port selection bit
0: Capture from P03
1: Low-speed on-chip oscillator/16
Compare 0 output port selection bit
0: P10 is I/O port
1: P10 is Compare 0 output
Compare 1 output port selection bit
0: P11 is I/O port
1: P11 is Compare 1 output
Compare 2 output port selection bit
0: P12 is I/O port
1: P12 is Compare 2 output
Not used (returns “0” when read)
Fig 32. Structure of capture/compare port register
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REJ03B0202-0202
Page 30 of 81
7549 Group
b7
b0
Compare output mode register
(CMOM: address 001316, initial value: 0016)
Compare 0 output level latch
0: Positive
1: Negative
Compare 1 output level latch
0: Positive
1: Negative
Compare 2 output level latch
0: Positive
1: Negative
Compare 0 trigger enable bit
0: Disabled
1: Enabled
Compare 1 trigger enable bit
0: Disabled
1: Enabled
Compare 2 trigger enable bit
0: Disabled
1: Enabled
Not used (returns “0” when read)
Fig 33. Structure of compare output mode register
b7
b0
Capture/Compare status register
(CCSR: address 002F16, initial value: 0016)
Compare 0 output status bit
0: “L” level output
1: “H” level output
Compare 1 output status bit
0: “L” level output
1: “H” level output
Compare 2 output status bit
0: “L” level output
1: “H” level output
Capture 0 status bit
0: latch 00 captured
1: latch 01 captured
Not used (returns “0” when read)
Fig 34. Structure of capture/compare status register
b7
b0
Compare interrupt source register
(CISR: address 003016, initial value: 0016)
Compare latch 00 interrupt source bit
Compare latch 01 interrupt source bit
Compare latch 10 interrupt source bit
Compare latch 11 interrupt source bit
Compare latch 20 interrupt source bit
Compare latch 21 interrupt source bit
Not used (returns “0” when read)
0: Disabled
1: Enabled
Fig 35. Structure of compare interrupt source register
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Page 31 of 81
7549 Group
Compare latch 00
Timer A latch
Compare latch 01
Output waveform latch 0
P10/CMP0
Timer A counter
Compare channel 0
P11/CMP1
Compare channel 1
P12/CMP2
Compare channel 2
Fig 36. Block diagram of compare output circuit
Data bus
Capture/Compare
register RW pointer
(001216, bits 0 to 2)
Compare buffer 00 (16)
Compare buffer 01 (16)
Compare latch 00 (16)
Compare latch 01 (16)
Compare latch 00,
01 reload bit
(002D16, bit 0)
Compare 0 output
port selection bit
(002E16, bit 1)
Compare 0
output status bit
(002F16, bit 0)
I/O port
Compare register
Output
waveform
latch 0
P10/CMP0
Compare 0
output level latch
(001316, bit 0)
Compare latch 00
interrupt source bit
(003016, bit 0)
Compare interrupt
Compare latch 01
interrupt source bit
(003016, bit 1)
Fig 37. Block diagram of compare channel 0
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REJ03B0202-0202
Compare 0 trigger
enable bit
(001316, bit 3)
Page 32 of 81
Timer A counter (16)
7549 Group
Timer A count clock
Re-load the count value
Timer A underflow
Timer A count value 000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
Compare latch 00
000B
Compare latch 01
0005
0002
0001
0000
000F
000E
000D
000C
000B
Compare 00 match
Compare 01 match
Compare output
Compare interrupt
Compare status bit
0
1
0
Note: Compare interrupt occurs only for the interrupt source selected by Compare interrupt source register.
Fig 38. Output compare mode (general waveform)
Timer A count clock
Re-load the count value
Timer A underflow
Timer A count value 000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
000F
000E
000D
Compare latch 00
000B
000E
Compare latch 01
0005
000C
000C
000B
Compare latch 00 write
Compare latch 01 write
Compare latch 00, 01 re-load bit
Compare latch 00, 01 re-load signal
Compare 00 match
Compare 01 match
Compare output
Compare interrupt
Compare status bit
0
1
Fig 39. Output compare mode (compare register write timing)
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Page 33 of 81
0
1
0
7549 Group
Input capture
7549 group has 1-input capture channel and can be used to
capture count value of Timer A.
Input capture shares the registers with three output compare
channels, but their individual circuits operate independently so
that all the channels can be used at the same time.
To use input capture, set the capture 0 input port selection bits. If
P03 is selected, set the P03 direction register to 0. When an input
capture trigger is input to the input capture circuit, the count
value of timer A is saved to the capture latches. The timer count
value at the rising edge of the external input trigger is saved to
capture latch 00, and the timer count value at the falling edge of
the external input trigger is saved to capture latch 01. Capture
latch 00 and capture latch 01 can be read using the following
procedure.
1. Set the capture/compare register RW pointer to the read target address.
2. Read the high-order bits of the capture/compare registers,
then read the low-order bits of the capture/compare registers. (Read both the capture/compare registers in the
sequence of high-order bits followed by low-order bits.)
The count value of timer can be retained by software by capture
y (y = 00, 01, 10, 11) software trigger bit too. When “1” is set to
this bit, count value of timer is retained to the corresponded
capture latch.
When reading from the capture y software trigger bit is executed,
“0” is read out.
• Notes
• When the low-speed on-chip oscillator output or XCIN input
clock is selected as the count source of timer A, input capture
can be used only if the same clock source is selected as
φSOURCE and as the count source of timer A.
• When writing “1” to capture y software trigger bit of capture
latch 00 and 01 at the same time, or external trigger and
software trigger occur simultaneously, if capture latches 00
and 01 are input simultaneously, the set value of capture 0
status bit is undefined.
• When setting the interrupt active edge selection bit and noise
filter clock selection bit of capture 0 the interrupt request bit
may be set to “1”.
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
(1) Set the capture interrupt enable bit to “0” (disabled).
(2) Set the interrupt edge selection bit or noise filter clock
selection bit.
(3) Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
(4) Set the capture interrupt enable bit to “1” (enabled).
• When the capture interrupt is used as the interrupt for return
from stop mode, set the capture 0 noise filter clock selection
bits to “00 (Filter stop)”.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 34 of 81
b7
b0
Capture software trigger register
(CSTR: address 003116, initial value: 0016)
Capture latch 00 software trigger bit
Capture 00 software trigger occurs by setting “1”
to this bit. (returns “0” when read)
Capture latch 01 software trigger bit
Capture 01 software trigger occurs by setting “1”
to this bit. (returns “0” when read)
Not used (returns “0” when read)
Fig 40. Structure of capture software trigger register
b7
b0
Capture mode register
(CAPM: address 003216, initial value: 0016)
Capture 0 interrupt edge selection bits
b1 b0
0 0 : Rising and falling edge
0 1 : Rising edge
1 0 : Falling edge
1 1 : Not available
Capture 0 noise filter clock selection bits
b1 b0
0 0 : Filter stop
0 1 : f (XIN)
1 0 : f (XIN)/8
1 1 : f (XIN)/32
Not used (returns “0” when read)
Fig 41. Structure of capture mode register
7549 Group
Data bus
Capture register
Capture/Compare
register RW pointer
(001216, bits 0-2)
Capture latch 00 (16) Capture latch 01 (16)
Capture 0 status bit
(002F16, bit 3)
Capture pointer
Rising
Capture latch 0x
software trigger bits
(003116, bits 0, 1)
Low-speed on-chip
oscillator/16
Digital filter
Capture trigger
Falling
Capture 0 interrupt
edge selection bits
(003216, bits 0, 1)
Capture Interrupt
Capture latch 0 (16)
P03/
CAP0
Capture 0 input
port selection bit
(002E16, bit 0)
Capture 0 noise filter
clock selection bits
(003216, bits 2, 3)
Timer A counter (16)
Fig 42. Block diagram of capture channel 0
Re-load the timer A count value
Timer A underflow
Capture input wave
Timer A count value 000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
000F
000E
000D
000C
000B
Overwrite
Capture latch 00
XXXX
000A
Capture latch 01
0001
000C
0005
XXXX
000F
Capture 0 interrupt
Capture 0 status bit
1
0
1
0
1
0
Fig 43. Capture input waveform (capture interrupt edge selection bit = “rising edge”)
Re-load the timer A count value
Timer A underflow
Capture input wave
Timer A count value 000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
000F
000E
000D
000C
000B
Overwrite
Capture latch 00
XXXX
000A
0001
XXXX
Capture latch 01
000C
0005
000F
Capture 0 interrupt
Capture 0 status bit
1
0
1
0
1
Fig 44. Capture input waveform (capture interrupt edge selection bit = “rising and falling edge”)
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 35 of 81
0
7549 Group
Serial Interface
• Serial I/O
Serial I/O can be used as either clock synchronous or
asynchronous (UART) serial I/O. A dedicated timer is also
provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O mode selection bit of the serial I/O control register (bit
6) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Data bus
Serial I/O control register
Address 001816
Receive buffer register 1
Receive shift register 1
P04/RXD
Address 001A16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Shift clock
Clock control circuit
P06/SCLK
φSOURCE
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
Baud rate generator
1/4
P07/SRDY
Falling-edge detector
F/F
1/4
Address 001C16
Clock control circuit
Transmit shift completion flag (TSC)
Shift clock
Transmit interrupt source selection bit
P05/TXD
Transmit shift register
Transmit interrupt request (TI)
Transmit buffer register
Transmit buffer empty flag (TBE)
Serial I/O status register
Address 001816
Address 001916
Data bus
Fig 45. Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY
Write pulse to receive/transmit
buffer register 1 (address 001816)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig 46. Operation of clock synchronous serial I/O function
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 36 of 81
7549 Group
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but
the two buffers have the same address in memory. Since the shift
register cannot be written to or read from directly, transmit data
is written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
Serial I/O 1 control register Address 001A16
Address 001816
Receive buffer register
OE
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Character length selection bit
P04/RXD
ST detector
7 bits
Receive shift register
1/16
8 bits
PE FE
UART control register
SP detector
Address 001B16
Clock control circuit
Serial I/O1 synchronous clock selection bit
P06/SCLK
Frequency division ratio 1/(n+1)
BRG count source selection bit
φSOURCE
Baud rate generator
Address 001C16
1/4
ST/SP/PA generator
Transmit shift completion flag (TSC)
1/16
P05/TXD
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer register
Address 001816
Serial I/O1 status register
Address 001916
Data bus
Fig 47. Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer
write signal
TBE=0
TSC=0
TBE=1
TBE=0
TBE=1
TSC=1*
Serial output TXD
ST
D0
D1
SP
ST
D0
D1
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer
read signal
SP
* Generated at 2nd bit in 2-stop-bit mode
RBF=0
RBF=1
RBF=1
Serial input RXD
ST
D0
D1
SP
ST
D0
D1
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig 48. Operation of UART serial I/O function
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 37 of 81
SP
7549 Group
[Transmit buffer register/receive buffer register (TB/
RB)] 001816
The transmit buffer register and the receive buffer register are
located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits,
the MSB of data stored in the receive buffer is “0”.
[Serial I/O status register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the
receive buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer
register, and the receive buffer full flag is set. A write to the
serial I/O status register clears all the error flags OE, PE, FE, and
SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O
enable bit SIOE (bit 7 of the serial I/O control register) also
clears all the status flags, including the error flags.
Bits 0 to 6 of the serial I/O status register are initialized to “0” at
reset, but if the transmit enable bit of the serial I/O control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O control register (SIOCON)] 001A16
The serial I/O control register consists of eight control bits for
the serial I/O function.
[UART control register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to
3) which are valid when asynchronous serial I/O is selected and
set the data format of an data transfer and one bit (bit 4) which is
always valid and sets the output structure of the P05/TxD pin.
[Baud rate generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial
transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate
generator.
Rev.2.02 Mar 31, 2009
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Page 38 of 81
•Notes
• Serial I/O interrupt
When setting the transmit enable bit to “1”, the serial I/O
transmit interrupt request bit is automatically set to “1”. When
not requiring the interrupt occurrence synchronized with the
transmission enabled, take the following sequence.
1. Set the serial I/O transmit interrupt enable bit to “0” (disabled).
2. Set the transmit enable bit to “1”.
3. Set the serial I/O transmit interrupt request bit to “0” after 1
or more instructions have been executed.
4. Set the serial I/O transmit interrupt enable bit to “1”
(enabled).
• I/O pin function when serial I/O is enabled.
The functions of P06 and P07 are switched with the setting values
of a serial I/O mode selection bit and a serial I/O synchronous
clock selection bit as follows.
(1) Serial I/O mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O synchronous clock selection bit
“0” : P06 pin turns into an output pin of a synchronous clock.
“1” : P06 pin turns into an input pin of a synchronous clock.
Setup of a SRDY output enable bit (SRDY)
“0” : P07 pin can be used as a normal I/O pin.
“1” : P07 pin turns into a SRDY output pin.
(2) Serial I/O mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O synchronous clock selection bit
“0” : P06 pin can be used as a normal I/O pin.
“1” : P06 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it
is P07 pin. It can be used as a normal I/O pin.
7549 Group
b7
b7
b0
b0
Serial I/O status register
(SIOSTS: address 001916, initial value: 8016)
b7
b0
Serial I/O control register
(SIOCON: address 001A16, initial value: 0016)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
BRG count source selection bit (CSS)
0: φSOURCE
1: φSOURCE/4
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift inprogress
1: Transmit shift completed
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
Overrun error flag (OE)
0: No error
1: Overrun error
SRDY output enable bit (SRDY)
0: P07 pin operates as ordinary I/O pin
1: P07 pin operates as SRDY output pin
Parity error flag (PE)
0: No error
1: Parity error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Framing error flag (FE)
0: No error
1: Framing error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Not used (returns “1” when read)
Serial I/O mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
UART control register
(UARTCON: address 001B16, initial value: E016)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P05/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig 49. Structure of serial I/O1-related registers
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REJ03B0202-0202
Page 39 of 81
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P04 to P07 operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P04 to P07 operate as serial I/O pins)
7549 Group
A/D Converter
The functional blocks of the A/D converter are described below.
b7
b0
[AD conversion register] AD
The A/D conversion register is a read-only register that stores the
result of A/D conversion. Do not read out this register during an
A/D conversion.
AD control register
(ADCON: address 003416, initial value: 1016)
Analog input pin selection bits
000: P10/AN0
001: P11/AN1
010: P12/AN2
011: P13/AN3
100: P14/AN4
101: P15/AN5
110: P16/AN6
111: P17/AN7
[AD control register] ADCON
The AD control register controls the A/D converter.
Bit 2 to 0 are analog input pin selection bits.
Bit 3 is the AD conversion clock selection bit. When “0” is set to
this bit, the A/D conversion clock is φSOURCE/2 and the A/D
conversion time is 122 cycles of φSOURCE. When “1” is set to
this bit, the A/D conversion clock is φSOURCE and the A/D
conversion time is 61 cycles of φSOURCE.
Bit 4 is the AD conversion completion bit. The value of this bit
remains at “0” during A/D conversion, and changes to “1” at
completion of A/D conversion.
A/D conversion is started by setting this bit to “0”.
[Comparison voltage generator]
The comparison voltage generator divides the voltage between
VSS and VCC by 1024, and outputs the divided voltages.
[Channel selector]
The channel selector selects one of ports P17/AN7 to P10/AN0,
and inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input
voltage with the comparison voltage and stores its result into the
AD conversion register. When AD conversion is completed, the
control circuit sets the AD conversion completion bit and the A/
D conversion interrupt request bit to “1”. Because the
comparator is constructed linked to a capacitor, set φSOURCE in
order that the A/D conversion clock is 250 kHz or over during A/
D conversion.
AD conversion clock selection bit
0: φSOURCE/2
1: φSOURCE
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
Fig 50. Structure of AD control register
Read 8-bit (Read only address 0035 16)
b7
b0
(Address 003516) b9 b8 b7 b6 b5 b4 b3 b2
Read 10-bit (read in order address 0036 16, 003516)
(Address 003616)
b7
b0
b9 b8
(Address 003516)
b7
b0
b7 b6 b5 b4 b3 b2 b1 b0
Note: High-order 6-bit of address 003616 returns “0” when read.
• Notes
As for A/D translation accuracy, on the following operating
conditions, accuracy may become low.
(1) When VCC voltage is lower than [3.0 V], the accuracy at the
low temperature may become extremely low compared with
that at room temperature. When the system would be used at
low temperature, the use at V CC = 3.0 V or more is
recommended.
(2) When XCIN or the low-speed on-chip oscillator is selected as
φSOURCE, the A/D converter cannot be used.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 40 of 81
Fig 51. Structure of AD conversion register
7549 Group
Data bus
AD control register
(Address 003416)
b7
b0
3
A/D interrupt request
Channel selector
A/D control circuit
P10/AN0
P11/AN1
P12/AN2
P13/AN3
P14/AN4
P15/AN5
P16/AN6
P17/AN7
φSOURCE
φSOURCE/2
AD conversion register (high-order)
AD conversion register (low-order)
10
Resistor ladder
VCC
Fig 52. Block diagram of A/D converter
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Comparator
Page 41 of 81
VSS
(Address 003616)
(Address 003516)
7549 Group
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter. The operation of
the watchdog timer is controlled by bits 2 to “0” in function set
ROM data 2 and the watchdog timer control register.
The following shows the time to watchdog timer underflow after
writing to the watchdog timer control register.
The example applies when the XIN input clock is selected as
φSOURCE and f(XIN) = 8 MHz.
• Watchdog timer H count source selection bit = 0: 131.072 ms
• Watchdog timer H count source selection bit = 1: 512 µs
b7
b0
• Watchdog timer disable bit
When the watchdog timer disable bit (bit 1 in function set ROM
data 2(FSROM2)) is set to “0”, the watchdog timer is enabled
and starts counting after reset.
Setting this bit to “1” does not operate the watchdog timer.
This bit cannot be rewritten by executing the instruction.
To use the watchdog timer, always set this bit to “0”.
After reset, the watchdog timer cannot start counting by a program.
Function set ROM data 2
(FSROM2: address FFDA16)
Watchdog timer source clock selection bit
0 : Low-speed on-chip oscillator/16
1 : φSOURCE/16
Watchdog timer disable bit
0 : Watchdog timer enabled
1 : Watchdog timer disabled
Watchdog timer H count source initial value
selection bit
0 : Initial value of bit 7 of WDTCON
after reset release is “0”
1 : Initial value of bit 7 of WDTCON
after reset release is “1”
• Watchdog timer source clock selection bit
The count source of the watchdog timer is selected by the
watchdog timer source clock selection bit (bit 0 in FSROM2).
This bit cannot be rewritten by executing the instruction.
When this bit is set to “0”, the count source is always set to the
low-speed on-chip oscillator output/16.
When this bit is set to “1”, the count source is set to φSOURCE/
16. φSOURCE is changed by setting the clock selection bits (bits
5 and 4 in the clock mode register (CLKM: address 003716)).
• Watchdog timer H count source selection bit
The count source of watchdog timer H is selected by the
watchdog timer control register (WDTCON: address 003916).
When the watchdog timer H count source selection bit (bit 7 in
WDTCON) is set to “0”, the count source is set to an underflow
signal from watch dog timer L. When this bit is set to “1”, the
clock selected as the count source of watchdog timer L is input to
watchdog timer H.
The initial value of this bit after releasing reset can be set by the
bit 2 in FSROM2.
• Watchdog Timer Operation
Resetting or writing any data to WDTCON sets watchdog timer H
to “FF16” and watchdog timer L to “FF16”. When the watchdog
timer starts, the selected clock is counted and internal reset occurs
by the watchdog timer H underflow. Writing to WDTCON is
usually programmed to be performed before underflow.
Reading WDTCON reads the values of the high-order 6 bits in
the watchdog timer H counter and the watch dog timer count
source selection bit.
STP instruction function selection bit
0 : System enters into the stop mode
at the STP instruction execution
1 : Internal reset occurs at the STP
instruction execution
Low-speed on-chip oscillator control bit
(Note 1)
0 : Stop of low-speed on-chip oscillator
disabled
1 : Stop of low-speed on-chip oscillator
enabled
Set “0” to these bits certainly.
Note 1: If “0” is set to this bit, it is not possible to write “1” to bit 0 in the clock
mode register. Also, the low-speed on-chip oscillator does not stop
even if in the stop mode.
Fig 53. Structure of Function set ROM data 2
b7
b0
Watchdog timer control register (Note)
(WDTCON: address 0039 16,
initial value: X01111112)
Watchdog timer H (read only for
high-order 6-bit)
Not used (returns “0” when read)
Watchdog timer H count source
selection bit
0 : Watchdog timer L underflow
1 : Low-speed on-chip oscillator/16
or φSOURCE/16
Note: The initial value of this register is changes by setting of
function set ROM data 2.
Fig 54. Structure of watchdog timer control register
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 42 of 81
7549 Group
Watchdog timer H
count source selection bit
(bit 7 of WDTCON)
Watchdog timer source
clock selection bit
(bit 0 of FSROM2)
“FF16” is set at
WDTCON writing
Data bus
Watchdog timer L (8)
1/16
Watchdog timer H (8)
“1”
Watchdog timer disable bit
(bit 1 of FSROM2)
STP instruction function
selection bit
(bit 3 of FSROM2)
STP Instruction
FSROM2: Function set ROM data 2
WDTCON: Watchdog timer control register
CPUM: CPU mode register
Fig 55. Block diagram of watchdog timer
• Notes
(1) The watchdog timer operates in wait mode. To prevent
underflow, write to the watchdog timer control register.
The watchdog timer stops in stop mode, but starts counting
at the same time as exiting stop mode. After exiting stop
mode, it continues counting during oscillation stabilization
time. To prevent underflow during the period, the watchdog
timer H count source selection bit (bit 7) in the watchdog
timer control register (address 003916) should be set to “0”
before executing the STP instruction.
Note that the watchdog timer continues counting even if the
STP instruction is executed in the following two conditions:
1 Stopping the low-speed on-chip oscillator: Disabled (bit
4 in FSROM2)
Source clock of the watchdog timer: Low-speed on-chip
oscillator/16 (bit 0 in FSROM2)
2 Stopping the low-speed on-chip oscillator: Disabled (bit
4 in FSROM2)
Source clock of the watchdog timer: φSOURCE (bit 0 in
FSROM2)
φSOURCE: Low-speed on-chip oscillator (bits 5 and 4 in
CLKM)
(2) STP instruction function selection bit
The function of the STP instruction can be selected by the
bit 2 in FSROM2. This bit cannot be used for rewriting by
executing the STP instruction.
• When this bit is set to “0”, stop mode is entered by
executing the STP instruction.
• When this bit is set to “1”, internal reset occurs by
executing the STP instruction.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
“FF16” is set at
WDTCON writing
“0”
φSOURCE
Low-speed on-chip
oscillator
Initial value setting
after releasing reset Watchdog timer H count source
initial value selection bit
(bit 2 of FSROM2)
Page 43 of 81
Reset pin input
Reset
circuit
Internal reset
7549 Group
Power-on Reset Circuit
Reset can be automatically performed at power on (power-on
reset) by the built-in power-on reset circuit.
To use the built-in power-on reset circuit, leave the RESET pin
open (the pull-up resistor is built-in).
VCC (Note)
Power-on reset circuit output
Low Voltage Detection Circuit
The built-in low voltage detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the power
source voltage drops below a set value (Typ.1.95 V).
The low voltage detection circuit is valid by setting “1” to bit 0
of the function set ROM data 0.
Also, when “1” is set to bit 2 of the function set ROM data 1, the
low voltage detection circuit can be valid even in the stop mode.
The low voltage detection circuit is stopped in the stop mode by
setting “0” to this bit, so that the power dissipation is reduced.
Internal reset signal
Reset
state
Power-on
Reset released
Note: Keep the value of supply voltage to
the minimum value or more of the
recommended operating conditions.
Fig 56. Operation waveform diagram of power-on
reset circuit
VCC
Reset voltage (Typ:1.95V)
Internal reset signal
Microcomputer starts operation
by the built-in on-chip oscillator.
Fig 57. Operation waveform diagram of low voltage detection circuit
Low-speed on-chip
oscillator clock
Internal CPU clock φ
RESET
Internal reset
signal
SYNC
?
Address
Data
?
?
?
9 to 16 cycles of
internal CPU clock φ
Fig 58. Timing diagram at reset
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 44 of 81
?
?
?
?
?
?
FFFC
?
FFFD
ADL
ADH,ADL
ADH
Reset address from the
vector table
7549 Group
(1)
Port P0 direction register (P0D)
000116
0016
(2)
Port P1 direction register (P1D)
000316
0016
(3)
Port P2 direction register (P2D)
000516
0016
(4)
Port P3 direction register (P3D)
000716
0016
(5)
Port P0 drive capacity control register (DCCR)
000C16
0016
(6)
Port P0 pull-up control register (PULL0)
000D16
0016
(7)
Port P1 pull-up control register (PULL1)
000E16
0016
(8)
Key-on wakeup input selection register (KEYS)
000F16
0016
(9)
Capture/Compare register (low-order) (CRAL)
001016
0016
(10)
Capture/Compare register (high-order) (CRAH)
001116
0016
(11)
Capture/Compare register RW pointer (CCRP)
001216
0016
(12)
Compare output mode register (CMOM)
001316
0016
(13)
Timer A (low-order) (TAL)
001416
FF16
(14)
(15)
Timer A (high-order) (TAH)
Serial I/O status register (SIOSTS)
001516
(16)
Serial I/O control register (SIOCON)
001A16
(17)
UART control register (UARTCON)
001B16
(18)
Prescaler 12 (PRE12)
002816
(19)
Timer 1 (T1)
002916
(20)
Timer 2 (T2)
002A16
FF16
(21)
Timer mode register (TM)
002B16
0016
(22)
Timer count source set register (TCSS)
002C16
0016
(23)
Compare register re-load register (CMPR)
002D16
0016
(24)
Capture/Compare port register (CCPR)
002E16
0016
(25)
Capture/Compare status register (CCSR)
002F16
0016
(26)
Compare interrupt source set register (CISR)
003016
0016
(27)
Capture software trigger register (CSTR)
003116
0016
(28)
Capture mode register (CAPM)
003216
(29)
AD control register (ADCON)
003416
(30)
Clock mode register (CLKM)
003716
(31)
Oscillation stop detection register (CLKSTP)
003816
(32)
Watchdog timer control register (WDTCON)
003916
(33)
Interrupt edge selection register (INTEDGE)
003A16
0016
(34)
CPU mode register (CPUM)
003B16
0016
(35)
Interrupt request register 1 (IREQ1)
003C16
0016
(36)
Interrupt request register 2 (IREQ2)
003D16
0016
(37)
Interrupt control register 1 (ICON1)
003E16
0016
(38)
Interrupt control register 2 (ICON2)
003F16
0016
001916
FF16
1
1
0
0
1
0
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 45 of 81
0
0
0
0
0
1
0016
0
0
0
0
0
0
FF16
0
0
0
0
1
0016
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
Note 4
0
1
0016
1
1
1
1
1
Notes 1: X : Undefined
2: The content of other registers is undefined when the microcomputer is reset.
The initial values must be surely set before you use it.
3: Do not access to the SFR area including nothing.
4: When the setting by the function set ROM data 2 (FSROM2) is performed,
the initial values of this bit at reset are changed.
Fig 59. Timing diagram at reset
0
7549 Group
Clock Generating Circuit
The clock generating circuit includes the XIN clock (ceramic
oscillator or crystal oscillator can be used), XCIN clock (32 kHz
oscillator can be used), external clock input, high-speed on-chip
oscillator, and low-speed on-chip oscillator.
Pins P20/XOUT/XCOUT and P21/XIN/XCIN can be shared for the
ports, XIN oscillation, and XCIN oscillation.
Use the oscillation method selection bits (bits 1 and bit 0 in
function set ROM data 1 (FSROM1)) to set the function of these
pins.
• Ceramic Resonator or Crystal Oscillator
Set the oscillation method selection bits (bits 1 and bit 0 in
FSROM1) to “012”, and connect the ceramic resonator (or the
oscillator) and external circuit with the shortest wiring length
possible.
The constants of the oscillator circuit differ depending on the
resonator. Use the values recommended by the resonator
manufacturer. (An external feedback resistor may be necessary
under some conditions.)
Setting the X IN /X CIN oscillation control bit to “0” starts
oscillation. This bit is sets to “0” after reset.
• 32 kHz Crystal Oscillator
Set the oscillation method selection bits to “102”, and connect the
32 kHz crystal oscillator and external circuit with the shortest
wiring length possible.
The constants of the oscillator circuit differ depending on the
resonator. Use the values recommended by the resonator
manufacturer. (An external feedback resistor may be necessary
under some conditions.)
Setting the X IN /X CIN oscillation control bit to “0” starts
oscillation. This bit is sets to “0” after reset.
• External Clock Input
Set the oscillation method selection bits to “112”, and connect the
clock source to the P20/XOUT pin. In this case, the P21/XIN pin
can be used as an I/O port.
• High-Speed On-Chip Oscillator
The high-speed on-chip oscillator is stopped after reset.
Setting the high-speed on-chip oscillator oscillation control bit
(bit 1 in CLKM) to “0” starts oscillation. This bit is sets to “1”
after reset.
• Low-Speed On-Chip Oscillator
The low-speed on-chip oscillator automatically starts oscillating
after reset.
Setting the low-speed on-chip oscillator oscillation control bit
(bit 0 in CLKM) to “1” stops oscillation. This bit is sets to “0”
after reset. If the low-speed on-chip oscillator control bit (bit 4 in
FSROM2) is set to “0” and stopping the low-speed on-chip
oscillator is disabled, the low-speed on-chip oscillator oscillation
control bit cannot be set to “1” and oscillation cannot be stopped.
Also, the oscillator does not stop even when the STP instruction
is executed.
• Using No Oscillator Pins (P20 as output port and P21
as I/O port)
To use only an internal on-chip oscillator, set the oscillation
method selection bits to “002”. The P20/XOUT pin can be used as
an output port and the P21/XIN pin can be used as an I/O port.
b7
b0
Function set ROM data 1
FSROM1 (FFD916)
Oscillation method select bits (Note 1)
b1 b0
0 0: No resonator used (P20 and P21 set as I/O ports)
0 1: Ceramic resonator or quartz-crystal oscillation
1 0: 32 kHz quartz-crystal oscillation
1 1: External clock input (P21 set as I/O port)
Stop mode low voltage detection circuit enable/disable bit
(Note 2)
0: Low voltage detection circuit disabled in stop mode
1: Low voltage detection circuit enabled in stop mode
Always set these bits to 0.
Always set this bit to 1.
Notes 1: The P20/XOUT and P21/XIN pins build in an on-chip oscillator. Even if these
pins are used as I/O ports, the oscillator circuit is enabled when the MCU’s Vcc
voltage drops below the operation limit voltage. In this case these pins may output
undefined values.
2: If the low voltage detection circuit is enabled in stop mode, power consumption in
stop mode will increase.
Fig 60. Structure of function set ROM data 1
M37549
XIN
XOUT
Rd
COUT
CIN
Insert a damping resistor if required.
The resistance will vary depending
on the oscillator and the oscillation
drive capacity setting.
Use the value recommended by the
maker of the oscillator.
Also, if the oscillator manufacturer’s
data sheet specifies that a feedback
resistor be added external to the chip
though a feedback resistor exists onchip, insert a feedback resistor
between XIN and XOUT following the
instruction.
Fig 61. External circuit of ceramic resonator
M37549
XCIN
XCOUT
Rd
CCIN
CCOUT
Insert a damping resistor if required.
The resistance will vary depending
on the oscillator and the oscillation
drive capacity setting.
Use the value recommended by the
maker of the oscillator.
Also, if the oscillator manufacturer’s
data sheet specifies that a feedback
resistor be added external to the
chip though a feedback resistor
exists on-chip, insert a feedback
resistor between XIN and XOUT
following the instruction.
Fig 62. External circuit of 32 kHz quarts-crystal
oscillator
Connect the external clock
to the P20/XOUT pin, not
the P21/XIN pin.
M37549
P21
XOUT
I/O port
External
oscillation circuit
Vcc
Vss
Fig 63. External clock input circuit
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 46 of 81
7549 Group
b7
b0
Clock mode register
(CLKM: address 003716, initial value: 0216)
Low-speed on-chip oscillator oscillation control bit
(Notes 1, 2, and 4)
0: Oscillation start
1: Oscillation stop
High-speed on-chip oscillator oscillation control bit
(Notes 2 and 4)
0: Oscillation start
1: Oscillation stop
XIN/XCIN oscillation control bit (Notes 2 and 4)
0: Oscillation start
1: Oscillation stop
Oscillation stabilization time set bit after release of the
STP instruction
0: Timer 1 set to “0116” and prescaler 12 to “FF16”
automatically
1: Un-automatically
Clock selection bits (Notes 3 and 4)
b5 b4
0 0 : Low-speed on-chip oscillator
0 1 : High-speed on-chip oscillator
1 0 : XIN/XCIN oscillation, External clock
1 1 : Not available
Clock division ratio selection bit
b7 b6
0 0 : φSOURCE/8 (low-speed mode)
0 1 : φSOURCE/4 (middle-speed mode)
1 0 : φSOURCE/2 (high-speed mode)
1 1 : No division (double-speed mode)
Notes 1: When stopping the low-speed on-chip oscillator is disabled by setting the low-speed
on-chip oscillator control bit (bit 4 in FSROM2), “1” cannot be written to this bit.
The low-speed on-chip oscillator does not stop even in stop mode.
2: “1” cannot be written to the oscillation control bits (bits 2 to 0) of the clock selected
as φSOURCE by the clock selection bits.
3: When “oscillation pins not used” is set by the oscillation method selection bits (bits 1
and 0 in FSROM1), “102” cannot be written to these bits.
4: Do not change the values of the clock selection bits and the clock oscillation control
bits at the same time using a single instruction. Always use different instructions to
rewrite these values.
Fig 64. Structure of clock mode register
• Note
• Switching to XIN/XCIN Oscillator
After a reset is cleared, operation starts using the low-speed onchip oscillator. When switching to XIN/XCIN oscillator, make
sure to set a sufficient wait duration with the on-chip oscillator to
allow the XIN/XCIN oscillator to stabilize.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 47 of 81
7549 Group
Oscillation Control
• Clock mode register
Clock mode register contains the oscillation control bits of each
oscillation circuits, clock selection bits and etc
• Clock selection bits
φSOURCE can be selected by the clock selection bits (bits 5 and
4 in clock mode register). φSOURCE can be selected from lowspeed on-chip oscillator, high-speed on-chip oscillator, XIN/XCIN
oscillaton or external clock input by the clock selection bits.
φSOURCE is also used to the clock for peripheral functions.
When the oscillation method selection bits (bits 1 and 0 in
FSROM1) is set to “002” (oscillation pins not used), setting the
clock selection bits to “10 2 ” (X IN /X CIN oscillation, external
clock input) is disabled.
• Clock division ratio selection bit
The internal clock φ is generated by dividing φSOURCE.
Select the division ratio using the clock division ration selection
bits (bits 7 and 6 in CLKM).
The division ratio can be selected from among φSOURCE/8
(low-speed mode), /4 (middle-speed mode), /2 (high-speed
mode), and no division (double-speed mode).
Table 9 shows the division ratio (mode) settings.
When releasing reset, the low-speed on-chip oscillator is selected
as φSOURCE, and φSOURCE/8 is selected as the internal clock.
The high-speed on-chip oscillator is stopped at this time. If an
oscillation circuit is connected to the clock pin, oscillation starts.
To switch φSOURCE to XIN/XCIN oscillation, generate wait time
using the on-chip oscillator until the oscillation is stabilized.
Table 9
Setting the clock division (mode)
CLKM
FSROM1
bit Clock division
φSOURCE
Mode
XIN
XCIN
External
clock
ratio selection
bits
Clock
selection bits
XIN/XCIN
oscillation
control bit
High-speed on-chip Low-speed on-chip
oscillator oscillation oscillator oscillation
control bit
control bit
FSROM2
Oscillation
method
selection bits
Low-speed onchip oscillator
control bit
Bit 7, 6
Bit 5, 4
Bit 2
Bit 1
Bit 0
Bit 1, 0
Bit 4
Double-speed
11
10
0
−
−
01
−
High-speed
10
10
0
−
−
01
−
Middle-speed
01
10
0
−
−
01
−
Low-speed
00
10
0
−
−
01
−
Double-speed
11
10
0
−
−
10
−
High-speed
10
10
0
−
−
10
−
Middle-speed
01
10
0
−
−
10
−
Low-speed
00
10
0
−
−
10
−
Double-speed
11
10
−
−
−
11
−
High-speed
10
10
−
−
−
11
−
Middle-speed
01
10
−
−
−
11
−
Low-speed
00
10
−
−
−
11
−
11
01
−
0
−
−
−
10
01
−
0
−
−
−
01
01
−
0
−
−
−
00
01
−
0
−
−
−
11
00
−
−
0
−
1/0
High-speed Double-speed
on-chip
High-speed
oscillator
Middle-speed
Low-speed
Low-speed Double-speed
on-chip
High-speed
oscillator
Middle-speed
Low-speed
10
00
−
−
0
−
1/0
01
00
−
−
0
−
1/0
00
00
−
−
0
−
1/0
−: can be “0” or “1”, no change in outcome
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 48 of 81
7549 Group
• Stop mode
When the STP instruction is executed, the internal clock φ stops
at an “H” level and the XIN/XCIN and on-chip oscillator stops. At
this time, timer 1 is set to “0116” and prescaler 12 is set to “FF16”
when the oscillation stabilization time set bit after release of the
STP instruction is “0”. On the other hand, timer 1 and prescaler
12 are not set when the above bit is “1”. Accordingly, set the wait
time fit for the oscillation stabilization time of the oscillator to be
used. When an external interrupt is accepted, oscillation is
restarted but the internal clock φ remains at “H” until timer 1
underflows. As soon as timer 1 underflows, the internal clock φ
is supplied. This is because when a ceramic resonator is used,
some time is required until a start of oscillation. In case
oscillation is restarted by reset, no wait time is generated. So
apply an “L” level to the RESET pin while oscillation becomes
stable, or set the wait time by on-chip oscillator operation after
system is released from reset until the oscillation is stabled.
• Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock
restarts if a reset occurs or when an interrupt is received. Since
the oscillator does not stop, normal operation can be started
immediately after the clock is restarted. To ensure that interrupts
will be received to release the STP or WIT state, interrupt enable
bits must be set to “1” before the STP or WIT instruction is
executed.
• Note
For use with the oscillation stabilization set bit after release of
the STP instruction set to “1”, set values in timer 1 and prescaler
12 after fully appreciating the oscillation stabilization time of the
oscillator to be used.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 49 of 81
7549 Group
Bits 0 and 1 of FSROM1: setting of the oscillation method select bits
“00”: Clock pins not used
P21/X IN/XCIN
Port P21
control circuit
“01”: Ceramic or quartzcrystal oscillation
P21/X IN/XCIN
P20/X OUT/XCOUT
“10”: 32 kHz quartzcrystal oscillation
P20/X OUT/XCOUT
P21/X IN/XCIN
(Note 2)
Rf
Port P20
control circuit
P20/X OUT/XCOUT
(Note 2)
Rf
“11”: External clock input
P21/X IN/XCIN P20/X OUT/XCOUT
Port P21
control circuit
XIN/XCIN oscillation
control bit
Noise filter
“11”: Double-speed mode
Clock selection bits
1/2
“10”
High-speed on-chip
oscillator (HSOCO)
1/4
φSOURCE
“01”
1/8
“00”
Timing φ
(Internal clock)
“01”: Middle-speed mode
“00”: Low-speed mode
Clock division ratio selection bits
High-speed on-chip oscillator
oscillation control bit
XIN oscillation cannot be
selected as φSOURCE
if clock pins not used is
selected.
Low-speed on-chip
oscillator (LSOCO)
“10”: High-speed mode
Peripheral
function clock
generation circuit
(1/1 to 1/256)
1/1 to 1/256
1/16
Peripheral
function
Oscillation stabilization time set timer
after release of the STP instruction
Low-speed on-chip oscillator
oscillation control bit
It is not possible to write “1” to the low-speed on-chip
oscillator oscillation control bit if low-speed on-chip
oscillator stop has been disabled by bit 4 in FSROM2.
Also, the low-speed on-chip oscillator does not stop
even if the STP instruction is executed.
Timer 1
S
Reset
STP instruction
Q
S
R
Prescaler 12
R
S
STP instruction
WIT
instruction
Q
Q
R
Reset
Interrupt disable flag I
Interrupt request
Notes 1: The oscillation circuit is built in the P20/XOUT/XCOUT pin and the P21/XIN/XCIN pin. When the Vcc of the microcomputer
is lower than the operation lower bound voltage even if these pins are used as I/O ports, the oscillation circuit is
connected and undefined values may be output from these pins.
2: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions.
Fig 65. Block diagram of internal clock generating circuit
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 50 of 81
7549 Group
State transition of clock mode register CLKM (address: 003716) setting value and clock
(When XIN oscillation is used. The same applies when XCIN oscillation and external clock input are used.)
φS
OU
XIN
se RCE
lec
tio
(b5 XIN
n
Oscillation Stop (b2=1)
,4=
(b2=0)
HS
O
(b5 CO
,4=
0,1
)
3)
ote 1,0)
3)
b5
,
(N 4
ote
XIN “O”
• HSOCO
LSOCO “O”
xx01x000
Os
XIN “O”
HSOCO “O”
• LSOCO
xx00x000
O
S
(b1 top
=1
)
,1
XIN “S”
HSOCO “S”
• LSOCO
xx00x110
b2
b1
b1
,1
b2
)
• XIN
HSOCO “S”
LSOCO “O”
xx10x010
XIN oscillation:
oscillation start (Note 3)
b2=0
b5,4
(Note 3)
on
ati
cill
Os =0)
(b0
XIN
(b5,4=1,0)
O
C
(Note 3)
O
p
Sto =1)
LS
(b0
[Remarks]
b5,4
(Note 3)
OC
b2
(N b0
ote
1
XIN “O”
HSOCO “S”
• LSOCO
xx00x010
HS
b1
,0
b1 )
1
ote
• XIN
HSOCO “O”
b5,4
LSOCO “O”
(Note 3)
xx10x000
0
b1, te 1)
o
(N
• XIN
HSOCO “S”
LSOCO “S”
xx10x011
cill
a
(b1 tion
=0
)
b2
(N
b1
(N b0
ote
1)
,4
b5
(No ,4
te
3
)
XIN “S”
HSOCO “O”
• LSOCO
xx00x100
b5
HSOCO “O”
LSOCO “S”
xx10x001
O
OC ,0)
LS ,4=0
(b5
b2
)
,4
(N
b2,0 (Note 1)
(N b0
ote
1
E
RC
OU n
φS ectio
l
se
XIN “S”
• HSOCO
LSOCO “O”
xx01x100
b2,0 (Note 1)
on
ati
cill
Os =0)
• XIN
(b1
p
Sto 1)
=
1
b
(
ote b0
1)
LSOCO
(N
b2
O
OC )
HS =0,1
,4
(b5
XIN “O”
• HSOCO
LSOCO “S”
xx01x001
Oscillation
(b0=0)
XIN “S”
• HSOCO
LSOCO “S”
xx01x101
b5
O
OC
HS
Stop (b0=1)
High-speed on-chip oscillator (HSOCO): oscillation start
b1=0
XIN “O”
HSOCO “S”
• LSOCO
xx00x010
(Note 2)
Low-speed on-chip oscillator
(LSOCO): oscillation start
b0=0
Os
cill
a
(b2 tion
=0
)
LSOCO
(b5,4=0,0)
φSOURCE selection
XIN
Reset released
S
(b2 top
=1
)
XIN, HSOCO, LSOCO, and respective oscillation and stop status in each mode are shown.
The symbol (•) indicates φSOURCE (oscillation) selected by the clock selection bits.
“O” indicates oscillation and “S” indicates stopping.
The values such as “xx00x010” indicate the values (binary) of the clock mode register in the mode.
The arrow (bx) indicates a bit in the clock mode register, showing a transition by changing the bit values.
Entering the mode should be performed according to the arrows. Wait mode and stop mode can be
entered from all modes, and the original mode is returned after exiting.
Wait mode
• Low-speed on-chip oscillator: Status before executing WIT instruction is kept
• High-speed on-chip oscillator: Status before executing WIT instruction is kept
• XIN oscillation: Status before executing the WIT instruction is kept
Stop mode
• Low-speed on-chip oscillator: Stopped (Note 1)
• High-speed on-chip oscillator: Stopped
• XIN oscillation: Stopped
Notes 1: When stopping the low-speed on-chip oscillator is disabled by the low-speed on-chip oscillator control bit (bit 4 in FSROM2),
“1” cannot be written to the bit 0 in CLKM. The low-speed on-chip oscillator does not stop even in stop mode.
2: After releasing reset, the low-speed on-chip oscillator is selected as φSOURCE and divided by 8 is selected as the CPU clock.
3: When the oscillation pins not used is set by the oscillation method selection bits (bits 1 and 0 in FSROM1), “10” cannot be
written to bits 5 and 5 in CLKM. To use XIN oscillation as φSOURCE, switch after XIN oscillation is stabilized. Supply a stable
clock when an external clock is used.
4: Do not change the values of the clock selection bits (bits 5 and 4) in CLKM and the individual clock oscillation control bits
(bits 2 to 0) at the same time using a singe instruction. Always use different instructions to rewrite these values.
5: Wait until the oscillation used in the destination mode is stabilized before entering.
Fig 66. φSOURCE state transition
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 51 of 81
7549 Group
• Oscillation stop detection circuit
The oscillation stop detection circuit is used to detect an
oscillation stop when a ceramic resonator or oscillation circuit
stops due to disconnection. To use the oscillation stop detection
circuit, set the low-speed on-chip oscillator to start operating.
The oscillation stop detection circuit is enabled by setting the
XIN oscillation stop detection function active bit to 1. While this
circuit is enabled, the operating status of the XIN oscillation
circuit is monitored using the low-speed on-chip oscillator. If an
oscillation stop is detected, the oscillation stop detection status
bit is set to 1. If the oscillation stop detection reset enable bit is
also set to 1, an internal reset is triggered at oscillation stop
detection.
The XIN oscillation stop detection function active bit and the
oscillation stop detection status bit are not initialized if an
oscillation stop detection reset is triggered and these bits retain
their value of 1. Since these bits are initialized to 0 by an external
reset, an oscillation stop detection reset can be determined by
checking the oscillation stop status bit.
The oscillation stop detection status bit is set to 0 by writing 0 to
the XIN oscillation stop detection function enable bit.
To enable the oscillation detection circuit, first write 0 to the XIN
oscillation stop detection function enable bit and set the
oscillation stop detection status bit to 0. Then set the oscillation
stop function to 1.
The XIN oscillation and external clock input are set as the clocks
for oscill ati on stop detect ion. Refer t o the el ectrica l
characteristics for the frequencies for oscillation stop detection.
b7
b0
Oscillation stop detection register
(CLKSTP: address 003816, initial value: 0016)
XIN oscillation stop detection function active bit
0: Detection function inactive
1: Detection function active
Oscillation stop detection reset enable bit
0: Oscillation stop detection reset disabled
1: Oscillation stop detection reset enabled
Oscillation stop detection status bit
0: Oscillation stop not detected
1: Oscillation stop detected
Not used (“0” at reading)
Fig 67. Structure of oscillation stop detection register
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 52 of 81
• Notes
(1) Do not execute the transition to “state 2’a” shown in Figure
68 State transition of oscillation stop detection circuit. In
this state, no reset is triggered and the MCU is stopped even
when the XIN oscillation stops.
(2) After an oscillation stop detection reset, if this reset is
enabled while bits XIN oscillation stop detection function
active and oscillation stop detection status are retained, a
reset is triggered again.
(3) The oscillation stop detection status bit is initialized under
the following conditions:
• External reset, power-on reset, low-voltage detection reset,
watchdog timer reset, and reset by the STP instruction
function.
• Write 0 to the XIN oscillation stop detection function active
bit
(4) While the oscillation stop detection function is in active, the
oscillation stop detection status bit may set to 1 when the
watchdog timer underflows or by a reset when the STP
instruction is executed with the STP instruction function
selection bit set to 1.
When an oscillation stop detection reset is triggered,
reconfirm that oscillation is stopped.
(5) The oscillation stop detection circuit is not included in the
emulator MCU “M37549RLSS”.
7549 Group
φSOURCE: XIN
φSOURCE: Low-speed on-chip oscillator (Note 4)
CLKM 54 = 102
State 2
XIN oscillation
: enabled
Low-speed on-chip oscillator : enabled
CLKSTP1 = 02
CLKSTP1 = 12 (Note 2)
(CLKSTP2 is
set to “0”.)
oscillation
: enabled
State 3 XLow-speed
on-chip oscillator : enabled
IN
Reset
released
Oscillation stop detection
circuit is in active. (Note 3)
oscillation
: enabled
State 2' XLow-speed
on-chip oscillator : enabled
CLKSTP 0 = 12
(Note 1)
State 3'
IN
CLKSTP0 = 0 2
(CLKSTP2 is set to “0”.)
External reset (RESET=“L”)
⋅ Power-on reset
⋅ Low voltage detection reset
⋅ Watchdog timer reset
⋅ Reset by STP instruction function
XIN oscillation
: enabled
Low-speed on-chip oscillator : enabled
State 3'a
Prohibitive state
Reset state 1
: enabled
XIN
High-speed on-chip oscillator: stop
Low-speed on-chip oscillator : enabled
CLKM 54 = 002
(Note 1)
Oscillation stop detection reset disabled
MCU stops when oscillation stops
occurs.
CLKM 54=102
When oscillation stop is detected;
CLKSTP2 is set to “1”.
Internal RESET does not occur.
(Note 2)
State 2'a (Note 2)
Oscillation stop detection reset disabled
When oscillation stop is detected;
CLKSTP2 is set to "1".
Internal RESET does not occur.
CLKM 54=002
(Note 1)
Reset
released
CLKSTP2 is set to “1”.
So, return from oscillation stop reset can be
confirmed.
CLKSTP1 = 12 (Note 2) CLKSTP1 = 02
State 2'b
CLKSTP1 = 12
CLKM 54 = 102
Oscillation stop detection reset enabled
When oscillation stop is detected;
CLKSTP2 is set to “1”.
Internal RESET occurs.
State 3'c
Return from oscillation stop detection reset
XIN
: enabled
High-speed on-chip oscillator : stop
Low-speed on-chip oscillator : enabled
CLKSTP1 = 02
State 3'b
Oscillation stop detection reset enabled
CLKM 54 = 002
(Note 1)
When oscillation stop is detected;
CLKSTP2 is set to “1”.
Internal RESET occurs.
Notes on switch of clock
(1) Executing the state transition after stabilizing XIN oscillation.
(2) MCU cannot be returned by on-chip oscillator and its operation is stopped since internal reset does not
occur at oscillation stop detected in state 2'a. Accordingly, do not execute the transition to state 2'a.
(3) STP instruction cannot be used when oscillation stop detection circuit is in active.
(4) The same applies when the high-speed on-chip oscillator is set as φSOURCE. Make sure that the low-speed
on-chip oscillator should also oscillate. When a reset occurs, the high-speed on-chip oscillator stops.
Fig 68. State transition of oscillation stop detection circuit
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Reset state 2
Page 53 of 81
Oscillation stop is detected
(internal reset)
7549 Group
QzROM Writing Mode
In the QzROM writing mode, the user ROM area can be written
while the microcomputer is mounted on-board by using a serial
programmer which is applicable for this microcomputer.
Table 10 lists the pin description (QzROM writing mode) and
Figure 69 shows the pin connections.
Refer to Figure 70 and Figure 71 for examples of a connection
with a serial programmer.
Contact the manufacturer of your serial programmer for serial
programmer.
Refer to the user's manual of your serial programmer for details
on how to use it.
Table 10 Pin description (QzROM writing mode)
Pin
VCC, VSS
RESET
P21 /XIN
P20 /XOUT
P00 − P05
P11 − P17
P30, P31
CNVSS
P10
P06
P07
Name
Power source
Reset input
Clock input
Clock output
I/O port
I/O
Input
Input
Input
Output
I/O
Function
Apply 2.7 to 5.5 V to VCC, and 0 V to VSS.
Reset input pin.
Set the same termination as the single-chip mode.
VPP input
ESDA I/O
ESCLK input
ESPGMB input
Input
I/O
Input
Input
QzROM programmable power source pin.
Serial data I/O pin.
Serial clock input pin.
Read/program pulse input pin.
1
24
P13/AN3/KEY3/T2OUT
P15/AN5/KEY5
2
23
P12/AN2/KEY2/CMP2
RESET
3
22
P11/AN1/KEY1/CMP1
21
P10/AN0/KEY0/CMP0
20
P31
P16/AN6/KEY6
P17/AN7/KEY7
P20/XOUT/XCOUT
VSS
GND
P21/XIN/XCIN
4
5
6
7
8
M37549G3/G2/G1FP
P14/AN4/KEY4
RESET
∗
Input “H” or “L” level signal or leave the pin open.
19
ESDA
P30
P07(LED7)/SRDY
ESPGMB
17
P06(LED6)/SCLK
ESCLK
16
P05(LED5)/TxD
18
VCC
VCC
9
VPP
CNVSS
10
15
P04(LED4)/RxD
P00(LED0)/INT0
11
14
P03(LED3)/CAP0
P01(LED1)/INT1
12
13
P02(LED2)
Package type: PRSP0024GA-A (24P2Q-A)
∗ : Set the same termination as
the single-chip mode.
: QzROM pin
Fig 69. Pin connection diagram (M37549G3/G2/G1FP)
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 54 of 81
7549 Group
7549 Group
Vcc
Vcc
CNVSS
4.7 kΩ
4.7 kΩ
P10 (ESDA)
P06 (ESCLK)
P07 (ESPGMB)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESET
circuit
*1
RESET
Vss
P21/XIN P20/XOUT
Set the same termination as
the single-chip mode.
* 1: Open-collector buffer
Note : For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF
Fig 70. When using E8 programmer, connection example
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 55 of 81
7549 Group
7549 Group
T_VDD
Vcc
T_VPP
CNVSS
4.7 kΩ
T_TXD
4.7 kΩ
T_RXD
P10 (ESDA)
T_SCLK
P06 (ESCLK)
T_BUSY
N.C.
T_PGM/OE/MD
P07 (ESPGMB)
RESET circuit
T_RESET
GND
RESET
Vss
P21/XIN
P20/XOUT
Set the same termination as
the single-chip mode.
Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
Fig 71. When using programmer of Suisei Electronics System Co., LTD, connection example
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 56 of 81
7549 Group
NOTES ON PROGRAMMING
NOTES ON HARDWARE
(1) Processor Status Register
The contents of the processor status register (PS) after reset are
undefined except for the interrupt disable flag I which is “1”.
After reset, initialize flags which affect program execution. In
particular, it is essential to initialize the T flag and the D flag
because of their effect on calculations. Initialize these flags at the
beginning of the program.
(1) Handling of Power Source Pin
(2) Interrupts
The contents of the interrupt request bit do not change even if the
BBC or BBS instruction is executed immediately after they are
changed by program because this instruction is executed for the
previous contents. For executing the instruction for the changed
contents, execute one instruction before executing the BBC or
BBS instruction.
(2) Note on Power Source Voltage
(3) Decimal Calculations
• For calculations in decimal notation, set the decimal mode
flag D to “1”, then execute the ADC instruction or SBC
instruction. In this case, execute SEC instruction, CLC
instruction or CLD in-struction after executing one
instruction before the ADC instruction or SBC instruction.
• In the decimal mode, the values of the N (negative), V
(overflow) and Z (zero) flags are invalid.
(4) Ports
The values of the port direction registers cannot be read. That is,
it is impossible to use the LDA instruction, memory operation
instruction when the T flag is “1”, addressing mode using
direction register values as qualifiers, and bit test instructions
such as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read/modify/write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA instruction, etc.
(5) A/D Conversion
Do not execute the STP instruction during A/D conversion.
(6) Instruction Execution Timing
The instruction execution time can be obtained by multiplying
the frequency of the internal clock φ by the number of cycles
mentioned in the machine-language instruction table.
The frequency of the internal clock φ is the same as that of the
φSOURCE in double-speed mode, twice the φSOURCE cycle in
high-speed mode, 4 times the φSOURCE cycle in middle-speed
mode and 8 times the φSOURCE cycle in low-speed mode.
(7) CPU Mode Register
The processor mode bits can be written only once after releasing
reset. Always set them to “002”. After written, rewriting any data
to these bits is disabled because they are locked. (Emulator MCU
is excluded.)
(8) State transition
Do not stop the clock selected as the operation clock because of
setting of bits 0 to 2.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 57 of 81
In order to avoid a latch-up occurrence, connect a capacitor
suitable for high frequencies as bypass capacitor between power
source pin (V CC pin) and GND pin (V SS pin). A ceramic
capacitor of 0.01 µF to 0.1 µF is recommended.
Connect a capacitor across the power source pin and GND pin
with the shortest possible wiring.
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and
may perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the supply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
7549 Group
NOTES ON USE
Countermeasures against noise
It is necessary not only design the system taking measures
against the noise as follows but to evaluate before actual use.
1. Shortest wiring length
(1) Package
Select the smallest possible package to make the total wiring
length short.
<Reason>
The wiring length depends on a microcomputer package. Use of
a small package, for example QFP and not DIP, makes the total
wiring length short to reduce influence of noise.
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O
pins as short as possible.
• Make the length of wiring (within 20 mm) across the
grounding lead of a capacitor which is connected to an
oscillator and the VSS pin of a microcomputer as short as
possible.
• Separate the VSS pattern only for oscillation from other
VSS patterns.
<Reason>
If noise enters clock I/O pins, clock waveforms may be
deformed. This may cause a program failure or program
runaway. Also, if a potential difference is caused by the noise
between the VSS level of a microcomputer and the VSS level of
an oscillator, the correct clock will not be input in the
microcomputer.
DIP
Noise
SDIP
SOP
QFP
XIN
XOUT
VSS
Fig 72. Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin
as short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring
(within 20 mm).
<Reason>
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is
completely initialized. This may cause a program runaway.
Noise
Reset
circuit
RESET
VSS
VSS
XIN
XOUT
VSS
N.G.
O.K.
Fig 74. Wiring for clock I/O pins
(4) Wiring to CNVSS pin
Connect CNVSS pin to a GND pattern at the shortest distance.
The GND pattern is required to be as close as possible to the
GND supplied to VSS.
In order to improve the noise reduction, to connect a 5 kΩ
resistor serially to the CNVSS pin - GND line may be valid.
As well as the above-mentioned, in this case, connect to a GND
pattern at the shortest distance. The GND pattern is required to
be as close as possible to the GND supplied to VSS.
<Reason>
The CNVSS pin of the QzROM is the power source input pin for
the built-in QzROM. When programming in the built-in
QzROM, the impedance of the CNVSS pin is low to allow the
electric current for writing flow into the QzROM. Because of
this, noise can enter easily. If noise enters the CNV SS pin,
abnormal instruction codes or data are read from the built-in
QzROM, which may cause a program runaway.
N.G.
(Note)
The shortest
CNVSS
Reset
circuit
VSS
RESET
VSS
About 5 kΩ
VSS
(Note) The shortest
O.K.
Note: This indicates pin.
Fig 73. Wiring for the RESET pin
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 58 of 81
Fig 75. Wiring for the VPP pin of the QzPROM
7549 Group
2. Connection of bypass capacitor across VSS line
and VCC line
Connect an approximately 0.1 µF bypass capacitor across the
VSS line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC
pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC
pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for
VSS line and VCC line.
• Connect the power source wiring via a bypass capacitor to
the VSS pin and the VCC pin.
<Reason>
Signal lines where potential levels change frequently (such as the
CNTR pin signal line) may affect other lines at signal rising edge
or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure
or a program runaway.
(1) Keeping oscillator away from large current
signal lines
Microcomputer
Mutual inductance
M
VCC
VCC
XIN
XOUT
VSS
Large
current
GND
VSS
N.G.
VSS
(2) Installing oscillator away from signal lines
where potential levels change frequently
O.K.
N.G.
Do not cross
CNTR
Fig 76. Bypass capacitor across the VSS line and the
VCC line
3. Wiring to analog input pins
The analog input pin is connected to the capacitor of a voltage
comparator. Accordingly, sufficient accuracy may not be
obtained by the charge/discharge current at the time of A/D
conversion when the analog signal source of high-impedance is
connected to an analog input pin. In order to obtain the A/D
conversion result stabilized more, please lower the impedance of
an analog signal source, or add the smoothing capacitor to an
analog input pin.
4. Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as
possible from signal lines where a current larger than the tolerance of current value flows.
<Reason>
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise
occurs because of mutual inductance.
(2) Installing oscillator away from signal lines where potential
levels change frequently
Install an oscillator and a connecting pattern of an oscillator
away from signal lines where potential levels change frequently.
Also, do not cross such signal lines over the clock lines or the
signal lines which are sensitive to noise.
XIN
XOUT
VSS
Fig 77. Wiring for a large current signal line/Writing of signal
lines where potential levels change frequently
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print a VSS pattern on
the underside (soldering side) of the position (on the component
side) where an oscillator is mounted.
Connect the VSS pattern to the microcomputer VSS pin with the
shortest possible wiring. Besides, separate this VSS pattern from
other VSS patterns.
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig 78. VSS pattern on the underside of an oscillator
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 59 of 81
7549 Group
5. Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program
for checking whether input levels are equal or not.
• As for an output port, since the output data may reverse
because of noise, rewrite data to its port latch at fixed
periods.
• Rewrite data to direction registers and pull-up control
registers at fixed periods.
Noise
O.K.
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
Fig 79. Setup for I/O ports
6. Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can
be detected by a software watchdog timer and the microcomputer
can be reset to normal operation. This is equal to or more
effective than program runaway detection by a hardware
watchdog timer. The following shows an example of a watchdog
timer provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing
routine and the interrupt processing routine detects errors of the
main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog
timer (SWDT) and writes the initial value N in the SWDT
once at each execution of the main routine. The initial
value N should satisfy the following condition:
N + 1 ≥ (Counts of interrupt processing executed in each
main routine)
As the main routine execution cycle may change because
of an interrupt processing or others, the initial value N
should have a margin.
• Watches the operation of the interrupt processing routine
by comparing the SWDT contents with counts of interrupt
processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and
determines to branch to the program initialization routine
for recovery processing in the following case:
If the SWDT contents do not change after interrupt
processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt
processing.
• Determines that the main routine operates normally when
the SWDT contents are reset to the initial value N at almost
fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to
branch to the program initialization routine for recovery
processing in the following case:
If the SWDT contents are not initialized to the initial value
N but continued to decrement and if they reach 0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT) ← N
(SWDT) ← (SWDT)−1
CLI
Interrupt processing
Main processing
(SWDT)
≤0?
≤0
(SWDT)
=N?
N
Interrupt processing
routine errors
Page 60 of 81
RTI
Return
Main routine
errors
Fig 80. Watchdog timer by software
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
>0
7549 Group
NOTES ON QzROM
Product shipped in blank
As for the product shipped in blank, Renesas does not perform
the writing test to user ROM area after the assembly process
though the QzROM writing test is performed enough before the
assembly process. Therefore, a writing error of approx.0.1 %
may occur.
Moreover, please note the contact of cables and foreign bodies
on a socket, etc. because a writing environment may cause some
writing errors.
Overvoltage
Take care not to apply the voltage above the Vcc pin voltage to
other pins. Make sure that the voltage of the CNVSS pin (VPP
power input pin for QzROM) does not change as shown in the
bold-lined periods (Figure 81) when powering on and off. If the
voltage changes as shown, the QzROM contents may be
rewritten.
~
~
(1)
(2)
1.8 V
1.8 V
VCC pin voltage
~
~
CNVSS pin voltage
(1) The input voltage to other MCU pins rises before the V CC pin
voltage rises.
(2) The input voltage to other MCU pins falls before the V CC pin
voltage falls.
Note: If V CC falls below the minimum value 1.8 V (shaded areas),
the internal circuit becomes unstable. Take additional care
to prevent overvoltage.
Fig 81. Timing Diagram (bold-lined periods are applicable)
Notes On QzROM Writing Orders
When ordering the QzROM product shipped after writing,
submit the mask file (extension: .mask) which is made by the
mask file converter MM.
• Be sure to set the ROM option data* setup when making the
mask file by using the mask file converter MM.. The ROM
code protect is specified according to the ROM option data* in
the mask file which is submitted at ordering. Note that the
mask file which has nothing at the ROM option data* or has
the data other than “0016” and “FF16” can not be accepted.
• Set “FF16” to the ROM code protect address in ROM data
regardless of the presence or absence of a protect. When data
other than “FF16” is set, we may ask that the ROM data be
submitted again.
* ROM option data: mask option noted in MM
<DATA REQUIRED FOR QzROM WRITING ORDERS
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
2. Mark Specification Form*
3. ROM data .......... Mask file
* For the QzROM writing confirmation form and the mark
specification form, refer to the “Renesas Technology Corp.”
Homepage (http://www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 61 of 81
7549 Group
ELECTRICAL CHARACTERISTICS of 7549 Group
(1) Absolute Maximum Ratings
Table 11 Absolute maximum ratings
Symbol
Parameter
VCC
Power source voltage
VI
Input voltage
P00−P07, P10−P17, P20, P21, P30, P31
______
Conditions
All voltages are based
on VSS.
When an input voltage
is measured, output
transistors are cut off.
Ratings
Unit
−0.3 to 6.5
V
−0.3 to VCC + 0.3
V
−0.3 to VCC + 0.3
V
−0.3 to VCC + 0.3
V
−0.3 to VCC + 0.3
V
VI
Input voltage RESET
VI
Input voltage CNVSS
VO
Output voltage
P00−P07, P10−P17, P20, P21, P30, P31
Pd
Power dissipation
300
mW
Topr
Operating temperature
−
−20 to 85
°C
Tstg
Storage temperature
−
−40 to 125
°C
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Ta = 25 °C
Page 62 of 81
7549 Group
(2) Recommended Operating Conditions
Table 12 Recommended operating conditions (1)
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol
VCC
Limits
Parameter
Power
source
voltage
Unit
Min.
Typ.
Max.
High-speed on-chip
oscillator
Double-, high-, middle-, low-speed mode
4.0
5.0
5.5
V
Low-speed on-chip
oscillator
Double-, high-, middle-, low-speed mode
1.8
5.0
5.5
V
f(XIN) ≤ 8MHz
4.5
5.0
5.5
V
f(XIN) ≤ 2MHz
2.4
5.0
5.5
V
f(XIN) ≤ 1MHz
2.2
5.0
5.5
V
f(XIN) ≤ 8MHz
4.0
5.0
5.5
V
f(XIN) ≤ 4MHz
2.4
5.0
5.5
V
f(XIN) ≤ 1MHz
1.8
5.0
5.5
V
f(XCIN) ≤ 50kHz
1.8
5.0
5.5
V
XIN oscillation,
external clock input
Double-speed mode
High-, middle-,
low-speed mode
XCIN oscillation
Double-, high-, middle-,
low-speed mode
VSS
Power source voltage
VIH
“H” input voltage (Note 4)
P00−P07, P10−P17, P21, P30, P31
0.8VCC
VCC
V
VIH
“H” input
voltage (Note 5)
______
RESET, XIN, XcIN
0.8VCC
VCC
V
VIL
“L” input voltage (Note 4)
P00−P07, P10−P17, P21, P30, P31
0
0.2VCC
V
VIL
“L” input______
voltage
RESET, CNVSS
0
0.2VCC
V
VIL
“L” input voltage (Note 5)
XIN, XcIN
0
0.16VCC
V
ΣIOH(peak)
“H” total peak output current (Notes 1, 4)
P00−P07, P10−P17, P20, P21, P30, P31
−60
mA
ΣIOL(peak)
“L” total peak output current (Note 1)
P00−P07
60
mA
ΣIOL(peak)
“L” total peak output current (Notes 1, 4)
P10−P17, P20, P21, P30, P31
60
mA
ΣIOH(avg)
“H” total average output current (Notes 1, 4)
P00−P07, P10−P17, P20, P21, P30, P31
−30
mA
ΣIOL(avg)
“L” total average output current (Note 1)
P00−P07
30
mA
ΣIOL(avg)
“L” total average output current (Notes 1, 4)
P10−P17, P20, P21, P30, P31
30
mA
IOH(peak)
“H” peak output current (Notes 2, 4)
P00−P07, P10−P17, P20, P21, P30, P31
−10
mA
IOL(peak)
“L” peak output current (Notes 2, 4)
P00−P07 (drive capacity: weakness), P10−P17, P20, P21, P30, P31
10
mA
IOL(peak)
“L” peak output current (Note 2)
P00−P07 (drive capacity: strength)
30
mA
IOH(avg)
“H” average output current (Notes 3, 4)
P00−P07, P10−P17, P20, P21, P30, P31
−5
mA
IOL(avg)
“L” average output current (Notes 3, 4)
P00−P07 (drive capacity: weakness), P10−P17, P20, P21, P30, P31
5
mA
IOL(avg)
“L” average output current (Notes 3)
P00−P07 (drive capacity: strength)
15
mA
0
V
NOTES:
1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average
value measured over 100 ms. The total peak current is the peak value of all the currents.
2. The peak output current is the peak current flowing in each port.
3. The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
4. P20 and P21 indicates these pins are used as I/O ports.
5. XIN and XCIN indicates these pins are used as clock pins.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 63 of 81
7549 Group
Table 13 Recommended operating conditions (2)
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
f(XIN)
XIN oscillation
frequency (Note 1)
XIN oscillation
External clock input
Double-speed mode
Vcc = 4.5−5.5 V
8
Vcc = 2.2−2.4 V
Vcc = 4.0−5.5 V
(Vcc − 2.4)
+4
0.4
(Vcc − 1.8)
+1
0.2
Vcc = 1.8−2.4 V
XCIN oscillation
frequency (Note 1)
XCIN oscillation
Vcc = 1.8−5.5 V
32.768
MHz
MHz
MHz
8
Vcc = 2.4−4.0 V
Double-, high-, middle-,
low-speed mode
MHz
(Vcc − 2.4) × 2
+2
0.7
(Vcc − 2.2)
+1
0.2
Vcc = 2.4−4.5 V
High-, middle-,
low-speed mode
Unit
Max.
Typ.
50
MHz
MHz
kHz
NOTE:
1. When the oscillation frequency has a duty cycle of 50 %.
Oscillation frequency: XIN(MHz)
8.0
When XIN is used, the MCU can be
operated within the range shown in
diagonal lines.
Confirm that the oscillation is stable
within the operating supply voltage
range before use.
Contact the oscillator manufacturer
for oscillation constants.
XIN oscillation
High-, middle-,
low-speed mode
XIN oscillation
Double-speed mode
High-speed on-chip oscillator
(5 V/Typ:4 MHz)
Double-, high-, middle-,
low-speed mode
4.0
2.0
1.0
Low-speed on-chip oscillator (5 V/Typ:250 kHz)//Double-, high-, middle-, low-speed mode
XCIN oscillation//Double-, high-, middle-, low-speed mode
0.0
0.0
1.5
2.0
3.0
2.5
3.5
Power source voltage: Vcc(V)
Fig 82. Power source voltage and oscillation frequency
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 64 of 81
4.0
4.5
5.0
5.5
7549 Group
(3) Electrical Characteristics
Table 14 Electrical characteristics (1)
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
“H” output voltage (Notes 1, 3)
P00−P07, P10−P17, P21, P30, P31
VOH
“L” output voltage (Note 1)
P00−P07 (drive capacity: weakness)
P10−P17, P21, P30, P31
VOL
“L” output voltage
P00−P07 (drive capacity: strength)
VOL
VT+ − VT-
IIH
IIH
IIH
IIH
IIL
IIL
IIL
IIL
IIL
RPH
VRAM
RHSOCO
Hysteresis
Min.
Typ.
Max.
Unit
IOH = −5 mA, Vcc = 4.0−5.5 V
Vcc−1.5
V
IOH = −1.0 mA, Vcc = 1.8−5.5 V
Vcc−1.0
V
IOL = 5 mA, Vcc = 4.0−5.5 V
1.5
V
IOL = 1.5 mA, Vcc = 4.0−5.5 V
0.3
V
IOL = 1.0 mA, Vcc = 1.8−5.5 V
1.0
V
IOL = 15 mA, Vcc = 4.0−5.5 V
2.0
V
IOL = 1.5 mA, Vcc = 4.0−5.5 V
0.3
V
IOL = 1.0 mA, Vcc = 1.8−5.5 V
1.0
V
INT0, INT1, CAP0,
P10−P17 (Note 4)
RXD, SCLK, RESET
0.5
V
“H” input current (Note 1)
P00−P07, P10−P17, P21, P30, P31
VI = Vcc
(Pin floating. Pull up transistors is disable)
“H” input current
RESET
VI = Vcc
“H” input current (Note 2)
XIN
VI = Vcc
4.0
µA
“H” input current (Note 2)
XCIN
VI = Vcc
0.5
µA
5.0
µA
5
µA
“L” input current (Note 1)
P00−P07, P10−P17, P21, P30, P31
VI = Vss
(Pin floating. Pull up transistors is disable)
−5.0
µA
“L” input current
RESET
VI = Vss
−0.7
mA
“L” input current (Note 2)
XIN
VI = Vss
−4.0
µA
“L” input current (Note 2)
XCIN
VI = Vss
−0.3
µA
“L” input current
P00−P07, P10−P17
VI = Vss
(Pull up transistors is enable)
−0.2
Pull-up resistor value
RESET
VI = Vss
−0.5
25
mA
kΩ
RAM hold voltage
When clock stopped
1.6
5.5
High-speed on-chip oscillator
oscillation frequency
Vcc = 4.0−5.5 V, Ta = 0−50 °C
3.8
4
4.2
Vcc = 4.0−5.5 V, Ta = −20−85 °C
3.6
4
4.4
V
MHz
RLSOCO
Low-speed on-chip oscillator
oscillation frequency
Vcc = 5.0 V, Ta = 25 °C
125
250
500
kHz
DOSC
Oscillation stop detection circuit
detection frequency
Vcc = 5.0 V, Ta = 25 °C
62.5
150
250
kHz
NOTES:
1.
2.
3.
4.
P20 and P21 indicates these pins are used as I/O ports.
XIN and XCIN indicates these pins are used as clock pins.
P05 is measured when the P05/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
It is available only when operating key-on wake up.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 65 of 81
7549 Group
Table 15 Electrical characteristics (2)
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Icc
Power
source
current
Test conditions
Min.
Typ.
Max.
Unit
High-speed on-chip oscillator: oscillation
· Vcc = 5.0 V
· Low-speed on-chip oscillator: stop
· XIN: stop
· Output transistors “off”
· Low voltage detection circuit: enable
Double-speed mode
2.5
5.2
mA
Low-speed mode
0.6
1.7
mA
Wait mode, functions except
timer 1 disabled
0.35
1.0
mA
Low-speed on-chip oscillator: oscillation
· Vcc = 5.0 V
· High-speed on-chip oscillator: stop
· XIN: stop
· Output transistors “off”
· Low voltage detection circuit: enable
Double-speed mode
230
600
µA
Low-speed mode
120
400
µA
Wait mode, functions except
timer 1 disabled
105
350
µA
f(XIN)=8 MHz (ceramic resonator)
· Vcc = 5.0 V
· High-speed on-chip oscillator: stop
· Low-speed on-chip oscillator: stop
· Output transistors “off”
· Low voltage detection circuit: enable
Double-speed mode
6.0
10
mA
Low-speed mode
2.6
6.0
mA
Wait mode, functions except
timer 1 disabled
1.9
5.0
mA
f(XCIN)=32.768 kHz
· Vcc = 5.0 V
· High-speed on-chip oscillator: stop
· Low-speed on-chip oscillator: stop
· Output transistors “off”
· Low voltage detection circuit: enable
Double-speed mode
100
200
µA
Low-speed mode
85
180
µA
Wait mode, functions except
timer 1 disabled
80
170
µA
Low-speed mode
25
70
µA
Wait mode, functions except
timer 1 disabled
23
60
µA
Low-speed mode
190
450
µA
Wait mode, functions except
timer 1 disabled
150
430
µA
Low-speed mode
24
65
µA
Wait mode, functions except
timer 1 disabled
23
55
µA
Ta = 25 °C
Vcc = 5.0 V
70
µA
Ta = 25 °C
Vcc = 2.0 V
20
µA
0.5
mA
Low-speed on-chip oscillator: oscillation
· Vcc = 2.0 V
· High-speed on-chip oscillator: stop
· XIN: stop
· Output transistors “off”
· Low voltage detection circuit: enable
f(XIN) = 2 MHz (ceramic resonator)
· Vcc = 2.0 V
· High-speed on-chip oscillator: stop
· Low-speed on-chip oscillator: stop
· Output transistors “off”
· Low voltage detection circuit: enable
f(XCIN) = 32.768 kHz
· Vcc = 2.0 V
· High-speed on-chip oscillator: stop
· Low-speed on-chip oscillator: stop
· Output transistors “off”
· Low voltage detection circuit: enable
Low voltage detection circuit self
consumption current
Increment when A/D conversion is executed
f(XIN) = 8 MHz,, Vcc = 5.0 V
Stop mode
· Output transistors “off”
· Low-speed on-chip oscillator: stop
· Low voltage detection circuit: stop
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 66 of 81
Ta = 25 °C
Ta = 85 °C
0.1
1.0
µA
10
µA
7549 Group
(4) A/D Converter Characteristics
Table 16 A/D Converter characteristics
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Min.
Typ.
10
bits
3
LSB
A/D conversion clock = f(φSOURCE)/2
122
tc(φSOURCE)
A/D conversion clock = f(φSOURCE)
61
tc(φSOURCE)
Resolution
Absolute accuracy
(excluding quantization error)
tCONV
Conversion time
RLADDER
Ladder resistor
II(AD)
A/D port input current
Unit
Max.
Ta = −20−85 °C, 2.7 ≤ Vcc ≤ 5.5 V
kΩ
55
µA
5.0
Table 17 A/D Converter Recommended Operating Conditions
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol
Parameter
VCC
Power source voltage
φ(AD)
A/D conversion clock
frequency (Note)
Test conditions
Limits
Min.
Typ.
Unit
Ta = −20−85 °C
2.7
5.5
V
4.0 ≤ Vcc ≤ 5.5 V
0.016
8
MHz
2.7 ≤ Vcc < 4.0 V
0.016
4
MHz
NOTE:
1. When XCIN or the low-speed on-chip oscillator is selected as φSOURCE, the A/D converter cannot be used.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Max.
Page 67 of 81
7549 Group
(5) Power-on reset circuit characteristics
Table 18 Power-on reset circuit characteristics
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
VPOR
Valid start voltage of power-on reset circuit (Note)
TW(VPOR)
VPOR hold time
TW(VPOR-VDET)
Rising time of valid power source of power-on reset circuit
Limits
Typ.
Min.
Max.
0
10
Unit
V
s
20
TW(VPOR) > 10s
ms
NOTE:
VPOR is the start voltage level of Vcc for the built-in power-on reset circuit to operate normally.
Keep VPOR to be lower than the Vcc voltage before rising of the Vcc power source to use the built-in power-on reset circuit.
Set the built-in low voltage detection circuit to be valid when the built-in power-on reset is used.
Table 19 Low voltage detection circuit characteristics
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol
Test conditions
Parameter
VLVD
Valid start voltage of low voltage detection circuit (Note)
VDET
Detection voltage of low voltage detection circuit
TDET
Detection time of low voltage detection circuit
Limits
Min.
Typ.
Max.
Unit
V
1.0
Ta = 0 50 °C
1.85
1.95
2.05
V
Ta = 20 85 °C
1.80
1.95
2.10
V
20
s
NOTE:
VLVD is the start voltage level of Vcc for the built-in low voltage detection circuit to operate normally.
If the Vcc power source becomes lower than VLVD, first set the Vcc voltage to be lower than VPOR. Next, according to the electrical
characteristics of the power-on reset circuit, perform the rising of Vcc.
VDET
Vcc power source
waveform
VLVD
VPOR
0V
TW(VPOR)
T(VPOR-VDET)
TDET
Internal reset signal
Power-on reset circuit
characteristics
Low voltage detection circuit
characteristics
Fig 83. Electrical characteristics of power-on reset circuit and low voltage detection circuit
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 68 of 81
7549 Group
(6) Timing Requirements
Table 20 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
______
tW(RESET)
Reset input “L” pulse width
Unit
2
µs
tC(XIN)
External clock input cycle time
125
ns
tWH(XIN)
External clock input “H” pulse width
50
ns
tWL(XIN)
External clock input “L” pulse width
50
ns
tWH(INT0)
INT0, INT1, CAP0 input “H” pulse width (Note 1)
80
ns
tWL(INT0)
INT0, INT1, CAP0 input “L” pulse width (Note 1)
80
ns
tC(SCLK)
Serial I/O clock input cycle time (Note 2)
800
ns
tWH(SCLK)
Serial I/O clock input “H” pulse width (Note 2)
370
ns
tWL(SCLK)
Serial I/O clock input “L” pulse width (Note 2)
370
ns
tsu(RXD-SCLK)
Serial I/O input set up time
220
ns
th(SCLK-RXD)
Serial I/O input hold time
100
ns
NOTES:
1. As for CAP0, it is the value when noise filter is not used.
2. In this time, bit 6 of the serial I/O control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.
Table 21 Timing requirements (2)
(VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
______
tW(RESET)
Reset input “L” pulse width
2
µs
tC(XIN)
External clock input cycle time
250
ns
tWH(XIN)
External clock input “H” pulse width
100
ns
tWL(XIN)
External clock input “L” pulse width
100
ns
tWH(INT0)
INT0, INT1, CAP0 input “H” pulse width (Note 1)
230
ns
tWL(INT0)
INT0, INT1, CAP0 input “L” pulse width (Note 1)
230
ns
tC(SCLK)
Serial I/O clock input cycle time (Note 2)
2000
ns
tWH(SCLK)
Serial I/O clock input “H” pulse width (Note 2)
950
ns
tWL(SCLK)
Serial I/O clock input “L” pulse width (Note 2)
950
ns
tsu(RXD-SCLK)
Serial I/O input set up time
400
ns
th(SCLK-RXD)
Serial I/O input hold time
200
ns
NOTES:
1. As for CAP0, it is the value when noise filter is not used.
2. In this time, bit 6 of the serial I/O control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 69 of 81
7549 Group
Table 22 Timing requirements (3)
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
______
tW(RESET)
Reset input “L” pulse width
2
µs
tC(XIN)
External clock input cycle time
500
ns
tWH(XIN)
External clock input “H” pulse width
200
ns
tWL(XIN)
External clock input “L” pulse width
200
ns
tWH(INT0)
INT0, INT1, CAP0 input “H” pulse width (Note 1)
460
ns
tWL(INT0)
INT0, INT1, CAP0 input “L” pulse width (Note 1)
460
ns
tC(SCLK)
Serial I/O clock input cycle time (Note 2)
4000
ns
tWH(SCLK)
Serial I/O clock input “H” pulse width (Note 2)
1900
ns
tWL(SCLK)
Serial I/O clock input “L” pulse width (Note 2)
1900
ns
tsu(RXD-SCLK)
Serial I/O input set up time
800
ns
th(SCLK-RXD)
Serial I/O input hold time
400
ns
NOTES:
1. As for CAP0, it is the value when noise filter is not used.
2. In this time, bit 6 of the serial I/O control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 70 of 81
7549 Group
(7) Switching Characteristics
Table 23 Switching characteristics (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
tWH(SCLK)
Serial I/O clock output “H” pulse width
tC(SCLK)/2−30
ns
tWL(SCLK)
Serial I/O clock output “L” pulse width
tC(SCLK)/2−30
ns
td(SCLK-TXD)
Serial I/O output delay time
tV(SCLK-TXD)
Serial I/O output valid time
tr(SCLK)
Serial I/O clock output rising time
140
−30
ns
ns
30
ns
tf(SCLK)
Serial I/O clock output falling time
30
ns
tr(CMOS)
CMOS output rising time (Note 1)
10
30
ns
tf(CMOS)
CMOS output falling time (Note 1)
10
30
ns
NOTE:
1. Pin XOUT is excluded.
Table 24 Switching characteristics (2)
(VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
tWH(SCLK)
Serial I/O clock output “H” pulse width
tC(SCLK)/2−50
ns
tWL(SCLK)
Serial I/O clock output “L” pulse width
tC(SCLK)/2−50
ns
td(SCLK-TXD)
Serial I/O output delay time
tV(SCLK-TXD)
Serial I/O output valid time
tr(SCLK)
Serial I/O clock output rising time
50
ns
tf(SCLK)
Serial I/O clock output falling time
50
ns
tr(CMOS)
CMOS output rising time (Note 1)
20
50
ns
tf(CMOS)
CMOS output falling time (Note 1)
20
50
ns
350
−30
ns
ns
NOTE:
1. Pin XOUT is excluded.
Table 25 Switching characteristics (3)
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
tWH(SCLK)
Serial I/O clock output “H” pulse width
tC(SCLK)/2−70
tC(SCLK)/2−70
Typ.
Max.
Unit
ns
tWL(SCLK)
Serial I/O clock output “L” pulse width
td(SCLK-TXD)
Serial I/O output delay time
tV(SCLK-TXD)
Serial I/O output valid time
tr(SCLK)
Serial I/O clock output rising time
70
ns
tf(SCLK)
Serial I/O clock output falling time
70
ns
tr(CMOS)
CMOS output rising time (Note 1)
25
70
ns
tf(CMOS)
CMOS output falling time (Note 1)
25
70
ns
NOTE:
1. Pin XOUT is excluded.
Measured
output pin
100 pF
CMOS output
Fig 84. Switching characteristics measurement circuit diagram
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 71 of 81
ns
450
−30
ns
ns
7549 Group
tWL(INT0)
tWH(INT0)
INT0, INT1
CAP0
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
tf
SCLK
0.2VCC
tWL(SCLK)
tC(SCLK)
tr
0.8VCC
0.2VCC
tsu(RxD-SCLK)
th(SCLK-RxD)
0.8VCC
0.2VCC
RXD (at receive)
td(SCLK-TxD)
TXD (at transmit)
Fig 85. Timing chart
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
tWH(SCLK)
Page 72 of 81
tv(SCLK-TxD)
7549 Group
PACKAGE OUTLINE
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas
Technology website.
JEITA Package Code
P-SSOP24-5.3x10.1-0.80
RENESAS Code
PRSP0024GA-A
Previous Code
24P2Q-A
MASS[Typ.]
0.2g
E
13
*1
HE
24
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
F
1
12
Index mark
c
A2
A1
D
L
A
*2
e
*3
y
bp
Detail F
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 73 of 81
Reference
Symbol
D
E
A2
A
A1
bp
c
HE
e
y
L
Dimension in Millimeters
Min Nom Max
10.0 10.1 10.2
5.2 5.3 5.4
1.8
2.1
0.1 0.2
0
0.3 0.35 0.45
0.18 0.2 0.25
0°
8°
7.5 7.8 8.1
0.65 0.8 0.95
0.10
0.4 0.6 0.8
7549 Group
APPENDIX
Note on Programming
1. Processor Status Register
(1) Initialization of the processor status register
It is required to initialize the processor status register (PS) flags
which affect program execution. It is particularly essential to
initialize the T and D flags because of their effect on
calculations. Initialize these flags at the beginning of the
program.
<Reason>
At a reset, the contents of the processor status register (PS) are
undefined except for the I flag which is “1”.
Reset
Initialize the flags
Main program
Fig. 86 Initialization of processor status register flags
(2) How to refer the processor status register
To refer the contents of the processor status register (PS),
execute the PHP instruction once and then read the contents of
(S+1). If necessary, execute the PLP instruction to return the
stored PS to its original status.
Execute the ADC or SBC instruction
NOP
Execute the SEC, CLC, or CLD instruction
Fig 88. Instructions for decimal calculations
(2) Status flag at decimal calculations
When the ADC or SBC instruction is executed in decimal mode
(D flag = “1”), three of the status flags (N, V, and Z) are
disabled.
The carry (C) flag is set to “1” if a carry is generated and is
cleared to “0” if a borrow is generated as a result of a calculation,
so it can be used to determine whether the calculation has
generated a carry or borrow.
Initialize the C flag before each calculation.
Stored PS
Fig 87. Stack memory contents after PHP instruction
execution
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Set the decimal mode (D) flag to “1”
3. JMP Instruction
When using the JMP instruction (indirect addressing mode), do
not specify the address where “FF16” is allocated to the loworder 8 bits as the operand.
(S)
(S) + 1
2. Decimal Calculations
(1) Instructions for decimal calculations
To perform decimal calculations, set the decimal mode (D) flag
to “1” with the SED instruction and execute the ADC or SBC
instruction. In that case, after the ADC or SBC instruction,
execute another instruction before the SEC, CLC, or CLD
instruction.
Page 74 of 81
4. Multiplication and Division Instructions
(1) The MUL and DIV instructions are not affected by the T
and D flags.
(2) Executing these instructions does not change the contents of
the processor status register.
7549 Group
5. Read-Modify-Write Instruction
Do not execute any read-modify-write instruction to the read
invalid (address) SFR.
The read-modify-write instruction reads 1-byte of data from
memory, modifies the data, and writes 1-byte the data to the
original memory.
In the 740 Family, the read-modify-write instructions are the
following:
(1) Bit handling instructions:
CLB, SEB
(2) Shift and rotate instructions:
ASL, LSR, ROL, ROR, RRF
(3) Add and subtract instructions:
DEC, INC
(4) Logical operation instructions (1’s complement):
COM
Although not the read-modify-write instructions, add and
subtract/logical operation instructions (ADC, SBC, AND, EOR,
and ORA) when T flag = “1” operate in the way as the readmodify-write instruction. Do not execute them to the read invalid
SFR.
<Reason>
When the read-modify-write instruction is executed to the read
invalid SFR, the following may result:
As reading is invalid, the read value is undefined. The instruction
modifies this undefined value and writes it back, so the written
value will be indeterminate.
Notes on Peripheral Functions
Notes on I/O Ports
1. Pull-up control register
When using each port which built in pull-up resistor as an output
port, the pull-up control bit of corresponding port becomes
invalid, and pull-up resistor is not connected.
<Reason>
Pull-up control is effective only when each direction register is
set to the input mode.
2. Use in Stand-By State
When using the MCU in stand-by state* 1 for low-power
consumption, do not leave the input level of an I/O port
undefined. Be especially careful to the I/O ports for the Nchannel open-drain.
In this case, pull-up (connect to Vcc) or pull-down (connect to
Vss) these ports through a resistor.
When determining a resistance value, note the following:
• External circuit
• Variation in the output level during ordinary operation
When using a built-in pull-up resistor, note variations in current
values:
• When setting as an input port: Fix the input level
• When setting as an output port: Prevent current from
flowing out externally.
<Reason>
Even if a port is set to output by the direction register, when the
content of the port latch is “1”, the transistor becomes the OFF
state, which allows the port to be in the high-impedance state.
This may cause the level to be undefined depending on external
circuits.
As described above, if the input level of an I/O port is left
undefined, the power source current may flow because the
potential applied to the input buffer in the MCU will be unstable.
*1 Stand-by state: Stop mode by executing the STP instruction
Wait mode by executing the WIT instruction
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 75 of 81
7549 Group
3. Modifying Output Data with Bit Handling
Instruction
When the port latch of an I/O port is modified with the bit
handling instruction* 1 , the value of an unspecified bit may
change.
<Reason>
I/O ports can be set to input mode or output mode in byte units.
When the port register is read or written, the following will be
operated:
• Port as input mode
Read: Read the pin level
Write: Write to the port latch
• Port as output mode
Read: Read the port latch or peripheral function output
(specifications vary depending on the port)
Write: Write to the port latch (output the content of the port
latch from the pin)
Meanwhile, the bit handling instructions are the read-modifywrite instructions*2. Executing the bit handling instruction to the
port register allows reading and writing a bit unspecified with the
instruction at the same time.
If an unspecified bit is set to input mode, the pin level is read and
the value is written to the port latch. At this time, if the original
content of the port latch and the pin level do not match, the
content of the port latch changes.
If an unspecified bit is set to output mode, the port latch is
normally read, but the peripheral function output is read in some
ports and the value is written to the port latch. At this time, if the
original content of the port latch and the peripheral function
output do not match, the content of the port latch changes.
*1 Bit handling instructions: CLB, SEB
*2 Read-modify-write instruction: Reads 1-byte of data from
memory, modifies the data, and writes 1-byte of the data to
the original memory.
4. Direction Registers
The values of the port direction registers cannot be read. This
means, it is impossible to use the LDA instruction, memory
operation instruction when the T flag is “1”, addressing mode
using direction register values as qualifiers, and bit test
instructions such as BBC and BBS. It is also impossible to use bit
operation instructions such as CLB and SEB, and read-modifywrite instructions to direction registers, including calculations
such as ROR. To set the direction registers, use instructions such
as LDM or STA.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 76 of 81
Termination of Unused Pins
1. Terminate unused pins
Perform the following wiring at the shortest possible distance (20
mm or less) from microcomputer pins.
(1) I/O ports
Set the I/O ports for the input mode and connect each pin to VCC
or VSS through each resistor of 1 kΩ to 10 kΩ. The port which
can select a built-in pull-up resistor can also use the built-in pullup resistor.
When using the I/O ports as the output mode, open them at “L”
or “H”.
• When opening them in the output mode, the input mode of the
initial status remains until the mode of the ports is switched
over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source
current may increase in the input mode. With regard to an
effects on the system, thoroughly perform system evaluation
on the user side.
• Since the direction register setup may be changed because of a
program runaway or noise, set direction registers by program
periodically to increase the reliability of program.
2. Termination remarks
(1) I/O ports setting as input mode
[1] Do not open in the input mode.
<Reason>
• The power source current may increase depending on the first
stage circuit.
• An effect due to noise may be easily produced as compared
with proper termination (1) shown on the above “1. Terminate
unused pins”.
[2] Do not connect to VCC or VSS directly.
<Reason>
If the direction register setup changes for the output mode
because of a program runaway or noise, a short circuit may
occur.
[3] Do not connect multiple ports in a lump to VCC or VSS
through a resistor.
<Reason>
If the direction register setup changes for the output mode
because of a program runaway or noise, a short circuit may occur
between ports.
7549 Group
Notes on Interrupts
Notes on Timers
1. Change of relevant register settings
1. Change of relevant register settings
When not requiring for the interrupt occurrence synchronous
with the following case, take the sequence shown in Figure 5.
• When switching external interrupt active edge
• When switching interrupt sources of an interrupt vector
address where two or more interrupt sources are allocated
1. Division Ratio of Timers 1, 2, and A
When n (0 to 255) is written to a timer latch, the frequency
division ratio is 1/(n+1).
Set the corresponding interrupt enable bit to
“0” (disabled).
Set the interrupt edge selection bit active edge
switch bit, or the interrupt source selection bit.
NOP (One or more instructions)
Set the corresponding interrupt request bit to “0”
(no interrupt request).
Set the corresponding interrupt enable bit to “1”
(enabled).
Fig 89. Sequence of changing relevant register
<Reason>
When setting the followings, the interrupt request bit of the
corresponding interrupt may be set to “1”.
• When switching external interrupt active edge
INT0 interrupt edge selection bit
(bit 0 of Interrupt edge selection register (address 003A16))
INT1 interrupt edge selection bit
(bit 1 of Interrupt edge selection register)
Capture 0 interrupt edge selection bit
(bits 1 and 0 of capture mode register (address 3216))
Capture 1 interrupt edge selection bit
(bits 3 and 2 of capture mode register)
2. Check of interrupt request bit
When executing the BBC or BBS instruction to determine an
interrupt request bit immediately after this bit is set to “0”, take
the following sequence.
<Reason>
If the BBC or BBS instruction is executed immediately after an
interrupt request bit is cleared to “0”, the value of the interrupt
request bit before being cleared to “0” is read.
Set the interrupt request bit to “0” (no interrupt issued)
NOP (one or more instructions)
Execute the BBC or BBS instruction
Fig 90. Sequence of check of interrupt request bit
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 77 of 81
2. Switching Count Source of Timers 1, 2, and A
When a count source of timer 1, timer 2 or timer A is switched,
stop a count of the timer.
3. Reading from and Writing to Timers 1, 2, and
Prescaler 12
If the timer/prescaler count source clock and φSOURCE are
different clocks, the timers and prescaler cannot be read or
written. Select the same clock to enable read and write
operations.
Note that timer 2 can be read and written even using a
different clock while its counting is stopped.
1Prescaler 12 and timer 1 cannot be read/written in the
following conditions:
Prescaler 12 count source: XCIN input clock
φSOURCE: Clock other than XCIN input clock
2Timer 2 cannot be read/written during counting in the
following conditions:
Timer 2 count source: Prescaler 12
Prescaler 12 count source: XCIN input clock
φSOURCE: Clock other than XCIN input clock
or
Timer 2 count source: Timer A underflow
Timer A count source: XCIN input clock
φSOURCE: Clock other than XCIN input clock
or
Timer 2 count source: Timer A underflow
Timer A count source: low-speed on-chip oscillator output
φSOURCE: Clock other than low-speed on-chip oscillator
4. Count Source of Prescaler 12
The X CIN input clock can be selected as the prescaler count
source only if the 32 kHz quartz crystal oscillator is selected by
the oscillation method selection bit in FSROM1.
5. Timer Value Setting
When the timer A write control bit is set to “write to only latch”,
written data is written to only to the latch even when the timer is
stopped. To set the initial setting value when the timer is stopped,
select “Write to timer and latch simultaneously” beforehand.
7549 Group
6. Reading from and Writing to Timer A
If the timer A count source clock and φSOURCE are different
clocks, timer A cannot be read or written during its counting.
Select the same clock or set timer A to stop counting to enable
read and write operations.
•Timer A cannot be read/written in the following
conditions:
Timer A count source: XCIN input clock
φSOURCE: Clock other than XCIN input clock
or
Timer A count source: Low-speed on-chip oscillator output
φSOURCE: Clock other than low-speed on-chip oscillator
7. Count Source of Timer A
The XCIN input clock can be selected as the count source of timer
A only if the 32 kHz quartz crystal oscillator is selected by the
oscillation method selection bit in FSROM1.
Notes on Output Compare
(1) If timer A is stopped, when a value is written to the
capture/compare register it is immediately transferred to the
compare latch. In addition, if timer A is stopped and the
compare x trigger enable bit is set to “1”, the output latch is
initialized.
(2) Do not write the same data to both of compare latch x0 and
x1.
(3) When setting value of the compare latch is larger than timer
setting value, compare match signal is not generated.
Accordingly, the output waveform is fixed to “L” or “H”
level.
However, when setting value of another compare latch is
smaller than timer setting value, this compare match signal
is generated. Accordingly, compare interrupt occurs.
(4) When the compare x trigger enable bit is cleared to “0”
(disabled), the match trigger to the waveform output circuit
is disabled, and the output waveform can be fixed to “L” or
“H” level.
However, in this case, the compare match signal is
generated.
Accordingly, compare interrupt occurs.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 78 of 81
Notes on Input Capture
(1) When the low-speed on-chip oscillator output or XCIN input
clock is selected as the count source of timer A, input
capture can be used only if the same clock source is selected
as φSOURCE and as the count source of timer A.
(2) When writing “1” to capture y software trigger bit of capture
latch 00 and 01 at the same time, or external trigger and
software trigger occur simultaneously, if capture latches 00
and 01 are input simultaneously, the set value of capture 0
status bit is undefined.
(3) When setting the interrupt active edge selection bit and
noise filter clock selection bit of capture 0 the interrupt
request bit may be set to “1”.
When not requiring the interrupt occurrence synchronized
with these setting, take the following sequence.
1Set the capture interrupt enable bit to “0” (disabled).
2Set the interrupt edge selection bit or noise filter clock
selection bit.
3Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
4Set the capture interrupt enable bit to “1” (enabled).
(4) When the capture interrupt is used as the interrupt for return
from stop mode, set the capture 0 noise filter clock selection
bits to “00 (Filter stop)”.
7549 Group
Notes on Serial I/O
Notes on A/D conversion
1. Serial I/O interrupt
When setting the transmit enable bit to “1”, the serial I/O
transmit interrupt request bit is automatically set to “1”. When
not requiring the interrupt occurrence synchronized with the
transmission enabled, take the following sequence.
1. Set the serial I/O transmit interrupt enable bit to “0” (disabled).
2. Set the transmit enable bit to “1”.
3. Set the serial I/O transmit interrupt request bit to “0” after 1
or more instructions have been executed.
4. Set the serial I/O transmit interrupt enable bit to “1”
(enabled).
1. Analog input pin
Make the signal source impedance for analog input low, or equip
an analog input pin with an external capacitor of 0.01µF to 1µF.
Further, be sure to verify the operation of application products on
the user side.
<Reason>
An analog input pin includes the capacitor for analog voltage
comparison.
Accordingly, when signals from signal source with high
impedance are input to an analog input pin, charge and discharge
noise generates. This may cause the A/D conversion/comparison
precision to be worse.
2. I/O pin function when serial I/O is enabled.
The functions of P06 and P07 are switched with the setting values
of a serial I/O mode selection bit and a serial I/O synchronous
clock selection bit as follows.
2. Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of
the capacity will be lost if the clock frequency is too low. This
may cause the A/D conversion precision to be worse.
Accordingly, set f(XIN) in order that the A/D conversion clock is
250 kHz or over during A/D conversion.
(1) Serial I/O mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
• Setup of a serial I/O synchronous clock selection bit
“0” : P0 6 pin turns into an output pin of a synchronous
clock.
• “1” : P06 pin turns into an input pin of a synchronous
clock.
Setup of a SRDY output enable bit (SRDY)
“0” : P07 pin can be used as a normal I/O pin.
“1” : P07 pin turns into a SRDY output pin.
(2) Serial I/O mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
• Setup of a serial I/O synchronous clock selection bit
“0” : P06 pin can be used as a normal I/O pin.
“1” : P06 pin turns into an input pin of an external clock.
• When clock asynchronous (UART) type serial I/O is
selected, it is P07 pin. It can be used as a normal I/O pin.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 79 of 81
3. Read A/D conversion register
• 8-bit read
Read only the A/D conversion low-order register (address 3516).
• 10-bit read
Read the A/D conversion high-order register (address 3616) first,
and then, read the A/D conversion low-order register (address
3516).
In this case, the high-order 6 bits of address 3616 returns “0”
when read.
4. A/D translation accuracy
As for A/D translation accuracy, on the following operating
conditions, accuracy may become low.
(1) When VCC voltage is lower than [3.0 V], the accuracy at the
low temperature may become extremely low compared with
that at room temperature. When the system would be used at
low temperature, the use at V CC = 3.0 V or more is
recommended.
(2) When XCIN or the low-speed on-chip oscillator is selected
as φSOURCE, the A/D converter cannot be used.
7549 Group
Notes on Watchdog Timer
1. Watchdog Timer Underflow
The watchdog timer operates in wait mode. To prevent
underflow, write to the watchdog timer control register.
The watchdog timer stops in stop mode, but starts counting at the
same time as exiting stop mode. After exiting stop mode, it
continues counting during oscillation stabilization time. To
prevent underflow during the period, the watchdog timer H count
source selection bit (bit 7) in the watchdog timer control register
(address 003916) should be set to “0” before executing the STP
instruction.
Note that the watchdog timer continues counting even if the STP
instruction is executed in the following two conditions:
1 Stopping the low-speed on-chip oscillator: Disabled (bit 4 in
FSROM2)
Source clock of the watchdog timer: Low-speed on-chip
oscillator/16 (bit 0 in FSROM2)
2 Stopping the low-speed on-chip oscillator: Disabled (bit 4 in
FSROM2)
Source clock of the watchdog timer: φSOURCE (bit 0 in
FSROM2)
φSOURCE: Low-speed on-chip oscillator (bits 5 and 4 in
CLKM)
2. STP instruction function selection bit
The function of the STP instruction can be selected by the bit 2 in
FSROM2. This bit cannot be used for rewriting by executing the
STP instruction.
• When this bit is set to “0”, stop mode is entered by executing
the STP instruction.
• When this bit is set to “1”, internal reset occurs by executing
the STP instruction.
Notes on RESET pin
1. Connecting capacitor
In case where the RESET signal rise time is long, connect a
ceramic capacitor or others across the RESET pin and VSS pin.
And use a 1000 pF or more capacitor for high frequency use.
When connecting the capacitor, note the following:
• Make the length of the wiring which is connected to a
capacitor as short as possible.
• Be sure to verify the operation of application products on the
user side.
<Reason>
If the several nanosecond or several ten nanosecond impulse
noise enters the RESET pin, it may cause a microcomputer
failure.
Note on Generating Clock Circuit
1. Switching to XIN/XCIN Oscillator
After a reset is cleared, operation starts using the low-speed onchip oscillator. When switching to XIN/XCIN oscillator, make
sure to set a sufficient wait duration with the on-chip oscillator to
allow the XIN/XCIN oscillator to stabilize.
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 80 of 81
Note on Oscillation Control
For use with the oscillation stabilization set bit after release of
the STP instruction set to “1”, set values in timer 1 and prescaler
12 after fully appreciating the oscillation stabilization time of the
oscillator to be used.
Notes on Oscillation Stop Detection Circuit
(1) Do not execute the transition to “state 2’a” shown in Figure
68 State transition of oscillation stop detection circuit. In
this state, no reset is triggered and the MCU is stopped even
when the XIN oscillation stops.
(2) After an oscillation stop detection reset, if this reset is
enabled while bits XIN oscillation stop detection function
active and oscillation stop detection status are retained, a
reset is triggered again.
(3) The oscillation stop detection status bit is initialized under
the following conditions:
• External reset, power-on reset, low-voltage detection reset,
watchdog timer reset, and reset by the STP instruction
function.
• Write 0 to the XIN oscillation stop detection function active
bit
(4) While the oscillation stop detection function is in active, the
oscillation stop detection status bit may set to 1 when the
watchdog timer underflows or by a reset when the STP
instruction is executed with the STP instruction function
selection bit set to 1.
When an oscillation stop detection reset is triggered,
reconfirm that oscillation is stopped.
(5) The oscillation stop detection circuit is not included in the
emulator MCU “M37549RLSS”.
Note on Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and
may perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the supply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
Note on Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor
suitable for high frequencies as bypass capacitor between power
source pin (V CC pin) and GND pin (V SS pin). A ceramic
capacitor of 0.01 µF to 0.1 µF is recommended.
Connect a capacitor across the power source pin and GND pin
with the shortest possible wiring.
7549 Group
Note on Memory
(1) Because the contents of RAM are indefinite at reset, set
initial values before using.
(2) Do not access to the reserved area.
(3) Random data is written into the Renesas shipment test area
and the reserved ROM area. Do not rewrite the data in these
areas. Data of these area may be changed without notice.
Accordingly, do not include these areas into programs such
as checksum of all ROM areas.
(4) The QzROM values in function set ROM data 0 to 2 set the
operating modes of the various peripheral functions after an
MCU reset is released. Do not fail to set the value for the
selected function. Bits designated with a fixed value of 1 or
0 must be set to the designated value.
Notes on QzROM
1. Note on Product shipped in blank
As for the product shipped in blank, Renesas does not perform
the writing test to user ROM area after the assembly process
though the QzROM writing test is performed enough before the
assembly process. Therefore, a writing error of approx.0.1 %
may occur.
Moreover, please note the contact of cables and foreign bodies
on a socket, etc. because a writing environment may cause some
writing errors.
2. Overvoltage
Take care not to apply the voltage above the Vcc pin voltage to
other pins. Make sure that the voltage of the CNVSS pin (VPP
power input pin for QzROM) does not change as shown in the
bold-lined periods (Figure 91) when powering on and off. If the
voltage changes as shown, the QzROM contents may be
rewritten.
~
~
(1)
(2)
1.8 V
1.8 V
VCC pin voltage
~
~
CNVSS pin voltage
(1) The input voltage to other MCU pins rises before the V CC pin
voltage rises.
(2) The input voltage to other MCU pins falls before the V CC pin
voltage falls.
Note: If VCC falls below the minimum value 1.8 V (shaded areas),
the internal circuit becomes unstable. Take additional care
to prevent overvoltage.
Fig 91. Timing Diagram (bold-lined periods are applicable)
3. QzROM Writing Orders
When ordering the QzROM product shipped after writing,
submit the mask file (extension: .mask) which is made by the
mask file converter MM.
• Be sure to set the ROM option data* setup when making the
mask file by using the mask file converter MM.. The ROM
code protect is specified according to the ROM option data* in
the mask file which is submitted at ordering. Note that the
mask file which has nothing at the ROM option data* or has
the data other than “0016” and “FF16” can not be accepted.
• Set “FF16” to the ROM code protect address in ROM data
regardless of the presence or absence of a protect. When data
other than “FF16” is set, we may ask that the ROM data be
submitted again.
* ROM option data: mask option noted in MM
Rev.2.02 Mar 31, 2009
REJ03B0202-0202
Page 81 of 81
4. Data Required for QzROM Writing Orders
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
2. Mark Specification Form*
3. ROM data...........Mask file
* For the QzROM writing confirmation form and the mark
specification form, refer to the “Renesas Technology Corp.”
Homepage (http://www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
REVISION HISTORY
7549 Group Datasheet
Rev.
Date
Description
1.00
Dec 15, 2006
-
First edition issued
2.00
Feb 19, 2007
1
FEATURES: “• LED output port” → “• LED direct drive port”
“• Built-in high-speed on-chip oscillator” → “High-speed on-chip oscillator”
“• Built-in low-speed on-chip oscillator” → “Low-speed on-chip oscillator”
•Power dissipation: “TBD” → “30 mW”
4
Table 1: I/O port P00-P07; “LED direct drive ports” is added
A/D converter; “8 channel” → “× 8 channel”
6
Table 2: P03 “Capture function pin” → “Capture input pin”
P10-P12 “Compare function pin” → “Compare output pin”
P13 “Timer 2 function pin” → “Timer 2 output pin”
P20, P21 “external oscillator pin” → “clock pins”
Page
Summary
10
[CPU mode register]: Description is revised and moved from the page 12.
11
Function set ROM Area: Description is revised and moved from the page 47.
<Notes>: (2) is added, (3) is revised
12
Fig 8 Note is deleted
14
Fig 10, Fig 11, Fig 12 is moved from the page 47.
Fig 12 is revised
15
[Pull-up control registers]: Description revised
Fig 13, Fig 14, Fig 15 is revised
16
Table 6 is revised
17, 18
Fig 16, Fig 17; Title is revised
19
Contents of Table 7 is added
21
Table 8: Key-on wakeup “P0” → “P1”
24
Timers, • Notes on Timers 1 and 2: Description is revised
26
Timer A (TA), • Notes on Timer A: Description is revised
27
Output compare: Contents of description added
Fig 29 “oscillator/512” → “oscillator/16”
31
Input capture: Contents of description added
32
Fig 39 “oscillator/512” → “oscillator/16”
37, 38
register name: “A/D” → “AD”
38
• Notes on A/D converter: (2) is added
39
Watchdog Timer is revised
Fig 50, Fig 53 is revised
40
• Notes on Watchdog Timer is revised
42
Fig 56 is revised
43
Clock Circuit is revised
44
Oscillation Control is added
Table 9 is added
Fig 61 is revised
47
Fig 62 is revised
48
Fig 63 is revised
49
“oscillation stop” → “oscillation stop detection”
Fig 64 is revised
Fig 65 is revised, Note 4 is added
• Notes on Function Set ROM Data 2 is deleted
50
Table 10: P10 “ESDA input” → “ESDA I/O”, “Output” → “I/O”
A-1
REVISION HISTORY
Rev.
Date
2.00
Feb 19, 2007
7549 Group Datasheet
Description
Page
2.01
Oct 15, 2007
Summary
53
(7) CPU Mode Register is revised
58
Overvoltage: Description revised, Fig 79 is added
59
ELECTRICAL CHARACTERISTICS is added
1
Interrupts. “13 sources, 13 vectors”→“12 sources, 12 vectors”
4
Interrupts. “13 sources, 13 vectors”→“12 sources, 12 vectors”
Power dissipation “TBD”→“30 mW”
10
“Stack page bit”→“Stack page selection bit”
14
Fig 12 is revised.
17
Fig 16 (6) and (8) are revised.
19
Table 7 RESET is added.
20-24
Interrupts is revised. Fig 20-22 are added.
26
Fig 24 is revised.
30
Fig 32 is revised.
42
Fig 53 is revised.
43
Fig 55 is revised.
52
Oscillation stop detection circuit is revised.
54
VCC, VSS “Apply 1.8 to 5.5 V to VCC”→“Apply 2.7 to 5.5 V to VCC”
57
(7) CPU Mode Register is revised.
59
3. Writing to analog input pins is revised.
65
Table 14 “RHSOSC”→“RHSOSO”
Min.: “TBD”→“3.8”, “3.6”, Max.: “TBD”→“4.2”, “4.4”
“RLSOSC”→“RLSOSO”
67
Table 16 Absolute accuracy Max.: “TBD”→“3”
Table 17 A/D Conversion clock frequency Min.: “TBD”→“0.016”
74
APPENDIX is added.
All pages “PRELIMINARY” deleted.
2.02
Mar 31, 2009
4
57, 74
Table 1 Power dissipation: 30 mW → 30 mW (Typ.)
“Processor Status Register” revised.
63
Table 12 VCC: XIN oscillation, XCIN oscillation, .... → XCIN oscillation deleted.
65
Table 14 NOTE 3 P05/TXD1 → P05/TXD
68
- Power-on reset circuit characteristics:
TW(VPOR) Limits Max. and Min. values changed.
- Low voltage detection circuit characteristics:
TW(VLVD) and TW (VLVD -VDET) eliminated.
VDET- → VDET, V(VDET+- VDET-) deleted.
- Fig. 83 revised.
61, 81
“Notes On QzROM Writing Orders” revised.
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