SC4624MLTRT

SC4624
Low Input Voltage, High Efficiency, 4A Integrated
FET Synchronous Step down DC/DC Regulator
POWER MANAGEMENT
Description
Features
u VIN Range: 2.3 – 5.5V
u 4A Continuous Output Current
u Adjustable Output Voltage 0.5V to Vin
u Low RDS(ON) integrated FETs: 74mΩ and 47mΩ
u Up to 95% Efficiency
u Synchronizable and Programmable Frequency:
200kHz – 2MHz
u Power Good Monitor
u <1.5µA of Shutdown Current
u Programmable Soft Start
u Programmable Current Limit
u Over Temperature protection
u Starts into pre-biased output
u 4x4mm MLPQ-20 and SOIC-16EDP packagesWEEE and RoHS Compliant
The SC4624 is a highly integrated synchronous step-down
DC/DC regulator designed for low input voltage range of
2.3V to 5.5 Volts. It can deliver 4A continuous output
current with the output voltage as low as 0.5 Volts. The
internal low RDS(ON) synchronous power switches eliminate
the need for external Schottky diode while delivering
overall converter efficiency up to 95%.
A power good pin is available to monitor the output voltage
status. Operating frequency is adjustable from 200 kHz
to 2MHz with a single resistor and it can be synchronized
to an external clock.
The SC4624 offers adjustable current limit, soft start and
over temperature protection to safeguard the device under
extreme operating conditions. The soft start provides a
controlled output voltage ramp up at startup. When a
logic low is applied to the Enable pin, the SC4624 enters
the shutdown mode and it consumes less than 1.5µA of
current.
Applications
 Low Voltage Distributed DC-DC Converters
 Telecommunication Power Supplies
 Portable Equipment
 xDSL
The SC4624 is available in 4x4 MLPQ-20 and SOIC-16EDP
packages.
Typical Application Circuit
R4
C11
Vin
R5
PH
SYNC/EN
R6
C9
VCC
R1
SC4624
SS
ISET
FS
C4
R9
C1
C2
COMP
PGND
AGND
C5 R3 R11
R8
FB
C3
C7
C8
R7
PGOOD
R2
Revision: August 27, 2010
Vout
L1
PVIN
1
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SC4624
POWER MANAGEMENT
Pin Configuration
5
4
3
2
Ordering Information
1
20
1
PVIN1
16
15
ISET
SS
C
VCC
5
SYNC/EN
Package
SC4624MLTRT (1) (2)
SC
4624
MLPQ-20
SC4624SETRT (1) (2)
SC4624
SO-16 EDP
SC4624EVB-SO
Notes:
(1) Available in tape and reel only. A reel contains 3,000 devices for MLPQ-20
package and 2,500 devices for SO-16 package.
(2) Available in lead-free package only. Device is WEEE and RoHS compliant.
FB
11
10
Evaluation Board
C
AGND
VCC
6
Top Mark
SC4624EVB-MLPQ
PGND1
T
FS
Device
D
PH1
PH2
PH3
D
PGND2
PVIN2
Top View
NC
NC
PGOOD
COMP
B
NC
B
20Pin MLPQ
θJA= 29°C/W; θJC= 2.5°C/W.
A
5
4
5
3
2
Top View
4
A
3
1
2
1
D
D
SYNC/EN
1
16
AGND
PGND2
3
14
FB
PGND1
C
PH1
4
PH2
5
PVIN1
T
6
PVIN2
B
15
2
13
12
PGOOD
VCC
10
8
C
COMP
11
7
ISET
VCC
FS
9
B
SS
16Pin SOIC-EDP
θJA= 31°C/W; θJC= 3.9°C/W.
A
5
4
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A
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SC4624
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the
Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
Supply Voltage
PVIN, VCC
-0.3 to 6
V
+/- 0.3
V
-0.3 to VCC+ 0.3
V
+/- 0.3
V
PVIN to VCC
FB, COMP, ISET, SYNC/EN, FS, SS, PGOOD to AGND
PGND to AGND
PHASE Voltage to PGND
VPHASE
-0.3 to PVIN+ 0.3
V
PHASE Pulse Voltage to PGND Tpulse < 50ns
VPHASE
-3 to PVIN+ 2
V
TSTG
-65 to 150
°C
TJ
150
°C
-40 to 125
°C
TP
260
°C
Lead Temperature (Soldering) 10 sec for SO Package Only
TLEAD
300
°C
ESD Protection Level(1)
VESD
2
kV
Storage Temperature Range
Junction Temperature
Junction Temperature (Operating)
IR Reflow Temperature
Note:
1) Tested in accordance to JEDEC standard JESD22-A114B.
Recommended Operating Conditions
The Performance is not guarantied if exceeding the specifications below.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Power Supply
Input Voltage Operating Range
Max. Output Current
VIN
2.3
5.5
V
IOUTMAX
0
4
A
Electrical Characteristics
Unless otherwise specified, VIN= VCC=SYNC/EN=3.3V, ROSC=51.1KΩ, RISET=27.4KΩ, TJ = -40°C to 125°C
Parameter
Symbol
Conditions
VIUV
VIN Rising
Min
Typ
Units
Power Supply
Start Threshold Voltage, UVLO
Hysteresis Voltage, UVLO
VIUVHY
Supply Current, Shutdown
ISD
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2
2.25
120
VSYNC = 0V
3
0.2
V
mV
1.5
µA
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SC4624
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless otherwise specified, VIN= VCC=SYNC/EN=3.3V, ROSC=51.1KΩ, RISET=27.4KΩ, TJ = -40°C to 125°C.
Parameter
Symbol
Conditions
IQswitching
Min
Typ
Max
Units
FB = COMP, No Load
7
10
mA
IQL
FB = 0.6V, No Load
3.5
7
mA
TOTP
Temperature Rising
160
°C
10
°C
Power Supply (Cont.)
Supply Current, Operating
Thermal Shutdown
Thermal Shutdown Trip Point
Thermal Shutdown Hysteresis
TOTP_HYS
Synchronization, Enable Input
SYNC/EN Threshold
Frequency Range, SYNC
VENL
Logic Low
0.8
V
VENH
Logic High
2.0
FSYNC
20% Higher than FOSC
200
2000
kHz
200
2000
kHz
V
Oscillator
Osciilator Frequency Range
FOSC
Osciilator Frequency Accuracy
ROSC= 51.1KΩ
415
500
600
kHz
ROSC=51.1KΩ, TA=TJ=25°C
435
500
565
kHz
Ramp Peak to Valley(1)
VPV
1.0
V
Ramp Peak Voltage(1)
VP
1.25
V
Ramp Valley Voltage(1)
VV
0.25
V
ISS
4
µA
Soft Start, Current Limit
Soft-Start Charge Current
ISET Bias Voltage
VISET
RISET = 27.4KΩ
0.45
0.55
0.62
V
Over Current Trip
IIST
RISIT = 57.6KΩ
1.9
2.55
3.1
A
Output UVLO
VOUV
VFB drop
Hiccup period(1)
TOCHP
0.3
V
131072
clks
Error Amplifier Open Loop
Voltage Gain (1)
100
dB
Error Amplifier Unity Gain Bandwidth(1)
10
MHz
Output Voltage Slew Rate, COMP(1)
4
V/µs
Error Amplifier
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SC4624
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless otherwise specified, VIN= VCC=SYNC/EN=3.3V, ROSC=51.1KΩ, RISET=27.4KΩ, TJ = -40°C to 125°C.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Error Amplifier (Cont.)
Source Output Current, COMP
FB = 0.4V
20
mA
Sink Output Current, COMP
FB = 0.6V
25
mA
Output Voltage High, COMP
FB = 0.4V, ICOMP = -1mA
2.5
V
Output Voltage Low, COMP
FB = 0.6V, ICOMP = 1mA
0.1
0.25
V
0.4925
0.5
0.5075
V
-2
+1
+2
%
300
nA
Feedback Voltage
VFB
Input Bias Current(1)
IFB
FB=VREF
High-Side P-MOSFET
RDSH(on)
VIN=VCC=5V, ISOURCE = 1A, TA=TJ=25 °C
74
100
mΩ
Low Side N-MOSFET
RDSL(on)
VIN=VCC=5V, ISINK = 1A, TA=TJ=25 °C
47
85
mΩ
VPGL
IPGOOD = 1mA
0.2
IPGOOD
PGOOD = 5V
TD
Vout rising or Vout falling
Vcc = 2.3V to 5.5V
Power Switches
Power Good
PGood Voltage Low
PGood Leakage Current
PGood Delay Time(1)
PGood High Window
With respect to nominal output,
TA=TJ=25 °C
V
1
1024
+8
+10
µA
clks
+15
%
Note:
(1) Guaranteed by design.
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SC4624
POWER MANAGEMENT
Start up by Vin
Operation
Typical Performance
Characteristics
Start up by Vin
Test condition: 5Vin, 1Vo, Io=0A
Test condition: 5Vin, 1Vo, Io=0A
Circuit condition: Application circuit#1, 5VIN, 1VOUT
VIN
Vin
VIN
Vin
5V/DIV
SS
SS
SS
SS
5V/DIV
5V/DIV
5V/DIV
V
Vout
OUT
VVout
OUT
0.5V/DIV
0.5V/DIV
PGOOD
PGOOD
5V/DIV
PGOOD
PGOOD
5V/DIV
10ms/DIV
10ms/DIV
Figure 1. Start Up by VIN@0A
Shutdown by Vin
FigureShutdown
2. Start Up
by by
VinVIN@4A
Test condition: 5Vin, 1Vo, Io=4A
Test condition: 5Vin, 1Vo, Io=0A
5V/DIV
5V/DIV
VVin
IN
5V/DIV
VIN
Vin
5V/DIV
SS
SS
SS
SS
0.5V/DIV
0.5V/DIV
VVout
OUT
VOUT
5V/DIV
5V/DIV
Vout
PGOOD
PGOOD
PGOOD
PGOOD
5ms/DIV
1ms/DIV
response
Figure Transient
3. Shutdown
by VIN@0A
Figure 4.
Shutdown
by VIN@4A
Stability
and Ripple
Test condition: 5Vin, 1Vo, Io=0 to 4A
R=F=2.5A/us,T1=T2=0.1ms
Test condition: 5Vin, 1Vo, Io=4A,
(Operating stably)
Vout
Vout
V
20mV/DIV
OUT
VVout
OUT
50mV/DIV
Io
2.0V/DIV
lOUT
IOUT
2A/DIV
PHASE
1us/DIV
20us/DIV
Figure 5. Transient Response@ 0 to 4A
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Vphase
V
Figure 6. Ripple and Stability@4A
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SC4624
POWER MANAGEMENT
Over current
protection (Cont.)
Operation
Typical Performance
Characteristics
Thermal protection
Test condition: 5Vin, 1Vout
Test condition: 5Vin,
1Vout
Circuit condition: Application
circuit#1,
5VIN, 1VOUT
0.6V/DIV
0.6V/DIV
VVout
OUT
5.0V/DIV
SS
SS
V
Vout
OUT
5.0V/DIV
SS
SS
3.0V/DIV
3V/DIV
V
Vphase
PHASE
VVphase
PHASE
100ms/DIV
1s/DIV
Figure 7. Over Load Hiccup
Figure 8. Thermal Shutdown Protection@0A
SYNC
Efficiency
External clock singal=650kHz, duty=50%
100
95
Sync
Signal
90
SYNC
2.0V/DIV
5Vin
80
Efficiency(%)
Efficiency(%)
85
75
2.5Vin
70
3.3Vin
65
60
55
50
VPHASE
Vphase
2.0V/DIV
45
40
1us/DIV
0.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Output
Current(A)
Output Current(A)
Figure 10. Efficiency(VIN)
Figure 9. Synchronization
130
0.5
Internal PMOS RDSON @ Room Temperature
80
120
Internal NMOS RDSON @ Room Temperature
75
.5VIN
70
.5VIN
RDSON (mΩ)
RDSON (mΩ)
110
100
90
.3VIN
65
60
.3VIN
80
55
VIN
VIN
70
1
2
IOUT (A)
3
50
4
1
IOUT (A)
3
4
Figure 12. Low-Side N-MOSFET
Figure 11. High-Side P-MOSFET
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SC4624
POWER MANAGEMENT
Operation
Typical Performance Characteristics (Cont.)
Regulation During Switching to Linear Mode
3.3Vin
4.4
2.52
4.0
2.50
5Vin
VOUT
2.48
3.6
3.2
2.46
IO(A)
IOUT (A)
VOUT (V)
CISET=100nF,
C9
OCP Trip
4.8
2.54
2.44
2.42
2.5Vin
2.8
2.4
2.0
2.40
1.6
2.38
1.2
2.36
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.8
20
IOUT (A)
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
RISET (KΩ)
RISET(Kohm)
Figure 13. Loading Regulation
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Figure 14. Over Current Setting versus RISET
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SC4624
POWER MANAGEMENT
Pin Descriptions
Pin
Pin
Pin Name
SO-16 MLPQ-20
Pin Functions
6
1
PVIN1
8
2
ISET
Current limit setting pin. A resistor connected between ISET and AGND sets the over
current protection threshold. A ceramic decoupling between ISET pin to AGND have to
be reserved to prevent from noise influence.
9
3
SS
Soft start time setting pin. A cap connected from this pin to GND sets the soft start up
time.
10
4
FS
Oscillator frequency setting pin. An external resistor connected from this pin to GND
sets the oscillator frequency.
11,15
5,12
VCC
12
6
PGOOD
7,8,9
NC
13
10
COMP
This is the output of the error amplifier. The voltage at this point is connected to the
inverting input of the PWM comparator. A compensation network is required in order to
optimize the dynamic performance of the voltage mode control loop.
14
11
FB
The inverting input of the error amplifier. It serves as the output voltage feedback point
for the buck controller. It senses the output voltage through an external divider.
16
13
AGND
1
14
2
15
PGND1
Power ground.
3
16
PGND2
Power ground.
4
17
PH1
Switching nodes
5
18
PH2
Switching nodes
19
PH3
Switching nodes
20
PVIN2
7
Power supply voltage for high side MOSFETs.
Power supply voltage for the analog section of the controller.
Power good indicator. It is an open drain output. Low when the output is below the
power good threshold level.
No connection.
Analog signal gound.
The oscillator frequency of the SC4624 is set by FS when SYNC/EN is pulled and
SYNC/EN held above 2V. Its synchronous mode is activated as SYNC/EN is driven by an external clock. Its shutdown mode is invoked if SYNC/EN is pulled and held below 0.8V.
Power supply voltage for high side MOSFETs.
THERMAL Pad for heatsinking purposes only. Connect to ground plane using multiple vias. Not
PAD
electrically connected internally.
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SC4624
POWER MANAGEMENT
Block Diagram
ASYNCHRONOUS
START UP
VCC
PVIN1
0.5V
THERMAL
SHUTDOWN
PVIN2
-
BANDGAP
TOP GATE
UVLO
BANDGAP
HIGH SIDE DRIVER
AND LOGIC
ISET
CONTROL
AND
HICCUP
VREF
ERROR
OPAMP
SOFT
START
I = F(R_ISET)
PH1
OVER
CURRENT
PROTECT
PH2
-
AGND
PH3
SS
BOTTOM
GATE
PWM
BLOCK
FB
COMP
PWM
LOGIC
SD
SYNC/EN
SHOOTTHRU
PROTECTION
OSC
FB
FS
CLOCK
LOW SIDE DRIVER
AND LOGIC
PGND1
PGND2
0.9VREF
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PGOOD
DELAY
1.1VREF
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SC4624
POWER MANAGEMENT
Application Information
Overview
The SC4624 is a programmable high switching frequency,
integrated 4A MOSFET, synchronous step down regulator.
This reduces external component count and makes it
effective for applications which are low in cost and sized
small. A non-overlap protection is provided for the gate
drive signals to prevent shoot through of the internal
MOSFET pair.
During start up or restart, A typical 4µA sourcing current
charges the capacitor and then the voltage of capacitor
ramp up the error amp reference slowly. The closed
loop creates narrow width driver pulses while the output
voltage is low and allows these pulses to increase to their
steady state duty cycle as the output voltage reaches
its regulated value. The duration of the soft start in the
SC4624 is controlled by an external capacitor.
The SC4624 is capable of producing an output voltage as
low as 0.5V and Its operation frequency is programmable
up to 2MHz by an external resistor. It features lossless
current sensing of the voltage drop across the internal
drain to source resistance of the high side MOSFET during
its conduction period.
The SC4624 starts up in asynchronous mode before SS
voltage reaches to 0.5V, and the bottom FET diode is used
for circulating current during the top FET off time. Ths SS
voltage level is clamped at VCC finally.
Pre-biased Output
The SC4624 is able to start into pre-biased output by
adding external RC circuit, where R(10KΩ) is between VCC
pin and EN pin, C(0.1uF) is between EN pin and AGND.
If there is a pre-biased load on the output of SC4624
during start-up, the internal low-side MOSFET of SC4624
is always disabled before SS reach to 0.5V, the output
voltage is maintained. The great feature avoids negative
voltage spikes or short circuit on the output, which could
cause damage to the down-stream IC during start-up.
The quiescent supply current in shutdown mode is
typically lower than 1µA. An external soft start is provided
to prevent output voltage overshoot during start-up. Over
Temperature Protection, Power Good Indicator, External
Clock Synchronization are some of the internal added
features.
Enable
The SC4624 is enabled by applying a voltage greater than
2V (typical) to the VCC and SYNC/EN pin. The voltage on
the VCC pin determines the operation of the SC4624. As
VCC increases during start up, the UVLO block senses VCC
and keeps the high side and low side MOSFETs off and
the internal soft start voltage low until VCC reaches 2V. If
no faults are present, the SC4624 will initiate a soft start
when VCC exceeds 2V. A typical 120mV hysteresis in the
UVLO comparator provides noise immunity during its start
up. (refer to Figure 1 to 2).
Timing between VCC and EN is very important for pre-biased
output. VCC must lead EN. When VCC and EN voltage rise
at same time(tied together), the pre-biased output voltage
is pull low before VCC reach to the voltage of UVLO. If this
isn’t desirable, RC(10KΩ and 0.1uF) must be added at EN
to prevent this from happening.
Oscillator
The FS pin is used to set the PWM oscillator frequency
through an external resistor that is connected from the
FS pin to the AGND. The internal ramp is a triangle at the
PWM frequency with a peak voltage of 1.25V and a valley
voltage of 0.25V. The approximate operating frequency is
determined by the value of an external resistor as shown
in Figure 15.
Shutdown
The SC4624 is disabled when VCC falls below 1.88V (typical)
or shutdown mode operation is invoked by clamping the
SYNC/EN pin to a voltage below 0.8V. During the shutdown
mode, A typical 0.2µA current draw through the VCC pin,
the internal soft start voltage is held low and the internal
MOSFETs are turned off. (refer to Figure 3 to 4).
Soft Start
The soft start function is required for step down controllers
to prevent excess in-rush current through the DC bus
during start up. An external capacitor is necessary for
the soft start function and is connected from SS pin to
AGND.
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SC4624
POWER MANAGEMENT
Operation
Application Information (Cont.)
Thermal Shutdown
When the junction temperature rises up around 160°C,
the internal soft start voltage is held low, the internal high
side and low side MOSFETs are turned off and the output
voltage will fall to zero. Once the junction temperature
goes below hysteresis temperature around 10°C, the
regulator will restart. (refer to Figure 8).
Switching Frequency Setting
145
135
125
115
105
RFS (KΩ)
95
85
75
65
5VIN
55
Linear Mode Operation (100% duty)
The SC4624 can allows 100% duty cycle operation. The
Vout is,
45
35
25
2.5VIN
15
9287
5
200
400
600
800
1000
1200
1400
1600
1800
2000
FOSC (kHz)
where
RL : Output inductor DC resistance.
RDSH : Internal high side P-MOSFET resistance.
(refer to Figure11).
Figure 15. Switching Frequency vs. RFS
The operation frequency can be programmed up to 2MHz,
but there is a minimum on-time limitation which is around
110ns. Users should take care of minimum limitation
on the operating duty cycle under high frequency
application.
As Vin drops gradually and close to Vout, the buck regulator
will go into 100% duty cycle ratio. A matter needing
attention is internal high side PMOS has minimum off time
limitation and is related to duty cycle rate. This condition
makes the working duty cycle perform at randon with the
output ripple increasing and a poor transient response.
Above phenomenon can be improved by larger output
capacitor and smaller output inductor. Users need to
verify whether above application condition has opposite
influence on entire circuit.
Synchronization Frequency
Synchronization operation mode is invoked by using an
external clock signal and is activated when the SYNC/EN
is pulled and held above 2V and held below 0.8V. The
range of synchronization frequency is from 200kHz to
2MHz.
Over Current Protection
A over current setting is programmed by an external
resistor (RISET). It goes through internal sense resistor and
generates a voltage.
A jitter happens when sync pulse clock edge is less than
120ns before the phase switches. It is caused by the
ground bounce of synchronization pulse coupled to PWM
comparator. Users try to avoid this application. (refer to
Figure 9).
9
9FF , u 52QVHQVH
where
I : The current is generated by RISET , and it is amplified
by internal current amplifier.
RONSENSE : Internal sense resistor.
Power Good Indicator
The PGOOD pin is an open-drain and incorporated window
comparators output. It’s is necessary that a pull-up
resistor from the PGOOD pin to the input supply for setting
the logic high level of the PGOOD signal. When FB voltage
is within +10% setting output voltages typical, the output
of power good comparator becomes high impedance after
delay time. The PGOOD signal delay time is around 1024/
FOSC. In shutdown mode the power good output is actively
pulled low.
Output inductor current goes through internal high side
P-MOSFET and generate a voltage.
9
9,1 ,/ u 5'6+ 21
where
IL : Output inductor current.
RDSH(ON) : High side P-MOSFET conduction resistance.
For example, 1MHz switching frequency applications, the
PGOOD delay time is around 1ms.
 2010 Semtech Corp.
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SC4624
POWER MANAGEMENT
Application information (Cont.)
The inductor value can be determined according to its
operating point and the switching frequency as follows:
After the high side PMOS turn on around 30ns, the OCP
comparator will compare between V2 and V1. When the
converter detects an over current condition (V2 > V1) as
shown in Figure 16, the SC4624 proceeds into the cycle by
cycle protection mode (Point B to Point C), which responds
to minor over current cases and the output voltage is
monitored.
/
,3 3
6
20$;
', u ,20$;
After the required inductor value is selected, the proper
selection of the core material is based on the peak
inductor current and efficiency requirements. The core
must be able to handle the peak inductor current IPEAK
without saturation and produce low core loss during the
high frequency operation and is given as follows:
,3($.
,,20$; ,3 3
The power loss for the inductor includes its core loss and
copper loss. If possible, the winding resistance should be
minimized to reduce any copper loss of the inductor, (the
core loss can be found in the manufacturer’s datasheet).
The inductor’s copper loss can be estimated as follows:
B
3&223(5
0
,/506 u 5:,1',1*
where
ILRMS is the RMS current in the inductor.
C
Vo
This current can be calculated as follows:
D
Iout
0
Imax
,/506
Figure 16. Over Current Protection Characteristic
,20$; u u ',
Output Capacitor Selection
Basically there are two major factors to consider in selecting the type and quantity of the output capacitors. The
first one is the required ESR (Equivalent Series Resistance) which should be low enough to reduce the voltage
deviation from its nominal one during its load changes.
The second one is the required capacitance, which should
be high enough to hold up the output voltage. Before the
Inductor Selection
For a typical SC4624 application, the inductor selection
is mainly based on its value, saturation current and DC
resistance. The inductor should be able to handle the
peak current without saturating and its copper resistance
in the winding should be as low as possible to minimize its
resistive power loss.
 2010 Semtech Corp.
287
The peak to peak inductor current is:
A poor layout will make OCP trip point shift and is not
easily to calculate by RISET. This is because it is affected
by ground bounce, spiker voltage between Vin pin and PH
pin, and internal parameter tolerance. Users can refer to
Figure 14, it shows how to set maximum output current
by RISET.
0.6 * Vout
,1
where
fs = switching frequency.
DI = ratio of the peak to peak inductor current to the
maximum output load current.
For example, with a switching frequency application of
550kHz, the hiccup period is around 238ms. (refer to
Figure 7).
A
287
,1
If the over current and low output voltage (set at 60% of
nominal output voltage) occur at the same time, the SS
pin is pull low by an internal switch and the comp pin is
pulled low and the devices stops switching. Assume start
from FB = 0V, FB and SS voltage rise forward 0.5V. Once
SS voltage exceeds 0.4V, the hiccup comparator becomes
enabled. The hiccup period is around 217/FOSC. (Point C to
Point D).
Vout
9 u 9 9 9 u I u ', u ,
13
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SC4624
POWER MANAGEMENT
Operation
Application Information (Cont.)
network to meet the requirements for a specific application.
SC4624 regulates the inductor current to a new value during a load transient, the output capacitor delivers all the
additional current needed by the load.
The SC4624 has an internal error amplifier and requires
the compensation network to connect among the COMP
pin and FB pin, GND, and the output as shown in Figure
17. The compensation network includes C1, C2, R1, R7,
R8 and C8. R9 is used to program the output voltage according to:
The ESR and ESL of the output capacitor, the loop parasitic inductance between the output capacitor and the
load combined with inductor ripple current are all major
contributors to the output voltage ripple.
Input Capacitor Selection
The input capacitor selection is based on its ripple current level, required capacitance and voltage rating. This
capacitor must be able to provide the ripple current by the
switching actions. For the continuous conduction mode,
the RMS value of the input capacitor can be calculated
from:
,&,1 506
,20$; u
9287 u 9,1 9287
9IN,1
This current gives the capacitor’s power loss as follows:
3&,1
&,1
,20$; u
5
4
5
5
3
2
1
SC4624
C1
D
R1
C2
COMP
L1
C
PH
C8
R
C4
C
R7
R8
B
B
R9
A
A
5
Figure 17. Compensation Network
Provides 3 Poles and 2 Zeros
4
3
2
For voltage mode step down applications as shown in Figure 17, the power stage transfer function is:
' u '
I6 u '9
∆ , ,20$; u 5&,1 (65 where
D = VO/VI , duty ratio.
DVI = the given input voltage ripple.
where
R = load resistance
RC = C4’s ESR.
Loop Compensation Design
For a DC/DC converter, it is usually required that the converter has a loop gain of a high cross-over frequency for
fast load response, high DC and low frequency gain for low
steady state error, and enough phase margin for its operating stability. Often one can not have all these properties
at the same time. The purpose of the loop compensation
is to arrange the poles and zeros of the compensation
The compensation network will have these characteristics:
 2010 Semtech Corp.
D
FB
Vout
, &,1 506 u 5&,1(65
This capacitor’s RMS loss can be a significant part of the
total loss in the converter and reduces the overall converter efficiency. The input ripple voltage mainly depends on
the input capacitor’s ESR and its capacitance for a given
load, input voltage and output voltage. Assuming that the
input current of the converter is constant, the required
input capacitance for a given voltage ripple can be calculated by:
u 92
w
GCOMP (s) = I ⋅
s
14
s
s
1+
wZ1
wZ 2
⋅
s
s
1+
⋅1+
wP1
wP 2
1+
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1
SC4624
POWER MANAGEMENT
Operation
Application Information (Cont.)
The design guidelines for the SC4624 applications are as
follows:
where
ωI =
1
R 7 ⋅ (C1 + C 2 )
ω Z1 =
1
R1 ⋅ C2
ωZ2 =
1
( R 7 + R 8 ) ⋅ C8
ωP1 =
C1 + C 2
R 1 ⋅ C1 ⋅ C 2
ωP 2 =
1
R 8 ⋅ C9
1. Set the loop gain crossover corner frequency wC for
given switching corner frequency wS = 2pfs,
2. Place an integrator at the origin to increase DC and
low frequency gains.
3. Select wZ1 and wZ2 such that they are placed near wO
to damp the peaking and the loop gain has a -20dB/
dec rate to go across the 0dB line for obtaining a wide
bandwidth.
4. Cancel the zero from C4’s ESR by a compensator pole
wP1 (wP1 = wESR = 1/(RCC4)).
5. Place a high frequency compensator pole wP2 (wP2 =
pfs) to get the maximum attenuation of the switching ripple and high frequency noise with the adequate
phase lag at wC.
8
The compensated loop gain will be as given as show in
Figure 18.
After the compensation, the converter will have the
following loop gain:
s
1+
1
s
s
1
⋅ wI ⋅ VI 1 +
1+
RC ⋅ C4
wZ1
wZ 2
VM
⋅
⋅
⋅
T(s) = GPWM ⋅ GCOMP (s) ⋅ G VD (s) =
L
s
s
s
1 + s 1 + s2L1C
⋅1+
1+
R
wP1
wP 2
s
1+
1
s
s
1
⋅ wI ⋅ VI 1 +
1+
R
w
w
V
C ⋅ C4
Z1
Z2
⋅
⋅
⋅
(s) ⋅ G VD (s=) = M
L1
s
s
s
1 + s + s2L1C
⋅1+
1+
R
wP1
wP 2
where
GPWM = PWM gain.
VM = 1.0V, ramp peak to valley voltage of SC4624.
Figure 18. Asymptotic Diagrams
of Power Stage and Loop Gain
 2010 Semtech Corp.
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SC4624
POWER MANAGEMENT
Operation
Application Information (Cont.)
the big vias to the bottom layer during the re-flow process
.
Layout Guidelines
In order to achieve optimal thermal and noise immunity
for high frequency converters, special attention must be
paid to the PCB layout. The goal of layout optimization
is to minimize the high di/dt loops and reduce ground
bounce.
Output voltage setting, line regulation, stability , switching
frequency and OCP trip point shifted are affected by a
poor layout. The following guidelines should be used to
ensure proper functions of the converters.
1. Both Power ground (PGND) and signal ground (AGND)
are separated.
2. A ground plane is recommended to minimize noise
and copper losses, and maximize heat dissipation.
3. Start the PCB layout by placing the power components
first. Arrange the power circuit to achieve a clean
power flow route.
4. Minimize all high di/dt loops. These loops pass high
di/dt current. Make sure the trace width is wide
enough to reduce copper losses in this loop. Ground
bounce happen to magnetic flux changed and it is
proportional to a magnetic filed which goes through
high di/dt loops.
5. The input ceramic capacitor (CIN) should be close to
PVIN pins and PGND pins.
6. Both input ceramic capacitor gnd and output ceramic
capacitor gnd are at same port.
7. A RC snubber circuit between PVIN and PH pins is
helpful for stability operation. Be careful with power
derating of snubber circuit.
8. The VCC bypass capacitor should be placed next to the
VCC and AGND pins.
9. The OCP setting resistor (RISET) and filter capacitor
(CISET) should be placed next to the ISET and AGND
pins.
10. Feedback divider connects to output connector by
Kelvin connection and far away from the noise sources
such as switching node and switching components.
11. A multilayer chip beads between AGND and PGND
will reduce the ground bounce injected to the “quiet”
circuit. It’s helpful for stability operation.
12. A large copper area underneath the SC4624 IC is
necessary for heat sinking purpose. And multiple
layers of large copper area connected through vias
can be used for better thermal performance. The size
of the vias as the connection between multiple layers
should not be too large or solder may seep through
 2010 Semtech Corp.
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SC4624
POWER MANAGEMENT
Operation
Application Information (Cont.)
5
4
3
2
5VIN, 1VOUT, 4A, all ceramic capacitors ( application circuit#1 )
5Vin
R6
10k
R2
10R
C6
C3
1nF
1uF
U1
5
VCC
6
PGOOD
14
C1
R1
C
20k
2.2pF
7
C2
10
390pF
11
1Vout@4A
L1
1.8uH
C8
270pF
R8
2.32k
C4
22uF
13
FS
4
NC
SS
3
COMP
NC
9
ISET
2
FB
PVIN1
18
PH2
PVIN2
20
19
PH3
PGND1
15
NC
PGND2
47.5k
R11
C7
47nF
C5
opt
R3
30k
PH1
R9
R12
AGND
1
8
(2)
B
12
17
R7
28.7k
VCC
SYNC/EN
PAD
R5
10k
D
16
C9
22uF
SC4624
28.7k
MLB-160808-0600R-S2
C11
R4
opt
VIN=5V; Vout=1V/4A
(1) opt
Switching Frequency=550kHz
Note: (1,2) Option for stability
L1: TOKO D104C(919AS-1R8N)
R12: Multilayer chip inductors; MLB-160808-0600R-S2
Input(C9)/Output Capacitors(C4): Panasonic ECJ33YBOJ226M(22uF/6.3V)
A
Title
SC4624
Application
Size
Document Number
Custom
Date:
5
 2010 Semtech Corp.
4
3
17
Monday, June 25, 2007
2
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Sheet
SC4624
POWER MANAGEMENT
Operation
PCB Layout
Component Side (TOP)
 2010 Semtech Corp.
(TOP layer)
(Bottom layer)
(IN1 layer)
(IN2 layer)
18
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SC4624
POWER MANAGEMENT
Outline Drawing - MLPQ - 20
A
B
D
DIM
PIN 1
INDICATOR
(LASER MARK)
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
E
A2
A
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
.031 .035 .039
.000 .001 .002
- (.008) .007 .010 .012
.154 .157 .161
.100 .106 .110
.154 .157 .161
.100 .106 .110
.020 BSC
.012 .016 .020
20
.004
.004
0.80 0.90 1.00
0.00 0.02 0.05
- (0.20) 0.18 0.25 0.30
3.90 4.00 4.10
2.55 2.70 2.80
3.90 4.00 4.10
2.55 2.70 2.80
0.50 BSC
0.30 0.40 0.50
20
0.10
0.10
SEATING
PLANE
aaa C
A1
C
D1
LxN
E/2
E1
2
1
N
bxN
bbb
e
C A B
D/2
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Land Pattern - MLPQ - 20
K
DIMENSIONS
(C)
Z
G
H
Y
DIM
C
G
H
K
P
X
Y
Z
INCHES
(.156)
.122
.106
.106
.020
.010
.033
.189
MILLIMETERS
(3.95)
3.10
2.70
2.70
0.50
0.25
0.85
4.80
X
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
 2010 Semtech Corp.
19
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SC4624
POWER MANAGEMENT
Outline Drawing - SO-16 EDP
A
D
e
N
2X
DIM
E/2
E1
1
2
ccc C
2X N/2 TIPS
A
A1
A2
b
c
D
E1
E
e
F
H
h
L
L1
N
01
aaa
bbb
ccc
E
3
e/2
B
D
aaa C
SEATING
PLANE
A2
C
bxN
A
A1
bbb
.053
.069
.000
.005
.049
.065
.012
.020
.007
.010
.390
.386
.394
.154
.150
.157
.236 BSC
.050 BSC
.100
.105
.110
.080
.085
.090
.010
.020
.028
.016
.041
(.041)
16
0°
8°
.004
.010
.008
1.35
0.00
1.25
0.31
0.17
9.80
3.80
2.54
2.03
0.25
0.40
0°
1.75
0.13
1.65
0.51
0.25
9.90 10.00
4.00
3.90
6.00 BSC
1.27 BSC
2.67
2.79
2.16
2.29
0.50
0.72
1.04
(1.04)
16
8°
0.10
0.25
0.20
C A-B D
F
EXPOSED PAD
DIMENSIONS
MILLIMETERS
INCHES
MIN NOM MAX MIN NOM MAX
H
c
GAUGE
PLANE
H
L
(L1)
0.25
DETAIL
h
h
SEE DETAIL
01
A
A
SIDE VIEW
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
DATUMS
3.
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4.
REFERENCE JEDEC STD MS-012, VARIATION AC.
-A-
AND
-B-
TO BE DETERMINED AT DATUM PLANE -H-
Land Pattern - SO-16 EDP
E
THERMAL VIA
Ø 0.36mm
SOLDER MASK
D
DIM
(C)
G
F
Z
Y
P
X
C
D
E
F
G
P
X
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.205)
.114
.201
.094
.118
.050
.024
.087
.291
(5.20)
2.90
5.10
2.40
3.00
1.27
0.60
2.20
7.40
NOTES:
 2010 Semtech Corp.
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2.
REFERENCE IPC-SM-782A, RLP NO. 300A.
3.
THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
20
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SC4624
POWER MANAGEMENT
© 2010 Semtech Corporation
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no
responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation,
repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond
the specified maximum ratings or operation outside the specified range.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT
APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH
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use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could
arise.
Contact Information
Semtech Corporation
Power Mangement Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
 2010 Semtech Corp.
21
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