HD74SSTV16857A
1:1 14-bit SSTL_2 Registered Buffer
REJ03D0831-0100
(Previous: ADE-205-695)
Rev.1.00
Apr 07, 2006
Description
The HD74SSTV16857A is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset
(RESET) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on the
positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise margins.
When RESET is low, all registers are reset and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low
state during power up.
Features
•
•
•
•
Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input
Differential SSTL_2 (Stub series terminated logic) CLK signal
Flow through architecture optimizes PCB layout
Ordering Information
Part Name
Package Type
Package Code
(Previous code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74SSTV16857ATEL
TSSOP-48 pin
PTSP0048KA-A
(TTP-48DBV)
T
EL (1,000 pcs / Reel)
HD74SSTV16857ANEL
TVSOP-48 pin
PTSP0048LA-A
(TTP-48DEV)
N
EL (1,000 pcs / Reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
H:
L:
X:
↑:
↓:
Note:
RESET
L
H
H
CLK
X
↓
↓
CLK
X
↑
↑
D
X
H
L
H
L or H
H or L
X
High level
Low level
Immaterial
Low to high transition
High to low transition
1. Output level before the indicated steady state input conditions were established.
Rev.1.00 Apr 07, 2006 page 1 of 10
Output Q
L
H
L
Q0
*1
HD74SSTV16857A
Pin Arrangement
Q1 1
48 D1
Q2 2
47 D2
GND 3
46 GND
V DDQ 4
45 V CC
Q3 5
44 D3
Q4 6
43 D4
Q5 7
42 D5
GND 8
41 D6
V DDQ 9
40 D7
Q6 10
39 CLK
Q7 11
38 CLK
V DDQ 12
37 V CC
GND 13
36 GND
Q8 14
35 V REF
Q9 15
34 RESET
V DDQ 16
33 D8
GND 17
32 D9
Q10 18
31 D10
Q11 19
30 D11
Q12 20
29 D12
V DDQ 21
28 V CC
GND 22
27 GND
Q13 23
26 D13
Q14 24
25 D14
(Top view)
Rev.1.00 Apr 07, 2006 page 2 of 10
HD74SSTV16857A
Absolute Maximum Ratings
Item
Supply voltage
Input voltage *1
Output voltage *1, 2
Input clamp current
Output clamp current
Continuous output current
VCC, VDDQ or GND current / pin
Symbol
VCC or VDDQ
VI
VO
IIK
IOK
IO
ICC, IDDQ or IGND
Maximum power dissipation
at Ta = 55°C (in still air)
Storage temperature
Notes:
PT
Ratings
–0.5 to 3.6
–0.5 to VDDQ+0.5
–0.5 to VDDQ+0.5
±50
±50
±50
±100
115
Unit
V
V
V
mA
mA
mA
mA
°C / W
Tstg
–65 to +150
°C
Conditions
VI < 0 or VI > VCC
VO < 0 or VO > VDDQ
VO = 0 to VDDQ
TSSOP
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum
rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
2. This current will flow only when the output is in the high state and VO > VDDQ.
Recommended Operating Conditions
Item
Supply voltage
Output supply voltage
Reference voltage
Termination voltage
Input voltage
AC high level input voltage
AC low level input voltage
DC high level input voltage
DC low level input voltage
High level input voltage
Low level input voltage
Differential (Common mode range)
input voltage (Minimum peak to
Symbol
VCC
VDDQ
VREF
VTT
VI
VIH
VIL
VIH
VIL
VIH
VIL
VCMR
VPP
Min
VDDQ
2.3
1.15
VREF–40 mV
0
VREF+310 mV
—
VREF+150 mV
—
1.7
–0.3
0.97
360
Typ
2.5
2.5
1.25
VREF
—
—
—
—
—
—
—
—
—
Max
2.7
2.7
1.35
VREF+40 mV
VCC
—
VREF–310 mV
—
VREF–150 mV
VDDQ+0.3
0.7
1.53
—
Unit
V
V
V
V
V
V
V
V
V
V
V
V
mV
IOH
IOL
Ta
—
—
0
—
—
—
–20
20
70
mA
mA
°C
Conditions
VREF = 0.5 × VDDQ
D
D
D
D
RESET
RESET
CLK, CLK
CLK, CLK
peak input)
High level output current
Low level output current
Operating temperature
Note: The RESET input of the device must be held at VDDQ or GND to ensure proper device operation. The differential
inputs must not be floating, unless RESET is low.
Rev.1.00 Apr 07, 2006 page 3 of 10
HD74SSTV16857A
Logic Diagram
*1
RESET
34
CLK
CLK
38
39
D1
VREF
48
1D
C1
1
Q1
R
35
To thirteen other channels
Note:
1. RESET input gate is connected to VDDQ.
Electrical Characteristics
Item
Input diode voltage
Output voltage
Symbol
VIK
VOH
VOL
Input current
(All inputs)
Quiescent supply current
Standby current
Dynamic operating clock only
IIN
ICC
*2
ICC (stdy)
ICCD *2
VCC (V)
2.3
Min
—
2.3 to 2.7 VCC–0.2
2.3
1.95
2.3 to 2.7
—
2.3
0
2.7
—
2.7
—
2.7
2.7
—
—
Typ
—
Max
–1.2
Unit
V
—
—
—
—
—
25
—
VDDQ
0.2
0.35
±5
45
V
—
38
10
45
µA
mA
µA
µA/
clock
MHz
Test Conditions
IIN = –18 mA
IOH = –100 µA
IOH = –16 mA
IOL = 100 µA
IOL = 16 mA
VIN = 2.7 V or 0
VIN = VIH(AC) or VIL(AC), IO =
0
RESET = GND
RESET = VCC,
VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50%
duty cycle
Dynamic operating per each
data input
ICCD
*2
2.7
—
11
15
µA/
clock
MHz/
data input
RESET = VCC,
VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50%
duty cycle. One data input
switching at half clock
frequency, 50% duty cycle.
Output high *3
Output low *3
rOH
rOL
2.3 to 2.7
2.3 to 2.7
7
7
—
—
20 *4
20 *4
Ω
Ω
IOH = –20 mA
IOL = 20 mA
rOH – rOL each
*3
separate bit
rO(∆)
2.5
—
—
4
Ω
IO = 20 mA, Ta = 25°C
CIN
2.5 *1
2.5
2.5
—
—
—
3.0
3.5
3.5
—
pF
VI = VREF±310 mV
Input
capacitance
Data inputs
CLK and CLK
RESET
Notes: 1.
2.
3.
4.
All typical values are at VCC = 2.5 V, Ta = 25°C.
Total ICC (max) = ICC + {ICCD (clock)×f(clock)} + {ICCD (Data)×1/2f(clock)×14}
This is effective in the case that it did terminate by resistance.
See figure. 1, 2.
Rev.1.00 Apr 07, 2006 page 4 of 10
VCMR = 1.25 V, VPP = 360 mV
VI = VCC or GND
HD74SSTV16857A
Switching Characteristics
Item
Symbol
VCC = 2.5 ± 0.2 V
Min
Max
—
200
0.75
—
0.9
—
0.75
—
0.9
—
22
—
Clock frequency *1
Setup time
Fast slew rate *4, 6
Slow slew rate *5, 6
Hold time
Fast slew rate *4, 6
Slow slew rate *5, 6
Differential inputs active time
fclock
tsu
Differential inputs inactive time
tinact
22
Pulse width Output slew *3
tw
tSL
2.5
1
th
tact
Unit
MHz
ns
Test Condition
Data before CLK↑, CLK↓
ns
Data after CLK↑, CLK↓
ns
Data inputs must be low after
RESET high.
—
ns
—
4
ns
volt/ns
Data and clock inputs must
be held at valid levels (not
floating) after RESET low.
CLK, CLK “H” or “L”
(CL = 30 pF, RL = 50 Ω, VREF = VTT = VDDQ × 0.5)
Item
Symbol
Maximum clock frequency
4.
5.
6.
Min
200
Typ
—
Max
—
Unit
FROM
(Input)
TO
(Output)
MHz
tPLH, tPHL
1.1
—
2.8
ns
CLK, CLK
Q
tPHL
—
—
5.0
RESET
Q
Although the clock is differential, all timing is relative to CLK going high and CLK going low.
This timing relationship is specified into test load (see waveforms – 3, 4) with all of the outputs switching.
Assumes into an equivalent, distributed load to the address net structure defined in the application
information provided in this specification.
For data signal input slew rate ≥ 1 V/ns.
For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns.
CLK, CLK signals input slew rates are ≥ 1 V/ns.
Propagation delay time
Notes: 1.
2.
3.
fmax
VCC = 2.5±0.2 V
*2
Rev.1.00 Apr 07, 2006 page 5 of 10
HD74SSTV16857A
Test Circuit
VTT
*2
50 Ω
Test point
*1
C L = 30 pF
Notes:
1. CL includes probe and jig capacitance.
2. VTT = VREF = VDDQ × 0.5
Waveforms – 1
LVCMOS
RESET
Input
VCC
VCC /2
VCC /2
0V
tinact
tact
*1
I CC
I CCH
90 %
10 %
I CCL
Waveforms – 2
tw
VIH
Input
VREF
VREF
VIL
Timing input
VCMR
tsu
VPP
th
VIH
Input
VREF
VREF
VIL
Rev.1.00 Apr 07, 2006 page 6 of 10
HD74SSTV16857A
Waveforms – 3
Timing input
VCMR
VCMR
tPLH
VPP
tPHL
V OH
Output
VTT
VTT
VOL
Waveforms – 4
LVCMOS
RESET
Input
VIH
VCC /2
VIL
tPHL
VOH
Output
VTT
VOL
Notes:
1. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA.
2. All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, Zo = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
3. The outputs are measured one at a time with one transition per measurement.
4. VTT = VREF = VDDQ/2
5. VIH = VREF+310 mV (AC voltage levels) for differential inputs. VIH = VCC for LVCMOS input.
6. VIL = VREF–310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
7. tPLH and tPHL are the same as tpd
Rev.1.00 Apr 07, 2006 page 7 of 10
HD74SSTV16857A
Application Data
• Pull-down
100
Current (Amps)
80
60
40
Min
Max
20
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
2.0
2.5
3.0
Voltage (V)
Figure 1
• Pull-up
0.0
0
Voltage (V)
0.5
1.0
1.5
Min
Max
Current (Amps)
-20
-40
-60
-80
-100
Figure 2
Rev.1.00 Apr 07, 2006 page 8 of 10
HD74SSTV16857A
Curve Data
Pull-down
Pull-up
Voltage (V)
I (mA)
I (mA)
I (mA)
I (mA)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Min
0
6
11.5
16
20
23
27
30.5
34
36.5
38.5
40
42
43
44
44
45
45
45
45
45
46
46
46
46
46
46
46
Max
0
7
15
22
29
35.5
41.5
48
54
59
65
70
75
79
82
84.5
87
89
90
90
91
91
91
91
91.5
92
92
92
Min
0
–6
–11.5
–16
–20
–23.5
–28
–31.5
–35
–38
–41
–44
–46
–48
–50
–51
–52
–52
–52.5
–53
–53
–53.5
–54
–54
–54
–54.5
–55
–55
Max
0
–7
–13
–19
–25
–31
–37
–42
–47
–53
–58
–62
–66
–71
–74
–77
–81
–84
–86
–89
–91
–92
–93
–94
–95
–96.5
–98
–99
Rev.1.00 Apr 07, 2006 page 9 of 10
HD74SSTV16857A
Package Dimensions
JEITA Package Code
P-TSSOP48-6.1x12.5-0.50
RENESAS Code
PTSP0048KA-A
*1
Previous Code
TTP-48DBV
MASS[Typ.]
0.2g
D
F
48
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
25
*2
E
HE
c
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
Reference Dimension in Millimeters
Symbol
24
1
e
*3
bp
L1
x
M
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
A
Z
θ
A1
y
L
Detail F
JEITA Package Code
P-TSSOP48-4.4x9.7-0.40
RENESAS Code
PTSP0048LA-A
*1
Previous Code
TTP-48DEV
Min Nom Max
12.5 12.7
6.10
0.08 0.13 0.18
1.20
0.14 0.19 0.24
0.10 0.15 0.20
0°
8°
7.90 8.10 8.30
0.50
0.08
0.10
0.65
0.4 0.5 0.6
1.0
MASS[Typ.]
0.077g
D
F
48
25
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
c
HE
*2
E
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
Reference Dimension in Millimeters
Symbol
24
1
e
*3
bp
L1
x
M
A
Z
A1
θ
L
y
Detail F
Rev.1.00 Apr 07, 2006 page 10 of 10
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Min Nom Max
9.70 9.90
4.40
0.05 0.10 0.15
1.20
0.13 0.18 0.23
0.10 0.15 0.20
0°
8°
6.20 6.40 6.60
0.40
0.07
0.08
0.40
0.40 0.50 0.60
1.00
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Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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