HD74SSTV32852
24-bit to 48-bit Registered Buffer with SSTL_2 Inputs and Outputs
REJ03D0833-0400
(Previous: ADE-205-687C)
Rev.4.00
Apr 07, 2006
Description
The HD74SSTV32852 is a 24-bit to 48-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS
reset (RESET) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to QA, QB is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on
the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise margins.
When RESET is low, all registers are reset and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low
state during power up.
Features
•
•
•
•
Supports LVCMOS reset (RESET)) input / SSTL_2 data (D) inputs and CLK input
Differential SSTL_2 (Stub series terminated logic) CLK signal
Pinout optimizes DIMM PCB layout
Ordering Information
Part Name
HD74SSTV32852LBEL
Package Type
LFBGA-114pin
Package Code
(Previous code)
PLBG0114GA-A
(BP-114V)
Package
Abbreviation
Taping Abbreviation
(Quantity)
LB
EL (1,000 pcs / Reel)
Function Table
Inputs
RESET *2
L
H
H
CL
CLK
LK
LK
X or floating
↓
↓
Outputs
CLK
X or floating
↑
↑
D
X or floating
H
L
QA
L
H
L
H
L or H
H or L
X
Q0
H:
High level
L:
Low level
X:
Immaterial
↑:
Low to high transition
↓:
High to low transition
Notes: 1. Output level before the indicated steady state input conditions were established.
2. See under the figure.
Rev.4.00 Apr 07, 2006 page 1 of 8
*1
QB
L
H
L
Q0
*1
HD74SSTV32852
Pin Arrangement
1
2
3
4
5
6
A
Height 1.4 mm
0.8 mm pitch
0.5 mm 114-Ball
B
C
D
E
F
G
16 mm
H
J
K
L
M
N
P
R
T
U
V
W
5.5 mm
(Top view)
Terminal Assignment
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1
Q2A
Q3A
Q5A
Q7A
Q8A
Q10A
Q12A
Q13A
Q14A
Q17A
Q18A
Q20A
Q22A
Q23A
Q24A
D2
D4
D5
D8
Rev.4.00 Apr 07, 2006 page 2 of 8
2
Q1A
VDDQ
Q4A
Q6A
GND
Q9A
Q11A
VCC
Q15A
Q16A
Q19A
VDDQ
Q21A
VDDQ
VCC
D1
D3
D7
D9
3
CLK
GND
VDDQ
GND
VDDQ
VDDQ
GND
VDDQ
GND
VDDQ
GND
GND
VDDQ
GND
RESET
D6
D10
D11
D12
4
CLK
GND
VDDQ
GND
VDDQ
VDDQ
GND
VDDQ
GND
VDDQ
GND
GND
VDDQ
GND
VREF
D18
D22
D23
D24
5
Q1B
VDDQ
Q4B
Q6B
GND
Q9B
Q11B
VCC
Q15B
Q16B
Q19B
VDDQ
Q21B
VDDQ
VCC
D13
D15
D19
D21
6
Q2B
Q3B
Q5B
Q7B
Q8B
Q10B
Q12B
Q13B
Q14B
Q17B
Q18B
Q20B
Q22B
Q23B
Q24B
D14
D16
D17
D20
HD74SSTV32852
Absolute Maximum Ratings
Item
Supply voltage
Input voltage *1
Output voltage *1
Input clamp current
Output clamp current
Continuous output current
VCC, VDDQ or GND current / pin
Package thermal impedance
Storage temperature
Notes:
Symbol
VCC or VDDQ
VI
VO
IIK
IOK
IO
ICC, IDDQ or IGND
θJA
Tstg
Ratings
–0.5 to 3.6
–0.5 to VDDQ+0.5
–0.5 to VDDQ+0.5
±50
±50
±50
±100
36
–65 to +150
Unit
V
V
V
mA
mA
mA
mA
°C/W
°C
Conditions
VI < 0 or VI > VCC
VO < 0 or VO > VDDQ
VO = 0 to VDDQ
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum
rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
Recommended Operating Conditions
Item
Supply voltage
Output supply voltage
Reference voltage
Termination voltage
Input voltage
AC high level input voltage
AC low level input voltage
DC high level input voltage
DC low level input voltage
High level input voltage
Low level input voltage
Differential (Common mode range)
input voltage (Minimum peak to
peak input)
High level output current
Low level output current
Operating temperature
Symbol
VCC
VDDQ
VREF
VTT
VI
VIH
VIL
VIH
VIL
VIH
VIL
VCMR
VPP
Min
VDDQ
2.3
1.15
VREF–40 mV
0
VREF+310 mV
—
VREF+150 mV
—
1.7
–0.3
0.97
360
Typ
2.5
2.5
1.25
VREF
—
—
—
—
—
—
—
—
—
Max
2.7
2.7
1.35
VREF+40 mV
VCC
—
VREF–310 mV
—
VREF–150 mV
VDDQ+0.3
0.7
1.53
—
Unit
V
V
V
V
V
V
V
V
V
V
V
V
mV
IOH
IOL
Ta
—
—
0
—
—
—
–20
20
70
mA
mA
°C
Conditions
VREF = 0.5 × VDDQ
D
D
D
D
RESET
RESET
CLK, CLK
CLK, CLK
Note: The RESET input of the device must be held at VDDQ or GND to ensure proper device operation. The differential
inputs must not be floating, unless RESET is low.
Rev.4.00 Apr 07, 2006 page 3 of 8
HD74SSTV32852
Logic Diagram
*1
RESET
R3
CLK
CLK
A3
A4
T2
D1
A2
1D
C1
A5
R
R4
VREF
Q1A
Q1B
To 23 other channels
Note:
1. RESET input gate is connected to VDDQ.
Electrical Characteristics
Item
Input diode voltage
Symbol
VIK
Output voltage
VOH
VOL
Input current
(All inputs)
Quiescent supply current
IIN
ICC
Standby current
Dynamic operating clock only
*2
ICC (stdy)
ICCD *2
VCC (V)
2.3
Min
—
2.3 to 2.7 VCC–0.2
2.3
1.95
2.3 to 2.7
—
2.3
0
2.7
—
2.7
—
2.7
2.7
—
—
Typ
—
Max
–1.2
Unit
V
—
—
—
—
—
—
—
VDDQ
0.2
0.35
±5
35
V
—
80
10
—
µA
mA
µA
µA/
clock
MHz
Test Conditions
IIN = –18 mA
IOH = –100 µA
IOH = –16 mA
IOL = 100 µA
IOL = 16 mA
VIN = 2.7 V or 0
VIN = VIH(AC) or VIL(AC), IO =
0
RESET = GND
RESET = VCC,
VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50%
duty cycle
ICCD
Dynamic operating per each
data input
*3
2.7
—
14
—
µA/
clock
MHz/
data
input
RESET = VCC,
VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50%
duty cycle. One data input
switching at half clock
frequency, 50% duty cycle.
rOH
rOL
2.3 to 2.7
2.3 to 2.7
7
7
—
—
20
20
Ω
Ω
IOH = –20 mA
IOL = 20 mA
rO(∆)
2.5
2.5 *1
—
4.0
3.0
3.5
—
—
—
—
4
5.0
4.0
5.0
Ω
pF
IO = 20 mA, Ta = 25°C
VI = VREF±310 mV
Output high *3
Output low *3
rOH – rOL each separate bit
Data inputs
Input
capacitance
CLK and CLK
*2
RESET
CIN
Notes: 1. All typical values are at VCC = 2.5 V, Ta = 25°C.
2. Total ICC (max) = ICC + {ICCD (clock)×f(clock)} + {ICCD (Data)×1/2f(clock)×24}
3. This is effective in the case that it did terminate by resistance.
Rev.4.00 Apr 07, 2006 page 4 of 8
VCMR = 1.25 V, VPP = 360 mV
VI = VCC or GND
HD74SSTV32852
Switching Characteristics
Item
Symbol
VCC = 2.5 ± 0.2 V
Min
Max
—
200
0.75
—
0.9
—
0.75
—
0.9
—
22
—
Clock frequency *1
Setup time
Fast slew rate *4, 6
Slow slew rate *5, 6
Hold time
Fast slew rate *4, 6
Slow slew rate *5, 6
Differential inputs active time
fclock
tsu
Differential inputs inactive time
tinact
22
Pulse width
Output slew *3
tw
tSL
2.5
1
th
tact
Unit
MHz
ns
Test Condition
Data before CLK↑, CLK↓
ns
Data after CLK↑, CLK↓
ns
Data inputs must be low after
RESET high.
—
ns
—
4
ns
volt/ns
Data and clock inputs must be held
at valid levels (not floating) after
RESET low.
CLK, CLK “H” or “L”
(CL = 30 pF, RL = 50 Ω, VREF = VTT = VDDQ × 0.5)
Item
Symbol
Maximum clock frequency
4.
5.
6.
Min
200
Typ
—
Max
—
Unit
FROM
(Input)
TO
(Output)
MHz
tPLH, tPHL
1.1
—
3.1
ns
CLK, CLK
QA, QB
tPHL
—
—
5.0
RESET
QA, QB
Although the clock is differential, all timing is relative
lative to CLK going high and CLK going low.
This timing relationship is specified into test load (see waveforms – 3, 4) with all of the outputs switching.
Assumes into an equivalent, distributed load to the address net structure def
defined in the application
information provided in this specification.
For data signal input slew rate ≥ 1 V/ns.
For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns.
CLK, CLK signals input slew rates are ≥ 1 V/ns.
Propagation delay time
Notes: 1.
2.
3.
fmax
VCC = 2.5 ± 0.2 V
*2
Rev.4.00 Apr 07, 2006 page 5 of 8
HD74SSTV32852
Test Circuit
VTT
*2
50 Ω
Test point
*1
C L = 30 pF
Notes:
1. CL includes probe and jig capacitance.
2. VTT = VREF = VDDQ × 0.5
Waveforms – 1
LVCMOS
RESET
Input
VCC
VCC /2
VCC /2
0V
tinact
tact
*1
I CC
I CCH
90 %
10 %
I CCL
Waveforms – 2
tw
VIH
Input
VREF
VREF
VIL
Timing input
VCMR
tsu
VPP
th
VIH
Input
VREF
VREF
VIL
Rev.4.00 Apr 07, 2006 page 6 of 8
HD74SSTV32852
Waveforms – 3
Timing input
VCMR
VCMR
tPLH
VPP
tPHL
V OH
Output
VTT
VTT
VOL
Waveforms – 4
LVCMOS
RESET
Input
VIH
VCC /2
VIL
tPHL
VOH
Output
VTT
VOL
Notes:
1. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA.
2. All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, Zo = 50 Ω,, input slew rate = 1 V/ns ±20% (unless otherwise specified).
3. The outputs are measured one at a time with one transition per measurement.
4. VTT = VREF = VDDQ/2
5. VIH = VREF+310 mV (AC voltage levels) for differential inputs. VIH = VCC for LVCMOS input.
6. VIL = VREF–310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
7. tPLH and tPHL are the same as tpd
Rev.4.00 Apr 07, 2006 page 7 of 8
HD74SSTV32852
Package Dimensions
JEITA Package Code
P-LFBGA114-5.5x16-0.80
RENESAS Code
PLBG0114GA-A
Previous Code
BP-114/BP-114V
D
w S A
MASS[Typ.]
0.22g
w S B
E
Pin#1 Index
×4
v
y1 S
y
A1
A
S
S
A
e
ZD
e
W
V
U
Reference
Symbol
T
R
P
N
B
M
L
Dimension in Millimeters
Min
Nom
D
5.50
E
16.00
v
Max
0.15
K
w
0.20
J
A
1.40
H
A1
G
0.35
F
0.40
0.45
0.80
e
0.40
0.50
0.60
E
b
D
x
0.08
y
0.10
y1
0.2
ZE
C
B
A
SD
INDEX MARK
1
2
3
4
6
SE
φ b
Rev.4.00 Apr 07, 2006 page 8 of 8
5
φ
×M S A B
ZD
0.75
ZE
0.80
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