FDMD84100 Dual N-Channel PowerTrench® MOSFET

FDMD84100
Dual N-Channel PowerTrench® MOSFET
100 V, 21 A, 20 mΩ
Features
General Description
„ Max rDS(on) = 20 mΩ at VGS = 10 V, ID = 7 A
„ Ideal for flexible layout in secondary side synchronous
rectification
This package integrates two N-Channel devices connected
internally in common-source configuration. This enables very
low package parasitics and optimized thermal path to the
common source pad on the bottom. Provides a very small
footprint (3.3 x 5 mm) for higher power density.
„ Termination is Lead-free and RoHS Compliant
Applications
„ 100% UIL tested
„ Isolated DC-DC Synchronous Rectifiers
„ Max rDS(on) = 32 mΩ at VGS = 6 V, ID = 5.5 A
„ Common Ground Load Switches
Bottom
Top
D2
D2
D2
G2
Pin 1
G1
1
8
D2
D1
2
7
D2
D1
3
6
D2
D1
4
5
G2
S1/S2
G1
D1
D1
D1
Pin 1
S1,S2 to backside
Power 3.3 x 5
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
Drain to Source Voltage
Parameter
VGS
Gate to Source Voltage
Drain Current
ID
-Continuous
TC = 25 °C
-Continuous
TA = 25 °C
-Pulsed
Single Pulse Avalanche Energy
EAS
PD
TJ, TSTG
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Ratings
100
Units
V
±20
V
21
(Note 1a)
7
(Note 4)
80
(Note 3)
121
23
(Note 1a)
Operating and Storage Junction Temperature Range
2.1
-55 to +150
A
mJ
W
°C
Thermal Characteristics
RθJC
Thermal Resistance, Junction to Case
RθJA
Thermal Resistance, Junction to Ambient
5.3
(Note 1a)
60
°C/W
Package Marking and Ordering Information
Device Marking
FDMD84100
Device
FDMD84100
©2014 Fairchild Semiconductor Corporation
FDMD84100 Rev.C
Package
Power 3.3 x 5
1
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com
FDMD84100 Dual N-Channel PowerTrench® MOSFET
January 2014
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
IDSS
Zero Gate Voltage Drain Current
VDS = 80 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS = ±20 V, VDS = 0 V
±100
nA
4
V
100
V
74
mV/°C
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
-9
VGS = 10 V, ID = 7 A
16
rDS(on)
Static Drain to Source On Resistance
VGS = 6 V, ID = 5.5 A
24
32
VGS = 10 V, ID = 7 A, TJ = 125 °C
30
38
VDD = 5 V, ID = 7 A
17
gFS
Forward Transconductance
2
3.1
mV/°C
20
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
VDS = 50 V, VGS = 0 V
f = 1 MHz
0.1
734
980
pF
168
225
pF
6.6
15
pF
1.3
3
Ω
8.4
17
ns
2.6
10
ns
14
25
ns
2.8
10
ns
11
16
nC
7.3
11
nC
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
Qg(TOT)
VDD = 50 V, ID = 7 A
VGS = 10 V, RGEN = 6 Ω
Total Gate Charge
VGS = 0 V to 10 V
Total Gate Charge
VGS = 0 V to 6 V
Qgs
Gate to Source Charge
Qgd
Gate to Drain “Miller” Charge
VDD = 50 V
ID = 7 A
3.4
nC
2.5
nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 7 A
(Note 2)
IF = 7 A, di/dt = 100 A/μs
0.8
1.2
V
43
70
ns
44
71
nC
NOTES:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
b.160 °C/W when mounted on
a minimum pad of 2 oz copper
a. 60 °C/W when mounted on
a 1 in2 pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. EAS of 121 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = 9 A, VDD = 100 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 30 A.
4. Pulse Id refers to Figure.11 Forward Bias Safe Operation Area.
©2014 Fairchild Semiconductor Corporation
FDMD84100 Rev.C
2
www.fairchildsemi.com
FDMD84100 Dual N-Channel PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted
4
ID, DRAIN CURRENT (A)
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
80
VGS = 8 V
60
VGS = 7 V
40
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 6 V
20
VGS = 5 V
0
0
1
2
3
4
VGS = 5 V
3
VGS = 6 V
VGS = 7 V
2
VGS = 8 V
1
0
0
5
20
40
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics
80
100
ID = 7 A
VGS = 10 V
2.0
rDS(on), DRAIN TO
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
-75
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
60
Figure 2. Normalized On- Resistance
vs Drain Current and Gate Voltage
2.2
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
80
ID = 7 A
60
TJ = 125 oC
40
20
TJ = 25 oC
0
-50
4
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
5
6
7
8
9
10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On- Resistance
vs Junction Temperature
Figure 4. On-Resistance vs Gate to
Source Voltage
80
IS, REVERSE DRAIN CURRENT (A)
100
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID, DRAIN CURRENT (A)
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
60
VDS = 5 V
40
TJ = 150 oC
20
TJ = 25 oC
TJ = -55 oC
0
2
4
6
8
10
TJ = 150 oC
1
TJ = 25 oC
0.1
0.01
TJ = -55 oC
0.001
0.0
10
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
©2014 Fairchild Semiconductor Corporation
FDMD84100 Rev.C
VGS = 0 V
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
3
www.fairchildsemi.com
FDMD84100 Dual N-Channel PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted
2000
Ciss
1000
VDD = 50 V
ID = 7 A
8
VDD = 25 V
Coss
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
VDD = 75 V
6
4
100
Crss
10
f = 1 MHz
VGS = 0 V
2
1
0.1
0
0
2
4
6
8
10
12
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 8. Capacitance vs Drain
to Source Voltage
Figure 7. Gate Charge Characteristics
50
25
TJ =
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
o
RθJC = 5.3 C/W
25 oC
10
TJ = 100 oC
TJ = 125 oC
1
0.001
0.01
0.1
1
10
20
15
10
VGS = 6 V
5
0
25
50
50
125
150
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
200
10000
P(PK), PEAK TRANSIENT POWER (W)
100
ID, DRAIN CURRENT (A)
100
TC, CASE TEMPERATURE ( C)
Figure 9. Unclamped Inductive
Switching Capability
10 µs
THIS AREA IS
LIMITED BY rDS(on)
100 µs
SINGLE PULSE
TJ = MAX RATED
RθJC = 5.3 oC/W
1 ms
CURVE BENT TO
MEASURED DATA
TC = 25 oC
1
10
10 ms
DC
100
300
TC = 25 oC
100
10
-5
10
-4
10
-3
10
-2
10
-1
10
1
t, PULSE WIDTH (sec)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 12. Single Pulse Maximum
Power Dissipation
Figure 11. Forward Bias Safe
Operating Area
©2014 Fairchild Semiconductor Corporation
FDMD84100 Rev.C
SINGLE PULSE
Rθ JC = 5.3 oC/W
1000
10
0.1
0.1
75
o
tAV, TIME IN AVALANCHE (ms)
1
VGS = 10 V
Limited by Package
4
www.fairchildsemi.com
FDMD84100 Dual N-Channel PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
2
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
NOTES:
0.01
ZθJC(t) = r(t) x RθJC
RθJC = 5.3 oC/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
SINGLE PULSE
0.001
-5
10
-4
10
-3
-2
10
10
-1
10
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Case Transient Thermal Response Curve
©2014 Fairchild Semiconductor Corporation
FDMD84100 Rev.C
5
www.fairchildsemi.com
FDMD84100 Dual N-Channel PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted
FDMD84100 Dual N-Channel PowerTrench® MOSFET
Dimensional Outline and Pad Layout
B
KEEP OUT
AREA
2X
A
2X
TOP VIEW
LAND PATTERN
RECOMMENDATION
SEE DETAIL A
FRONT VIEW
C
DETAIL A
SCALE: 2X
BOTTOM VIEW
©2014 Fairchild Semiconductor Corporation
FDMD84100 Rev.C
6
www.fairchildsemi.com
tm
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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2.
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Product Status
Definition
Advance Information
Formative / In Design
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Preliminary
First Production
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
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No Identification Needed
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Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
Obsolete
Not In Production
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Rev. I66
©2014 Fairchild Semiconductor Corporation
FDMD84100 Rev.C
7
www.fairchildsemi.com
FDMD84100 Dual N-Channel PowerTrench® MOSFET
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