FDMD8280 Dual N-Channel Power Trench® MOSFET 80 V, 40 A, 8.2 mΩ Features General Description Max rDS(on) = 8.2 mΩ at VGS = 10 V, ID = 11 A This device includes two 80V N-Channel MOSFETs in a dual Power (3.3 mm X 5 mm) package. HS source and LS Drain internally connected for half/full bridge, low source inductance package, low rDS(on)/Qg FOM silicon. Max rDS(on) = 11 mΩ at VGS = 8 V, ID = 9.5 A Ideal for flexible layout in primary side of bridge topology Termination is Lead-free and RoHS Compliant Applications 100% UIL tested Synchronous Buck : Primary Switch of Half / Full bridge converter for telecom Kelvin High Side MOSFET drive pin-out capability Motor Bridge : Primary Switch of Half / Full bridge converter for BLDC motor MV POL : 48V Synchronous Buck Switch Pin 1 D1 1 12 G1 D1 2 11 D1 3 10 D2/S1 G2 4 9 D2/S1 S2 5 8 D2/S1 S2 6 7 D2/S1 G1R Power 3.3 x 5 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current ID -Continuous TC = 25 °C -Continuous TA = 25 °C Drain Current -Pulsed Single Pulse Avalanche Energy EAS PD TJ, TSTG Ratings 80 Units V ±20 V 40 (Note 1a) 11 (Note 4) 160 (Note 3) 150 Power Dissipation TC = 25 °C Power Dissipation TA = 25 °C (Note 1a) 2.1 Power Dissipation TA = 25 °C (Note 1b) 1 A mJ 38 Operating and Storage Junction Temperature Range -55 to +150 W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case 3.3 RθJA Thermal Resistance, Junction to Ambient (Note 1a) 60 RθJA Thermal Resistance, Junction to Ambient (Note 1b) 130 °C/W Package Marking and Ordering Information Device Marking 8280 Device FDMD8280 ©2014 Fairchild Semiconductor Corporation FDMD8280 Rev.C Package Power 3.3 x 5 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMD8280 Dual N-Channel PowerTrench® MOSFET October 2014 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 64 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 4.0 V 80 V 48 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C -9 VGS = 10 V, ID = 11 A 6.6 rDS(on) Static Drain to Source On Resistance VGS = 8 V, ID = 9.5 A 7.5 11 VGS = 10 V, ID = 11 A, TJ = 125 °C 10 12.4 VDD = 10 V, ID = 11 A 29 gFS Forward Transconductance 2.0 3.0 mV/°C 8.2 mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 40 V, VGS = 0 V f = 1 MHz 0.1 2179 3050 pF 341 480 pF 15 25 pF 2.7 5.4 Ω 15 27 ns 12 22 ns 26 42 ns Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg(TOT) VDD = 40 V, ID = 11 A VGS = 10 V, RGEN = 6 Ω Total Gate Charge VGS = 0 V to 10 V Total Gate Charge VGS = 0 V to 8 V Qgs Gate to Source Charge Qgd Gate to Drain “Miller” Charge VDD = 40 V ID = 11 A 8.9 18 ns 31 44 nC 25 35 nC 9.5 nC 6.6 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 11 A (Note 2) 0.8 1.3 VGS = 0 V, IS = 1.8 A (Note 2) 0.7 1.2 IF = 11 A, di/dt = 100 A/μs V 27 43 ns 12 22 nC NOTES: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. b. 130 °C/W when mounted on a minimum pad of 2 oz copper a. 60 °C/W when mounted on a 1 in2 pad of 2 oz copper SS SF DS DF G SS SF DS DF G 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %. 3. EAS of 150 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = 10 A, VDD = 72 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 32 A. 4. Pulse Id measured at td <= 250μs, refer to Fig 11 SOA graph for more details. ©2014 Fairchild Semiconductor Corporation FDMD8280 Rev.C 2 www.fairchildsemi.com FDMD8280 Dual N-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 160 5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) VGS = 10 V VGS = 8 V 120 VGS = 6.5 V 80 VGS = 6 V 40 0 VGS = 5.5 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 1 2 3 4 5 VGS = 5.5 V VGS = 6 V 4 VGS = 6.5 V 3 VGS = 8 V 2 1 0 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 40 VDS, DRAIN TO SOURCE VOLTAGE (V) rDS(on), DRAIN TO 1.5 1.2 0.9 -25 0 25 50 75 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 50 ID = 11 A VGS = 10 V -50 40 100 125 150 ID = 11 A 30 20 TJ = 125 oC 10 TJ = 25 oC 0 4 5 IS, REVERSE DRAIN CURRENT (A) PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) 120 VDS = 5 V 80 TJ = 25 oC TJ = -55 oC 2 4 6 8 7 8 9 200 100 VGS = 0 V 10 TJ = 150 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 10 0.2 0.4 0.6 0.8 1.0 1.2 VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current ©2014 Fairchild Semiconductor Corporation FDMD8280 Rev.C 10 Figure 4. On Resistance vs Gate to Source Voltage 160 0 6 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On Resistance vs Junction Temperature TJ = 150 oC 160 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX TJ, JUNCTION TEMPERATURE (oC) 40 120 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 2.1 0.6 -75 80 ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics 1.8 VGS = 10 V 3 1.4 www.fairchildsemi.com FDMD8280 Dual N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 10000 ID = 11 A Ciss VDD = 30 V 8 1000 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 40 V 6 VDD = 50 V 4 Coss 100 10 2 0 Crss f = 1 MHz VGS = 0 V 0 6 12 18 24 30 1 0.1 36 Figure 7. Gate Charge Characteristics 10 ID, DRAIN CURRENT (A) 50 TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 40 VGS = 10 V 30 VGS = 8 V 20 Limited by Package 10 o 1 0.001 RθJC = 3.3 C/W 0.01 0.1 1 10 0 25 100 50 75 100 tAV, TIME IN AVALANCHE (ms) P(PK), PEAK TRANSIENT POWER (W) 10000 100 10 μs THIS AREA IS LIMITED BY rDS(on) 100 μs SINGLE PULSE TJ = MAX RATED RθJC = 3.3 oC/W TC = 25 oC 1 ms 10 ms DC CURVE BENT TO MEASURED DATA 1 10 100 300 TC = 25 oC 100 10 -5 10 -4 10 -3 10 -2 10 -1 10 1 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 11. Forward Bias Safe Operating Area ©2014 Fairchild Semiconductor Corporation FDMD8280 Rev.C SINGLE PULSE RθJC = 3.3 oC/W 1000 10 0.1 0.1 150 Figure 10. Maximum Continuous Drain Current vs Case Temperature 300 1 125 o Figure 9. Gate Leakage Current vs Gate to Source Voltage ID, DRAIN CURRENT (A) 80 Figure 8. Capacitance vs Drain to Source Voltage 100 IAS, AVALANCHE CURRENT (A) 1 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 12. Single Pulse Maximum Power Dissipation 4 www.fairchildsemi.com FDMD8280 Dual N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 2 DUTY CYCLE-DESCENDING ORDER 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: 0.01 ZθJC(t) = r(t) x RθJC RθJC = 3.3 oC/W Peak TJ = PDM x ZθJC(t) + TC Duty Cycle, D = t1 / t2 SINGLE PULSE 0.001 -5 10 -4 10 -3 -2 10 10 -1 10 1 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Case Transient Thermal Response Curve ©2014 Fairchild Semiconductor Corporation FDMD8280 Rev.C 5 www.fairchildsemi.com FDMD8280 Dual N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted FDMD8280 Dual N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. 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