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Super mini DIP-IPM Ver.4
APPLICATION NOTE
PS2196X-4 series
PS2196X-T series
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
Table of Contents
Table of Contents
CHAPTER 1 Super Mini DIP-IPM Ver.4 INTRODUCTION................................................................................3
1.1 Target Applications ................................................................................................................................................. 3
1.2 Product Line-up...................................................................................................................................................... 3
1.3 Functions and Features ......................................................................................................................................... 3
1.4 The differences between previous series (PS2196X-XXX) and this series (PS2196X-4,-T) .................................. 5
CHAPTER 2 SPECIFICATIONS AND CHARACTERISTICS ............................................................................6
2.1 Super Mini DIP-IPM Ver.4 Specifications ............................................................................................................... 6
2.1.1 Maximum Ratings......................................................................................................................................... 6
2.1.2 Thermal Resistance ..................................................................................................................................... 7
2.1.3 Electric Characteristics (Power Part)............................................................................................................ 7
2.1.4 Electric Characteristics (Control Part) .......................................................................................................... 8
2.1.5 Recommended Operating Conditions .......................................................................................................... 9
2.1.6 Mechanical Characteristics and Ratings ...................................................................................................... 9
2.2 Protective Functions and Operating Sequence.................................................................................................... 10
2.2.1 Short Circuit Protection .............................................................................................................................. 10
2.2.2 Control Supply UV Protection......................................................................................................................11
2.2.3 OT Protection ............................................................................................................................................. 13
2.3 Package Outlines................................................................................................................................................. 14
2.3.1 Terminal frame change from previous series (PS2196X-XXX) ................................................................... 14
2.3.2 Short Pin Type Package Outline Drawing .................................................................................................. 15
2.3.3 Long Pin Type Package Outline Drawing ................................................................................................... 16
2.3.4 Zigzag Pin Type Package Outline Drawing ................................................................................................ 17
2.3.5 N-side Open Emitter Type Package Outline Drawing................................................................................. 18
2.3.6 Both Sides Zigzag Pin Type Package Outline Drawing .............................................................................. 19
2.3.7 Laser Marking ............................................................................................................................................ 20
2.3.8 Terminal Description................................................................................................................................... 20
2.4 Mounting Method ................................................................................................................................................. 22
2.4.1 Electric Spacing.......................................................................................................................................... 22
2.4.2 Mounting Method and Precautions............................................................................................................. 22
CHAPTER 3 SYSTEM APPLICATION HIGHLIGHT....................................................................................... 23
3.1 Application Guidance ........................................................................................................................................... 23
3.1.1 System connection ..................................................................................................................................... 23
3.1.2 Interface Circuit (Direct Coupling Interface example except for type ‘-S’) .................................................. 24
3.1.3 Interface Circuit (Direct Coupling Interface Example for type ‘-S’) ............................................................. 25
3.1.4 Interface Circuit (Opto-coupler Isolated Interface)...................................................................................... 26
3.1.5 Change into internal connection between VNO and VNC terminals............................................................... 27
3.1.6 Circuits of Signal Input terminals and Fo Terminal ..................................................................................... 28
3.1.7 Snubber Circuit .......................................................................................................................................... 29
3.1.8 Recommended Wiring method around Shunt Resistor .............................................................................. 30
3.1.9 Precaution for wiring on PCB ..................................................................................................................... 31
3.1.10 SOA of Super Mini DIP-IPM Ver.4 ............................................................................................................ 32
3.1.11 Power Life Cycles..................................................................................................................................... 33
3.2 Power Loss and Thermal Dissipation Calculation ................................................................................................ 34
3.2.1 Power Loss Calculation.............................................................................................................................. 34
3.2.2 Temperature Rise Considerations and Calculation Example...................................................................... 36
3.3 Noise Withstand Capability .................................................................................................................................. 37
3.3.1 Evaluation Circuit ....................................................................................................................................... 37
3.3.2 Countermeasures and Precautions ............................................................................................................ 37
3.3.3 Static Electricity Withstand Capability......................................................................................................... 38
CHAPTER 4 KEY PARAMETERS SELECTING GUIDANCE ........................................................................ 39
4.1 Determination of Shunt Resistance...................................................................................................................... 39
4.2 Single Supply Drive Scheme................................................................................................................................ 41
4.2.1 Bootstrap Capacitor Initial Charging........................................................................................................... 41
4.2.2 Charging and Discharging of the Bootstrap Capacitor During Inverter Operation ...................................... 42
CHAPTER 5 INTERFACE DEMO BOARD..................................................................................................... 45
5.1 Super Mini DIP-IPM Ver.4 Interface Demo Board ................................................................................................ 45
5.2 Pattern Wiring ...................................................................................................................................................... 46
5.3 Circuit Schematic and Parts List .......................................................................................................................... 47
CHAPTER 6 PACKAGE HANDLING .............................................................................................................. 49
6.1 Packaging Specification ....................................................................................................................................... 49
6.2 Handling Precautions ........................................................................................................................................... 50
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Mitsubishi DIP-IPM Ver.4 Application Note
Super Mini DIP-IPM Ver.4 INTRODUCTION
CHAPTER 1
Super Mini DIP-IPM Ver.4 INTRODUCTION
1.1 Target Applications
Motor drives for household electric appliances, such as air conditioners, washing machines, refrigerators.
Low power industrial motor drives with 1500V isolation voltage except automotive applications.
1.2 Product Line-up
Table 1-1. Super Mini DIP-IPM Ver.4 Line-up
Type Name (Note 1)
IGBT Rating
PS21961-4/-4A/-4C/-4S/-4W
3A/600V
PS21962-4/-4A/-4C/-4S/-4W
5A/600V
PS21963-4E/-4AE/-4CE/-4ES/-4EW
8A/600V
PS21963-4/-4A/-4C/-4S/-4W
10A/600V
PS21964-4/-4A/-4C/-4S/-4W
15A/600V
PS21965-4/-4A/-4C/-4S/-4W
20A/600V
Motor Rating (Note 2)
0.2kW/220VAC
0.4kW/220VAC
0.75kW/220VAC
0.75kW/220VAC
0.75kW/220VAC
1.5kW/220VAC
Isolation Voltage
Viso = 1500Vrms
(Sine 60Hz, 1min
All shorted
pins-heat sink)
Table 1-2. Super Mini DIP-IPM Ver.4 Line-up with over temperature protection function type
Type Name (Note 1)
IGBT Rating
Motor Rating (Note 2)
Isolation Voltage
PS21961-T/-AT/-CT/-TW/-ST
3A/600V
0.2kW/220VAC
PS21962-T/-AT/-CT/-TW/-ST
5A/600V
0.4kW/220VAC
Viso = 1500Vrms
PS21963-ET/-AET/-CET /-ETW/-EST
8A/600V
0.75kW/220VAC
(Sine 60Hz, 1min
PS21963-T/-AT/-CT/-TW/-ST
10A/600V
0.75kW/220VAC
All shorted
pins-heat sink)
PS21964-T/-AT/-CT/-TW/-ST
15A/600V
0.75kW/220VAC
PS21965-T/-AT/-CT/-TW/-ST
20A/600V
1.5kW/220VAC
Note 1: Type name suffixed by ‘-A’ indicates the option for long pin type, ‘-C’ for zigzag pin type, ‘-S’ for N-side open
emitter type, ‘-W’ for both sides zigzag pin type and ‘-T’ with over temperature protect. Please refer to chapter
2 for details.
Note 2: The motor ratings are simulation results under following conditions: VAC=220V, VD=VDB=15V, Tc=100°C,
Tj=125°C, fPWM=5kHz, P.F=0.8, motor efficiency=0.75, current ripple ratio=1.05, motor over load 150% 1min.
1.3 Functions and Features
Super Mini DIP-IPM Ver.4 is an ultra-small compact intelligent power module with transfer mold package
favorable for larger mass production. Power chips, drive and protection circuits are integrated in the module,
which makes it easy for AC100-200V class low power motor inverter control. Fig.1-1, Fig.1-2 and Fig.1-3 show
the photograph, internal cross-section structure and the circuit block diagram respectively.
One of the most important features of Super Mini DIP-IPM Ver.4 is that it realized higher thermal dissipation
by incorporating thermal structure with high thermal conductive isolating sheet, due to which, the chip shrink
becomes possible and therefore achieved super-small package with lower temperature rise than previous
DIP-IPM Ver.3.
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Mitsubishi DIP-IPM Ver.4 Application Note
Super Mini DIP-IPM Ver.4 INTRODUCTION
Lead frame
Wire FWDi
Mold
Fig.1-1 Package photograph
IGBT
IC
Isolated thermal radiation sheet
Copper foil +Insulating resin
Fig.1-2 Internal cross-section structure
(except for PS21961)
VUFB
HVIC
VP1
VCC
VUB
UP
UP
UOUT
VNC
DIP-IPM
COM
P
IGBT1
Di1
VUS
U
VVFB
VP
VVB
VP
IGBT2
Di2
VOUT
VVS
V
VWFB
VWB
WP
WP
WOUT
VWS
LVIC
IGBT4
Di4
IGBT5
Di5
IGBT6
Di6
W
VCC
VOUT
UN
UN
VN
VN
WN
WN
WOUT
Fo
Fo
CIN
VNO
VNC
Di3
UOUT
VN1
IGBT3
GND
N
CIN
Fig.1-3 Internal circuit schematic (except for type ‘-S’)
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Super Mini DIP-IPM Ver.4 INTRODUCTION
Features:
٨ For P-side IGBTs:
-Drive circuit;
-High voltage level shift circuit;
-Control supply under voltage (UV) lockout circuit (without fault signal output).
٨ For N-side IGBTs:
-Drive circuit;
-Short circuit (SC) protection circuit (by using external shunt resistor)
-Control supply under voltage (UV) lockout circuit (with fault signal output)
-Over temperature (OT) protection (by monitoring LVIC temp). (-T series only)
٨ Fault Signal Output
-Corresponding to N-side IGBT SC protection, N-side UV protection and OT.
٨ IGBT Drive Supply
-Single DC15V power supply.
٨ Control Input Interface
-Schmitt-triggered 3V,5V input compatible, high active logic.
1.4 The differences between previous series (PS2196X-XXX) and this series (PS2196X-4,-T)
(1) Terminal frame change
The terminal frame is changed. This change intends to increase the insulation distance between terminals
with high voltage potential so as to ensure the electric space meet the Japanese PSE 䋨Product Safety of
Electric home appliance and materials䋩standard requirements of clearance and creepage distances. For
more detail, refer section 2.3.1~6 and 2.4.1.
(2) Change into internal connection between VNO and VNC terminals
In the previous series(PS2196X-XXX), the VNO terminal (17pin) needs to be connected externally to the VNC
terminal (16pin) on the PCB. But in these series, the VNO terminal is changed to connect with VNC terminal inside
the module. So, the external wiring connection becomes no more needed.
For more detail, refer section 2.3.8 and 3.1.2~5.
(3) Addition over temperature protection function (-T series only)
PS2196X-T series have over temperature (OT) protection function that the previous series (PS2196X-XXX)
didn't have. For more detail, refer section 2.2.3.
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SPECIFICATIONS AND CHARACTERISTICS
CHAPTER 2
SPECIFICATIONS AND CHARACTERISTICS
2.1 Super Mini DIP-IPM Ver.4 Specifications
The Super Mini DIP-IPM Ver.4 specifications are described below by using PS21964-4/-4A/-4C/-4W
(15A/600V) as an example. Please refer to respective datasheet for the detailed description of other types.
2.1.1 Maximum Ratings
The maximum ratings of PS21964-4/-4A/-4C/-4W are shown in Table 2-1.
Table 2-1 Maximum Ratings of PS21964-4/-4A/-4C/-4W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Item explanation:
(1) Vcc
The maximum P-N voltage in no switching state. A voltage suppressing circuit such as a brake
circuit is necessary if P-N voltage exceeds this value.
(2) Vcc(surge) The maximum P-N surge voltage in no switching state. A snubber circuit is necessary if P-N voltage
exceeds Vcc(surge).
The maximum sustained collector-emitter voltage of built-in IGBT and FWDi.
(3) VCES
The allowable DC current continuously flowing at collect electrode (Tc=25°C)
(4) +/-IC
(5) Tj
Power cycles are ensured no less than 10 millions under the condition of Tf=100°C and Tj≤125°C. The
rating value becomes low when temperature rises high.
(6) Vcc(prot) The maximum supply voltage for IGBT turning off safely in case of an SC fault. The power chip might be
damaged if supply voltage exceeds this specification.
(7) Tc position Tc (case temperature) is defined to be the temperature just underneath the specified power chip.
Please mount a thermistor in a heat sink surface at the defined position so as to get accurate
temperature information.
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SPECIFICATIONS AND CHARACTERISTICS
2.1.2 Thermal Resistance
Table 2-2 shows the thermal resistance of PS21964-4/-4A/-4C/-4W.
Table 2-2. Thermal resistance of PS21964-4/-4A/-4C/-4W㩷
The above data shows the thermal resistance between chip junction and case at steady state. The
thermal resistance goes into saturation in about 10 seconds. The thermal resistance under 10sec is called as
transient thermal impedance which is shown in Fig.2-1.
Thermal impedance Zth(j-c)*
1.00
(9 & K
FWDi
IGBT
0.10
0.01
0.1
Time (sec.)
1
Fig.2-1 Typical transient thermal impedance
10
㩷
Zth(j-c)* is the normalized value of the transient thermal impedance
Zth(j-c)*= Zth(j-c) / Rth(j-c)max
for example, the IGBT transient thermal impedance of PS21964 in 0.3sec is 3.0×0.8=2.4°C/W.
2.1.3 Electric Characteristics (Power Part)
Table 2-3 shows the typical static characteristics and switching characteristics of PS21964-4/-4A/-4C/-4W.
Table 2-3. Static characteristics and switching characteristics of PS21964-4/-4A/-4C/-4W
㩷
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SPECIFICATIONS AND CHARACTERISTICS
Switching time definition and performance test method are shown in Fig.2-2 and 2-3.
trr
VCE
Irr
P-Side IGBT
Ic
VP1
L
90%
90%
VB
VCIN(P)
IN
COM
OUT
VS
A
P-Side Input Signal
10%
10%
VCC
10%
B
tc(off)
tc(on)
VCIN
td(on)
10%
㪭㪛㩷
VCIN(N)
tr
( ton=td(on)+tr )
td(off)
tf
( toff=td(off)+tr )
VN1
OUT
IN
VNC
VNO
CIN
L
㪥㪄㪪㫀㪻㪼㩷IGBT㩷
N-Side Input Signal
Fig.2-2 Switching time definition
Fig.2-3 Evaluation circuit (inductive load)
Short A for N-side IGBT, and short B for P-side IGBT evaluation
Turn on
Turn off
Fig.2-4 Typical switching waveform (PS21964-4)
Conditions : VCC=300V, VD=VDB=15V, Tj=125°C, Ic=15A, Inductive load half-bridge circuit
2.1.4 Electric Characteristics (Control Part)
Table 2-4 Control (Protection) characteristics of PS21964-4/-4A/-4C/-4W
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SPECIFICATIONS AND CHARACTERISTICS
2.1.5 Recommended Operating Conditions
The recommended operating conditions of PS21964-4/-4A/-4C/-4W are given in Table 2-5.
Although these conditions are the recommended but not the necessary ones, it is highly recommended to
operate the modules within these conditions so as to ensure DIP-IPM safe operation.
Table 2-5
Recommended operating conditions of PS21964-4/-4A/-4C/-4W
2.1.6 Mechanical Characteristics and Ratings
The mechanical characteristics and ratings are shown in Table 2-6
Please refer to Section 2.4 for the detailed mounting instruction of Super Mini DIP-IPM Ver.4.
Table 2-6
Mechanical characteristics and ratings of PS21964-4/-4A/-4C/-4W
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SPECIFICATIONS AND CHARACTERISTICS
2.2 Protective Functions and Operating Sequence
There are SC protection, UV protection and OT protection (-T only) in the Super Mini DIP-IPM Ver.4. The
operating principle and sequence are described below.
2.2.1 Short Circuit Protection
Super Mini DIP-IPM Ver.4 uses external shunt resistor for the current detection as shown in Fig.2-4. The
internal protection circuit inside the IC captures the excessive large current by comparing the CIN voltage
feedback from the shunt with the referenced SC trip voltage, and perform protection automatically. The threshold
voltage trip level of the SC protection is 0.48V(typ.), according to which the shunt resistance should be correctly
selected.
In case of SC protection happens, all the gates of N-side three phase IGBTs will be interrupted together with
a fault signal output.
To prevent DIP-IPM erroneous protection due to normal switching noise and/or recovery current, it is
necessary to set an RC filter(time constant: 1.5μ ~ 2μs) to the CIN terminal input (Fig.2-4, 2-5). Also, please
make the pattern wiring around the shunt resistor as short as possible.
DIP-IPM
Drive circuit
P
H-side IGBTs
U
V
W
L-side IGBTs
SC Protection External Parts
N1
Shunt resistor
C
Collect current
Ic (A)
SC protective level
N
VNC
R
Collector current
waveform
Drive circuit
CIN
0
2
SC protection
Fig.2-4
SC protecting circuit
Input pulse width tw (μs)
㩷
Fig.2-5 Filter time constant setting
SC protection (Lower-side only with the external shunt resistor and RC filter)
a1. Normal operation: IGBT ON and carrying current.
a2. Short circuit detection (SC trigger).
a3. IGBT gate hard interruption.
a4. IGBT turns OFF.
a5. Fo outputs (tFO(min)=20μs).
a6. Input = “L”. IGBT OFF.
a7. Input = “H”.
a8. IGBT OFF in spite of “H” input.㩷
㩷
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SPECIFICATIONS AND CHARACTERISTICS
N-side control input
a6
Protection circuit state
a7
SET
RESET
a3
Internal IGBT gate
a2
SC
a4
a1
a8
Output current Ic(A)
SC reference voltage
Sense voltage of the
Shunt resistor
CR circuit time constant delay
Fault output (Fo)
a5
Fig.2-6
SC protection timing chart
2.2.2 Control Supply UV Protection
The UV protection is designed to prevent unexpected operating behavior as described in Table 2-7.
Both P-side and N-side have UV protecting function. However, fault signal (Fo) output only corresponds to
N-side UV protection. Fo output continuously during UV state.
In addition, there is a noise filter (typ. 10μs) integrated in the UV protection circuit to prevent instantaneous
UV erroneous trip. Therefore, the control signals are still transferred in the initial 10μs after UV happened.
Table 2-7 DIP-IPM operating behavior versus control supply voltage
Control supply voltage
Operating behavior
Equivalent to zero power supply.
UV function is inactive, no Fo output.
0-4.0V (P, N)
Normally IGBT does not work. But, external noise may cause
DIP-IPM malfunction (turns ON), so DC-link voltage need to turn on
after control supply turning on.
UV function become active and output Fo (N-side only).
4.0-12.5V (P, N)
Even if control signals are applied, IGBT does not work
IGBT can work. However, conducting loss and switching loss will
12.5-13.5V (P, N)
increase, and result extra temperature rise at this state,.
13.5-16.5V (N), 13.0-18.5V (P)
Recommended conditions.
IGBT works. However, switching speed becomes fast and saturation
16.5-20.0V (N),18.5-20.0V (P)
current becomes large at this state, increasing SC broken risk.
20.0V- (P, N)
The control circuit will be destroyed.
Ripple Voltage Limitation of Control Supply
If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause
DIP-IPM erroneous operation. To avoid such problem happens, line ripple voltage should meet the following
specifications:
dV/dt ≤ +/-1V/μs, Vripple≤2Vp-p
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SPECIFICATIONS AND CHARACTERISTICS
㩷
N-side UV Protection Sequence
a1. Control supply voltage rising: After the voltage level reaches UVDr, the circuits start to operate when
next input is applied.
a2. Normal operation : IGBT ON and carrying current.
a3. Under voltage trip (UVDt).
a4. IGBT OFF in spite of control input condition.
a5. Fo outputs(tFO ≥20μs and Fo outputs continuously during UV period.)
a6. Under voltage reset (UVDr).
a7. Normal operation : IGBT ON and carrying current.
㩷
Control input
Protection circuit state
㪩㪜㪪㪜㪫㩷
Control supply voltage VD
a1
㪪㪜㪫㩷
㪬㪭㪛㩷㫋㩷
㪩㪜㪪㪜㪫㩷
a6
UVD r
a3
a2
a4
a7
Output current Ic(A)
Keeping high-level output
a5
Fault output (Fo)
㩷
Fig.2-7 Timing chart of N-side UV protection
P-side UV Protection Sequence
a1. Control supply voltage rising : After the voltage reaches UVDBr, the circuits start to operate when
next input is applied.
a2. Normal operation : IGBT ON and carrying current.
a3. Under voltage trip (UVDBt).
a4. IGBT OFF in spite of control input condition, but there is no Fo signal outputs.
a5. Under voltage reset (UVDBr).
a6. Normal operation : IGBT ON and carrying current.㩷
㩷
Control input
Protection circuit state
Control supply voltage VDB
㪩㪜㪪㪜㪫㩷
㪪㪜㪫㩷
a1
㪬㪭㪛㪙㩷㫋㩷
a2
㪩㪜㪪㪜㪫㩷
a5
UVDB r
a3
a4
a6
Output current Ic(A)
Keeping high-level output (No Fo output)
Fault output (Fo)
㩷
Fig.2-8 Timing Chart of P-side UV protection
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SPECIFICATIONS AND CHARACTERISTICS
2.2.3 OT Protection
PS2196X-T series have OT (over temperature) protection function by monitoring LVIC temperature rise.
While LVIC temp go over and keeps over OT trip temperature, error signal Fo outputs and all N-side IGBTs are shut
down without reference to input signal. (P-side IGBTs are not shut down)
The specification of OT trip temp.and its sequence are described in Table 2-8 and Fig.2-9.
Table 2-8 OT trip temp. specification
Item
Over temperature
protection (Note5)
Symbol
OTt
OTrh
Condition
Trip level
VD=15V,
At temperature of LVIC
Trip/reset hysteresis
Min.
100
-
Typ.
120
10
Max.
140
-
Unit
°C
OT Protection Sequence
a1. Normal operation : IGBT ON and carrying current
a2. LVIC temperature exceeds over temperature trip level(OTt).
a3. IGBT OFF in spite of control input condition.
a4. Fo outputs during over temperature period, however, the minimum pulse width is 20μs.
a5. LVIC temperature becomes under over temperature reset level.
a6. Circuits start to operate normally when next input is applied.
Control input
Protection circuit state
SET
RESET
OTt
LVIC temperature
RESET
a2
a5
OTrh
a1
a3
a6
Output current Ic
a4
Fault output Fo
Fig.2-9 Timing Chart of OT protection
Precaution about this OT protection function
(1)This OT protection will not work effectively in the case of rapid temperature rise like motor lock or over
current . (This protection monitors LVIC temperature, so it cannot respond to rapid temperature rise of
power chips.)
(2)If the cooling system is abnormal state (e.g. heat sink comes off, fixed loosely, or cooling fun stops)
when OT protection works, can't reuse the DIP-IPM . (Because the junction temperature of power chips
will exceeded the maximum rating of Tj(150°C).)
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SPECIFICATIONS AND CHARACTERISTICS
2.3 Package Outlines
Super Mini DIP-IPM Ver.4 packages are developed with 5 types terminal shapes optional for different
mounting requirement. There are short pin type (standard type), long pin type, control pin zigzag type, N-side
IGBT open emitter type and both sides zigzag type with same size package.
2.3.1 Terminal frame change from previous series (PS2196X-XXX)
The terminal frame is changed to the shape shown in Fig.2-10. This change intends to increase the insulation
distance between terminals with high voltage potential so as to ensure the electric space meet the Japanese PSE
䋨Product Safety of Electric home appliance and materials䋩 standard requirements of 2.5mm(min) for clearance
and 3.0mm(min.) for creepage distance. Table 2-9 shows the location of the changes in terminal frame, and Table
2-10 shows a comparison of the insulation distance before and after change. However, there is no change in the
pin assignment and pin pitch.
Table 2-9 Location of the change in terminal frame for Super Mini DIP-IPM Ver.4
Changed location
Changed pins
(a)
Root shape of stopper terminal
Pin number 2, 3, 17, 18, 25
(b)
Space between roots of power terminals
Between pins of 21-22, 22-23 and 23-24
Table 2-10 Insulation distance between each pair terminals of Super Mini DIP-IPM Ver.4
Clearance distance
Creepage distance
Previous
New
Previous
Between control terminals with high potential
2.256mm(typ) 2.5mm(min)
(Between pins of 2-3,3-4,4-5)
Between power terminals
2.88mm(min)
(Between pins of 21-22, 22-23, 23-24)
The insulation distances except for stated above already meet the PSE standard.
Change(a)
↓
New
3.0mm(min)
Change(a)
↓
A
Change(b)
↑
Change(a)
B
↑
Change(a)
[Previous : PS2196X-XXX]
[After change: PS2196X-4,-T]
Detail A㧔Change for clearance㧕
[Previous : PS2196X-XXX]
[After change: PS2196X-4,-T]
Detail B (Change for creepage)
Fig.2-10 Locations of the change in the terminal frame shape
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SPECIFICATIONS AND CHARACTERISTICS
(Note: Connect only one VNC terminal to the system GND and leave another one open)
2.3.2 Short Pin Type Package Outline Drawing
㩷
Fig.2-11 Short pin type package(-4/-T) outline drawing
QR code® is a registered trademark of DENSO WAVE INCORPORATED in JAPAN and other countries.㩷
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SPECIFICATIONS AND CHARACTERISTICS
(Note: Connect only one VNC terminal to the system GND and leave another one open)
2.3.3 Long Pin Type Package Outline Drawing
Fig.2-12 Long pin type package(-4A/-AT) outline drawing
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SPECIFICATIONS AND CHARACTERISTICS
(Note: Connect only one VNC terminal to the system GND and leave another one open)
2.3.4 Zigzag Pin Type Package Outline Drawing
㩷
Fig.2-13
Zigzag pin type package(-4C/-CT) outline drawing
17
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SPECIFICATIONS AND CHARACTERISTICS
(Note: Connect only one VNC terminal to the system GND and leave another one open)
2.3.5 N-side Open Emitter Type Package Outline Drawing
Fig.2-14 N-side open emitter type package(-4S/-ST) outline drawing
18
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SPECIFICATIONS AND CHARACTERISTICS
(Note: Connect only one VNC terminal to the system GND and leave another one open)
2.3.6 Both Sides Zigzag Pin Type Package Outline Drawing
Fig.2-15 Both sides zigzag pin type package(-4W/-TW) outline drawing
19
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SPECIFICATIONS AND CHARACTERISTICS
2.3.7 Laser Marking
The laser marking specification of Super Mini DIP-IPM Ver.4 is described in Fig.2-16. Mitsubishi Corporation
mark, Type name, Lot number, and QR code mark are marked in the upper side of module.
Marking area
Marking details (S=3/1)
QR code area
Fig.2-16 Laser marking view
2.3.8 Terminal Description
Table 2-11 Terminal description
Except for –S type
PS2196X-4S or -ST
Name
Description
Name
Description
1
NC
No connection
NC
Same in the left
2
VUFB
U-phase P-side drive supply positive terminal
VUFB
Same in the left
3
VVFB
V-phase P-side drive supply positive terminal
VVFB
Same in the left
4
VWFB
W-phase P-side drive supply positive terminal
VWFB
Same in the left
5
UP
U-phase P-side control input terminal
UP
Same in the left
6
VP
V-phase P-side control input terminal
VP
Same in the left
7
WP
W-phase P-side control input terminal
WP
Same in the left
8
VP1
P-side control supply positive terminal
VP1
Same in the left
9
VNC*1
P-side control supply GND terminal
VNC*1
Same in the left
10
UN
U-phase N-side control input terminal
UN
Same in the left
11
VN
V-phase N-side control input terminal
VN
Same in the left
12
WN
W-phase N-side control input terminal
WN
Same in the left
13
VN1
N-side control supply positive terminal
VN1
Same in the left
14
FO
Fault signal output terminal
FO
Same in the left
15
CIN
SC trip voltage detecting terminal
CIN
Same in the left
16
VNC*1
N-side control supply GND terminal
VNC*1
Same in the left
2
17
NC*
No connection
NC*2
Same in the left
18
NC
No connection
NW
WN-phase IGBT emitter
19
NC
No connection
NV
VN-phase IGBT emitter
20
N
Inverter DC-link negative terminal
NU
UN-phase IGBT emitter
21
W
W-phase output terminal(W-phase drive supply GND)
W
Same in the left
22
V
V-phase output terminal (V-phase drive supply GND)
V
Same in the left
23
U
U-phase output terminal (U-phase drive supply GND)
U
Same in the left
24
P
Inverter DC-link positive terminal
P
Same in the left
25
NC
No connection
NC
Same in the left
*1) Connect only one VNC terminal to the system GND and leave another one open.
*2) In the previous series, the VNO terminal (17pin) needs to be connected externally to the VNC terminal (16pin) on the
PCB. But in this series, the VNO terminal is changed to connect with VNC terminal inside the module.
So, the external wiring connection becomes no more needed. Furthermore, because there is no electric connection
of this terminal (17pin) to other circuit inside the module, If the PCB which the 17pin is connected to 16pin(VNC) is
used, there is no any problem.
Pin
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Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SPECIFICATIONS AND CHARACTERISTICS
Detailed description of input and output terminals㩷
Symbol
Description
• Drive supply terminals for P-side IGBTs.
• By virtue of applying the bootstrap circuit scheme, individual isolated power
supplies are not needed for the DIP-IPM P-side IGBT drive. Each bootstrap
P-side drive supply
capacitor is charged by the N-side VD supply during ON-state of the
VUFB-U
positive terminal
corresponding N-side IGBT in the loop.
VVFB-V
• Abnormal operation might happen if the VD supply is not aptly stabilized or
VWFB-W
has insufficient current capability. In order to prevent malfunction caused by
P-side drive supply
such unstability as well as noise and ripple in supply voltage, a bypass
GND terminal
capacitor with favorable frequency and temperature characteristics should
be mounted very closely to each pair of these terminals.
• Inserting a Zener diode (24V/1W) between each pair of control supply
Note 1
terminals is helpful to prevent control IC from surge destruction.
• Control supply terminals for the built-in HVIC and LVIC.
P-side control
• In order to prevent malfunction caused by noise and ripple in the supply
supply terminal
voltage, a bypass capacitor with favorable frequency characteristics should
VP1
VN1
be mounted very closely to these terminals.
• Carefully design the supply so that the voltage ripple caused by noise or by
N-side control
system operation is within the specified minimum limitation.
• It is recommended to insert a Zener diode (24V/1W) between each pair of
supply terminal
Note 1
control supply terminals to prevent surge destruction.
• Control ground terminal for the built-in HVIC and LVIC.
VNC
N-side control
• Ensure that line current of the power circuit does not flow through this
GND terminal
Note 2
terminal in order to avoid noise influences.
• Control signal input terminals.
• Voltage input type. These terminals are internally connected to Schmitt
UP,VP,WP
trigger circuit.
Control input
• The wiring of each input should be as short as possible to protect the
terminal
UN,VN,WN
DIP-IPM from noise interference.
• Use RC coupling in case of signal oscillation.
• Current sensing resistor should be connected between this terminal and VNC
Short-circuit trip
to detect short-circuit accidents (short-circuit voltage trip level). Input
voltage detecting
CIN
impedance for CIN terminal is approximately 600kΩ.
terminal
• RC filter should be connected for noise immunity.
• Fault signal output terminal.
Fault signal output
• This output is open drain type. FO signal line should be pulled up to a 5V
FO
terminal
logic supply with approximately 10kΩ resistor.
• DC-link positive power supply terminal.
P
• Internally connected to the collectors of all P-side IGBTs.
Inverter DC-link
• To suppress surge voltage caused by DC-link wiring or PCB pattern
positive terminal
inductance, smoothing capacitor should be inserted very closely to the P
and N terminal. It is also effective to add small film capacitor with good
Note 1
frequency characteristics.
• DC-link negative power supply terminal (power ground) of the inverter.
N
(Except Type ‘-S’) • This terminal is connected internally to the emitters of all N-side IGBTs.
Inverter DC-link
• Open emitter terminal of each N-side IGBT
negative terminal NU,NV,NW
• Usually, these terminals are connected to the power GND through individual
(for Type ‘-S’)
shunt resistor.
• Inverter output terminals for connection to inverter load (e.g. AC motor).
Inverter power
• Each terminal is internally connected to the intermidiate point of the
U, V, W
output terminal
corresponding IGBT half bridge arm.
Table 2-12
Item
Note: 1) Use oscilloscope to check voltage waveform of each power supply terminals and P&N terminals, the time division of OSC
should be set to about 1μs/div. Please ensure the voltage (including surge) not exceed the specified limitation.
2) Connect only one VNC terminal to the system GND, and leave another one open.
21
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SPECIFICATIONS AND CHARACTERISTICS
2.4 Mounting Method
This section shows the electric spacing and mounting precautions of Super Mini DIP-IPM Ver.4.
2.4.1 Electric Spacing
The electric spacing specification of Super Mini DIP-IPM Ver.4 is shown in Table 2-13
Table 2-13
Minimum insulation distance of Super Mini DIP-IPM Ver.4
Clearance (mm)
Creepage (mm)
Between live terminals with high potential
2.50
3.00
Between terminals and heat sink
1.45
1.50
2.4.2 Mounting Method and Precautions
When installing a module to a heat sink, excessive uneven fastening force might apply stress to inside chips,
which will lead to a broken or degradation of the device. An example of recommended fastening order is shown
in Fig.2-17
Temporary fastening
1o2
Permanent fastening
1o2
Fig.2-17
Recommended screw fastening order
Note: Generally, the temporary fastening torque is set to 20-30% of the maximum torque rating.
Table 2-14. Mounting torque and heat sink flatness specifications
Item
Condition
Mounting torque
Recommended 0.69N·m, Screw : M3
Heat radiation side of DIP-IPM package and
Flatness of heat
External heat sink
radiation part
Refer Fig.2-18
Min.
0.59
Typ.
-
Max.
0.78
Unit
N·m
-50
-
+100
Pm
Note : Recommend to use plain washer (ISO7089-7094) in fastening the screws.
External heat sink
Grease applying surface
DIP-IPM
Measurem ent position
㧗㧙
17.5mm
4.6mm
+
-
Edge of package
DIP-IPM
Heat sink flatness area
㧙
㧗
External heat sink
[External heat sink]
Fig.2-18 Measurement point of heat sink flatness
In order to get effective heat dissipation, it is necessary to enlarge the contact area as much as possible to
minimize the contact thermal resistance. Regarding the heat sink flatness (warp/concavity and convexity) on the
module installation surface (refer to Fig.2-18), the surface finishing-treatment should be within Rz12.
Evenly apply thermally-conductive grease with 100P-200Pm thickness over the contact surface between a
module and a heat sink, which is also useful for preventing corrosion. Furthermore, the grease should be with
stable quality and long-term endurance within wide operating temperature range. Use a torque wrench to fasten
up to the specified torque rating. Exceeding the maximum torque limitation might cause a module damage or
degrade. Also, pay attention not to have any desert remaining on the contact surface between the module and
the heat sink.
22
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
CHAPTER 3
SYSTEM APPLICATION HIGHLIGHT
3.1 Application Guidance
This chapter states the Super Mini DIP-IPM Ver.4 application method and interface circuit design hints.
3.1.1 System connection
CBW+
CBWCBV+
CBVCBU+
CBU-
P-side input(PWM) (3V,5V) Note 1),2)
C2
C1
C1: Electrolytic type with good temperature and frequency characteristics
Note: the capacitance also depends on the PWM control
strategy of the application system
C2:0.22P-2PF ceramic capacitor with good temperature, frequency and DC
bias characteristics.
Input signal
conditioning
Input signal
conditioning
Input signal
conditioning
Level shift
Level shift
Level shift
Drive circuit
Drive circuit
Note 7)
Note 5)
UV lockout
circuit
Drive circuit
Inrush limiting circuit
DIP-IPM
P
P-side IGBTs
AC line input
U
V
W
Note 4)
M
Note 8)
Z
C
N1
N
N-side IGBTs
Note 6) VNC
Z : Surge absorber
C : AC filter(ceramic capacitor 2.2n -6.5nF)
(common-mode noise filter)
CIN
Drive circuit
Input signal conditioning
Fo Logic
Protection
circuit (SC)
UV lockout
circuit
Note 7)
Fo
N-side input(PWM)
(3V,5V) Note 1),2)
Fig.3-1
AC output
Fo output(5V line)
Note 3)
VNC
(15V line)
VD
㩷
㩷
Application System block diagram of Super Mini DIP-IPM Ver.4 (except for type ‘-S’)
Note 1) Input signal is high active logic. A 3.3k:(min.) pull down resistor is built-in each input circuit. If
external RC filter is used for noise immunity, pay attention to the variation of the input signal
level.
Note 2) By virtue of integrating HVIC inside the module, direct coupling to MCU/DSP without any
opto-coupler or transformer for electric isolation is possible.
Note 3) Fo output is open drain type. This signal line should be pulled up to the positive side of a 5V
supply with an approximate 10k: resistor.
Note 4) The wiring between the power DC-link capacitor and the P/N1 terminals should be as short as
possible to protect DIP-IPM against catastrophic high surge voltage. For extra precaution, a
small film type snubber capacitor (0.1P~0.22PF, high voltage type) is recommended to mount
closely to the P and N1 terminals.
Note 5) Use high-voltage (over 600V) and high-speed recovery diode for the bootstrap circuit.
Note 6) To prevent HVIC from surge destruction, it is recommended to insert a Zener diode (24V, 1W)
between each control supply terminals.
Note 7) To prevent unexpected floating potential variation generated by extra wiring inductance and
motor current, the negative electrodes of bootstrap supplies should be connected directly to
DIP-IPM U, V, W terminals and separated from the main inverter output wires.
23
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
3.1.2 Interface Circuit (Direct Coupling Interface example except for type ‘-S’)
Fig.3-2 shows a typical application circuit of interface schematic, in which control signals are transfered
directly from a controller (MCU or DSP).
C2 C1
C2 C1
Bootstrap negative electrodes
should be connected to U,V,W
terminals directly and separated
from the main output wires
DIP-IPM
VWFB
VVFB
VUFB
C2 C1
P
HVIC
VP1
C3
UP
VCC
VUB
UP
UOUT
U
VUS
VVB
VP
VP
VOUT
V
M
VVS
VWB
WP
MCU
VNC
WP
COM
W OUT
W
VWS
LVIC
UOUT
VN1
5V line
VCC
C3
VOUT
UN
VN
WN
Fo
UN
VN
WN
Fo
Long wiring here might cause short
circuit failure
W OUT
CIN
N
VNO
VNC
GND
C
CIN
B
15V line
C4
R1
Shunt resistor
A
N1
Long wiring here might cause SC level
fluctuation and malfunction.
Long GND wiring here might generate noise
to input and cause IGBT malfunction.
Fig.3-2 Interface circuit example except for type ‘-S’
Note:
(1) Input drive is High-Active type. There is a 3.3k:(min.) pull-down resistor integrated in the IC input circuit. To prevent malfunction, the wiring of
each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on and turn-off
threshold voltage.
(2) Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible.
(3) Fo output is open drain type. It should be pulled up to the positive side of a 5V power supply by a resistor of about 10k:.
(4) To prevent erroneous protection, the wiring of A, B, C should be as short as possible.
(5) The time constant R1C4 of the protection circuit should be selected in the range of 1.5P~2Ps. SC interrupting time might vary due to the
wiring pattern. Tight tolerance, temp-compensated type is recommended for R1,C4
(6) All capacitors should be mounted as close to the terminals of the DIP-IPM as possible. (C1: good temperature, frequency characteristic
electrolytic type, and C2, C3 : good temperature, frequency and DC bias characteristic ceramic type are recommended.)
(7) To prevent surge destruction, the wiring between the smoothing capacitor and the P,N1 terminals should be as short as possible. Generally a
0.1P~0.22PF snubber between the P-N1 terminals is recommended.
(8) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
(9) It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
(10) If control GND is connected to power GND by broad pattern, it may cause malfunction by power GND fluctuation. It is recommended to
connect control GND and power GND at only a point.
24
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
3.1.3 Interface Circuit (Direct Coupling Interface Example for type ‘-S’)
C1:Electrolytic capacitor with good temperature characteristics C2,C3:0.22μ-2μF R-category ceramic capacitor for noise filtering
C2 C1
C2 C1
C2 C1
Bootstrap negative
electrodes should be
connected to U,V,W
terminals directly and
separated from the main
output wires
VVFB
VUFB
DIP-IPM
VWFB
P
HVIC
VP1
VCC
VUB
UP
UOUT
C3
UP
U
VUS
VVB
VP
VP
VOUT
V
VVS
M
VWB
WP
VNC
WP
W
COM
VWS
LVIC
MCU
WOUT
UOUT
VN1
5Vline
NU
VCC
C3
VOUT
UN
NV
UN
VN
VN
WN
Fo
WN
WOUT
Fo
CIN
NW
VNO
VNC
Long wiring here might cause short
circuit failure
GND
C
CIN
15Vline
Long wiring here might cause SC
level fluctuation and malfunction.
Long GND wiring here might
generate noise to input and cause
IGBT malfunction.
Shunt resistors
A
B R1
+
Note 1: Please set the filter time constant R1C4 for
comparator input such that the IGBT can be shutdown
within 2μsec. The wiring pattern may affect the
shutdown time.
Note 2: Please set the threshold voltage of the comparator
reference input to be same as DIP-IPM SC trip
reference voltage (0.48V typ)
Note 3: Please set the shunt resistance such that the
shutdown SC level is under 1.7 times current rating.
Note 4: Refer the previous page for other notations.
Fig.3-3
-
Vref
B R1
+
OR Logic
C4
Vref
B R1
+
-
N1
C4
Vref
Comparator
C4
External protection circuit
Interface circuit example for type ‘-S’
25
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
3.1.4 Interface Circuit (Opto-coupler Isolated Interface)
C2 C1 C2 C1
VVFB
VUFB
C2 C1
DIP-IPM
VWFB
Bootstrap negative electrodes
should be connected to U, V, W
terminals directly and separated
form the main output wires.
P
HVIC
VP1
5V line
C3
UP
VCC
VUB
UP
UOUT
U
VUS
VVB
VP
VP
VOUT
V
VVS
M
VWB
WP
MCU
VNC
WP
COM
WOUT
W
VWS
LVIC
UOUT
VN1
C3
VCC
VOUT
UN
VN
WN
Fo
UN
VN
WN
WOUT
Fo
CIN
Long wiring here might cause short
circuit failure
N
VNO
VNC
GND
C
CIN
B
15V line
R1
C4
Shunt resistor
A
N1
Long GND wiring here might cause GND level
variation leading to noise interference to input
signals
Long wiring here might generate extra voltage
leading to SC malfunction
Fig.3-4 Interface circuit example except for type ‘-S’
Note 1: High speed (high CMR) opto-coupler is recommended;
2: Fo terminal sink current is 1mA. A buffer circuit is necessary to drive an opto-coupler.
26
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
3.1.5 Change into internal connection between VNO and VNC terminals
In the previous series, the VNO terminal (17pin) needs to be connected externally to the VNC terminal (16pin) on
the PCB(Fig.3-5). But in this series, the VNO terminal is changed to connect with VNC terminal inside the module.
(Fig.3-6) So, the external wiring connection becomes no more needed. Furthermore, because there is no
electric connection of this terminal (17pin) to other circuit inside the module, If the PCB which the 17pin is
connected to 16pin(VNC) is used, there is no any problem.
㩷
LVIC
UOUT
VN1
5V line
VCC
C3
VOUT
UN
UN
VN
VN
WN
Fo
WN
WOUT
Fo
CIN
N
VNO
VNC
GND
VNO
CIN
DIP-IPM
R1
15V line
C4
Shunt resistor
N1
㩷
Fig.3-5 Previous series (PS2196X-XXX)
LVIC
UOUT
VN1
5V line
C3
VCC
VOUT
UN
VN
WN
Fo
UN
VN
WN
WOUT
Fo
CIN
N
VNO
VNC
GND
NC
CIN
DIP-IPM
R1
15V line
C4
Shunt resistor
N1
Fig.3-6 These series (PS2196X-4/-T)
27
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
3.1.6 Circuits of Signal Input terminals and Fo Terminal
(1) Internal Circuit of Control Input Terminals
Super Mini DIP-IPM Ver.4 series adopt High-Active input logic which released the sequence restriction
between the control supply and the input
DIP-IPM
signal in start-up or shut down operation,
1kΩ
therefore, make the system fail-safe.
Level Shift
Gate Drive
UP,VP,W P
Circuit
Circuit
In addition, a 3.3kΩ(min) pull-down
resistor is built-in each input circuit of the
3.3kΩ (min)
DIP-IPM as shown in Fig.3-7, hence,
external pull-down resistor is not needed.
1kΩ
Gate Drive
Furthermore, by lowering the turn on
UN,VN,W N
Circuit
and turn off threshold value of input
3.3kΩ (min)
signal as shown in Table 3-1, a direct
coupling to 3V-class microcomputer or
DSP becomes possible.
Fig.3-7. Internal structure of control input terminals
Table 3-1. Input threshold voltage ratings(Tj=25°C)
Item
Symbol
Condition
Turn-on threshold voltage
Vth(on)
UP,VP,WP-VNC terminals
Turn-off threshold voltage
Vth(off)
UN,VN,WN-VNC terminals
Threshold voltage hysterisis
Vth(hys)
Min.
0.8
0.35
Typ.
2.1
1.3
0.65
Max.
2.6
-
Unit
V
Note:There are limits for the minimum input pulse width in Super Mini DIP-IPM Ver.4. DIP-IPM might make no
response or not work normally if the input signal pulse width (both on and off) is less than the limited value.
Please refer to the datasheet for the specification.
5V line
10kΩ
DIP-IPM
UP,VP,W P,UN,VN,WN
MCU/DSP
Fo
3.3kΩ (min)
VNC(Logic)
Fig.3-8 Control input connection
Note: The RC coupling (parts shown in the dotted line) at each input depends on user’s PWM control strategy and the wiring
impedance of the printed circuit board.
The DIP-IPM signal input section integrates a 3.3kΩ(min) pull-down resistor. Therefore, when using an external
filtering resistor, please pay attention to the signal voltage drop at input terminal.
(2) Internal Circuit of Fo Terminal
FO terminal is an open drain type, it should be pulled up to a 5V supply as shown in Fig.3-8. Fig.3-9 shows
the typical V-I characteristics of Fo terminal. The maximum sink current of Fo terminal is 1mA. If opto-coupler is
applied to this output, please pay attention to the opto-coupler drive ability.
Table 3-2 Electric characteristics of Fo terminal
Item
Symbol
Condition
VSC=0V,Fo=10kΩ,5V pulled-up
VFOH
Fault output voltage
VSC=1V,Fo=1mA
VFOL
28
Min.
4.9
-
Typ.
-
Max.
0.95
Unit
V
V
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
1.0
0.9
0.8
VFO(V)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0
0.2
0.4
0.6
0.8
1.0
IFO(mA)
Fig.3-9
Fo terminal typical V-I characteristics (VD=15V, Tj=25°C)
3.1.7 Snubber Circuit
In order to prevent DIP-IPM from extra surge destruction, the wiring length between the smoothing capacitor
and DIP-IPM P-N terminals should be as short as possible. Also, a 0.1μ~0.22μF/630V snubber capacitor should
be mounted in the DC-link close to DIP-IPM.
There are two positions ( (1)or(2) ) to mount a snubber capacitor as shown in Fig.3-10. Snubber capacitor
should be installed in the position (2) so as to suppress surge voltage effectively. However, the charging and
discharging currents generated by the wiring inductance and the snubber capacity will flow through the shunt
resistor, which might cause erroneous protection if this current is large enough.
In order to suppress the surge voltage maximally, the wiring at part-A should be as short as possible when
mounting a snubber capacitor outside the shunt resistor as shown in position (1). A better wiring example is
shown in location (3).㩷
DIP-IPM
Wiring Inductance
P
+
㩿㪈㪀㩷
㩿㪉㪀㩷
㩿㪊㪀㩷
-
A
N
Shunt resistor
㩷
Fig.3-10 Recommended snubber circuit location
29
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
3.1.8 Recommended Wiring method around Shunt Resistor
External shunt resistor is employed to detect short-circuit accident. A longer wiring between the shunt
resistor and DIP-IPM might cause so much large surge that might damage built-in IC. To decrease the pattern
inductance, the wiring between the shunt and DIP-IPM should be as short as possible, and using low inductance
type resistor such as SMT resistor instead of long-lead type resistor.
㩷
DIP-IPM
Wiring Inductance should be less than 10nH.
Equivalent to the inductance of a cooper
pattern in dimension of width=3mm,
thickness=100μm, length=17mm
VNC
N
Shunt resistor
Please make the GND wiring connection of
shunt resistor to the VNC terminal as close as
possible.
㩷
(a) Wiring instruction (except for type ‘-S’)
㩷
㪛㪠㪧㪄㪠㪧㪤㩷
Each wiring inductance should be less than 10nH
Equivalent to the inductance of a cooper
pattern in dimension of width=3mm,
thickness=100μm, length=17mm
㪥㪬㩷
㪥㪭㩷
㪭㪥㪚㩷
㪥㪮㩷
Please make the GND wiring connection of
shunt resistor to the VNC terminal as close as
possible.
㪪㪿㫌㫅㫋㩷㫉㪼㫊㫀㫊㫋㫆㫉㫊㩷
㩷
(b) Wiring instruction for type ‘-S’㩷
Fig.3-11
Recommended wiring method of shunt resistor
Influence of pattern wiring around the shunt resistor is shown below.
㩷
Drive circuit
DIP-IPM
P
H-side IGBTs
U
V
W
SC protection External Parts
DC-bus current route
L-side IGBTs
B
N
A
㪚㩷
Drive circuit
R2
CIN
C1
Shunt resistor
SC protection
VNC
Fig.3-12
D
N1
External protection circuit㩷
30
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
(1) Influence of the part-A wiring
The ground of Low-side IGBT gate is VNC. If part-A wiring pattern in Fig.3-12 is too long, extra voltage
generated by the wiring parasitic inductor will result the potential of IGBT emitter variation during switching
operation. Please install shunt resistor as close to the N terminal as possible.
(2) Influence of the part-B wiring
The part-B wiring affects SC protection level. SC protection works by judging the voltage of the CIN
terminals. If part-B wiring is too long, extra surge voltage generated by the wiring inductance will lead to
deterioration of SC protection level. Please connect CIN and VNC terminals directly to the two ends of shunt
resistor and avoid superfluous wiring.
(3) Influence of the part-C wiring pattern
C1R2 filter is added to remove noise influence occurring on shunt resistor. Filter effect will dropdown and
noise will easily superimpose on the wiring if part-C wiring is too long. Please install the C1R2 filter near CIN, VNC
terminals as close as possible.
(4) Influence of the part-D wiring pattern
Part-D wiring pattern gives influence to all the items described above, maximally shorten the GND wiring is
expected.
3.1.9 Precaution for wiring on PCB
These wire potentials fluctuate between Vcc and GND potential at
switching, so it may cause malfunction if wires for control (e.g. control input
Vin, control supply) are located near by or cross these wires.
It is recommended to locate wires for control as far from these wires as
possible, and pass under the resistor, diode or jumper if need to cross.
Capacitor and Zener diode
should be located at near
terminals
Supply GND for P-side driving
VUFB
P
Output
(to motor)
Vin
UP
U
Power supply
+15V
VP1
Bootstrap
diode
Bootstrap negative electrodes
should be connected to U,V,W
terminals directly and separated
from the main output wires
Cin wiring should be
as short as possible
Wiring between N and
shunt resistor should be
as short as possible.
CIN
Control
GND
VNC
㪥㩷
㪛㪠㪧㪄㪠㪧㪤㩷
Snubber
capacitor
Shunt
resistor
Connect CIN filter's
capacitor to control GND
(not to Power GND)
㪥㪈㩷
Power GND
Locate sunbber capacitor
between P and N1 and as
near by terminals as possible
It is recommended to connect control GND and
power GND at only a point. (not broad pattern)
Fig.3-13
Precaution for wiring on PCB
31
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
3.1.10 SOA of Super Mini DIP-IPM Ver.4
The following describes the SOA (Safety Operating Area) of the Super Mini DIP-IPM Ver.4.
Maximum rating of IGBT collector-emitter voltage
VCES :
Supply voltage applied on P-N terminals
VCC :
VCC(surge): The total amount of VCC and the surge voltage generated by the wiring inductance and the
DC-link capacitor.
VCC(PROT) : DC-link voltage that DIP-IPM can protect itself.
≤Vcc(surge)
Collector current Ic
≤Vcc(surge)
≤VCC
VCE=0䋬IC=0
≤VCC(PROT)
Short-circuit current
VCE=0䋬IC=0
≤2μs
Fig.3-14
SOA at switching mode and short-circuit mode
In Case of switching
VCES represents the maximum voltage rating (600V) of the IGBT. By subtracting the surge voltage (100V
or less) generated by internal wiring inductance from VCES is VCC(surge), that is 500V. Furthermore, by
subtracting the surge voltage (50V or less) generated by the wiring inductor between DIP-IPM and
DC-link capacitor from VCC(surge) derives VCC, that is 450V.
In Case of Short-circuit
VCES represents the maximum voltage rating (600V) of the IGBT . By Subtracting the surge voltage (100V
or less) generated by internal wiring inductor from VCES is VCC(surge), that is, 500V. Furthermore, by
subtracting the surge voltage (100V or less) generated by the wiring inductor between the DIP-IPM and
the electrolytic capacitor from VCC(surge) derives VCC, that is, 400V.
32
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
3.1.11 Power Life Cycles
When DIP-IPM is in operation, repetitive temperature variation will happens on the IGBT junctions (ΔTj). The
amplitude and the times of the junction temperature variation affect the device lifetime.
Fig.3-15 shows the IGBT power cycle curve as a function of average junction temperature variation (ΔTj).
(The curve is a regression curve based on 3 points of ΔTj=46, 88, 98°C with regarding to failure rate of 0.1%, 1%
and 10%. These data are obtained from the reliability test of intermittent conducting operation)!
10000000
1%
10%
0.1%
Power Cycles
1000000
100000
10000
1000
10
100
1000
Average junction temperature variation ΔTj(°C)
Fig.3-15
Power cycle curve
33
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
3.2 Power Loss and Thermal Dissipation Calculation
3.2.1 Power Loss Calculation
Simple expressions for calculating average power loss are given below:
䃂 Scope
The power loss calculation intends to provide users a way of selecting a matched power device for their
VVVF inverter application. However, it is not expected to use for limit thermal dissipation design.
䃂 Assumptions
(1) PWM controlled VVVF inverter with sinusoidal output;
(2) PWM signals are generated by the comparison of sine waveform and triangular waveform.
(3) Duty amplitude of PWM signals varies between
1− D 1+ D
(%/100), (D: modulation depth).
㨪
2
2
(4) Output current various with Icp·sinx and it does not include ripple.
(5) Power factor of load output current is cosθ, ideal inductive load is used for switching.
䃂 Expressions Derivation
PWM signal duty is a function of phase angle x as
1 + D × sin x
which is equivalent to the output voltage
2
variation. From the power factor cosθ, the output current and its corresponding PWM duty at any phase
angle x can be obtained as below:
Output current = Icp × sin x
1 + D × sin( x + θ )
PWM Duty =
2
Then, VCE(sat) and VEC at the phase x can be calculated by using a linear approximation:
Vce( sat ) = Vce( sat )(@ Icp × sin x)
Vec = (−1) × Vec(@ Iecp(= Icp) × sin x)
Thus, the static loss of IGBT is given by:
1
2π
∫
π
0
( Icp × sin x) ×Vce( sat )(@ Icp × sin x) ×
1 + D sin( x + θ )
• dx
2
Similarly, the static loss of free-wheeling diode is given by:
1
2π
∫
2π
π
((−1) × Icp × sin x)((−1) × Vec(@ Icp × sin x) ×
1 + D sin( x + θ )
• dx
2
On the other hand, the dynamic loss of IGBT, which does not depend on PWM duty, is given by:
1
2π
∫
π
0
( Psw(on)(@ Icp × sin x) + Psw(off )(@ Icp × sin x)) × fc • dx
34
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
FWDi recovery characteristics can be approximated by the ideal curve shown in Fig.3-16, and its
dynamic loss can be calculated by the following expression:
trr
Iec
Vec
t
Irr
Vcc
Fig.3-16
Ideal FWDi recovery characteristics curve
Psw =
Irr × Vcc × trr
4
Recovery occurs only in the half cycle of the output current, thus the dynamic loss is calculated by:
1 2π Irr (@ Icp × sin x) × Vcc × trr (@ Icp × sin x)
× fc • dx
2 ∫π
4
1 2π
= ∫ Irr (@ Icp × sin x) × Vcc × trr (@ Icp × sin x) × fc • dx
8 ρ
٨ Attention of applying the power loss simulation for inverter designs㩷
䊶㩷 Divide the output current period into fine-steps and calculate the losses at each step based on the
actual values of PWM duty, output current, VCE(sat), VEC, and Psw corresponding to the output
current. The worst condition is most important.
䊶㩷 PWM duty depends on the signal generating way.㩷
䊶㩷 The relationship between output current waveform or output current and PWM duty changes with
the way of signal generating, load, and other various factors. Thus, calculation should be carried
out on the basis of actual waveform data.㩷
䊶㩷 VCE(sat),VEC and Psw(on, off) should be the values at Tj=125°C.㩷
35
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
3.2.2 Temperature Rise Considerations and Calculation Example
Fig.3-17 shows the typical characteristics of allowable motor rms current versus carrier frequency under the
following inverter operating conditions based on power loss simulation results.
Conditions: VCC=300V, VD=VDB=15V, VCE(sat)=Typ., Switching loss=Typ., Tj=125°C, Tf=100°C, Rth(j-f)=Max.,
Rth(c-f)=0.3°C/W (per 1/6 module), P.F=0.8, 3-phase PWM modulation, 60Hz sine waveform output
16
14
Io(Arms)
12
10
8
PS21965
PS21964
PS21963
PS21963-E
PS21962
PS21961
6
4
2
0
0
5
10
15
20
25
fc(kHz)
Fig.3-17. Effective current-carrier frequency characteristics
Fig.3-17 shows an example of estimating allowable inverter output rms current under different carrier
frequency and permissible maximum operating temperature condition (Tf=100°C. Tj=125°C). The results may
change for different control strategy and motor types. Anyway please ensure that there is no large current
over device rating flowing continuously.
The allowable motor current can also be obtained from the free power loss simulation software provided by
Mitsubishi electric on its web site (URL: http://www.mitsubishichips.com/).
36
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
3.3 Noise Withstand Capability
3.3.1 Evaluation Circuit
Super Mini DIP-IPM Ver.4 series have been confirmed to be with over +/-2.0kV noise withstand capability
by the noise evaluation under the conditions shown in Fig.3-18. However, noise withstand capability greatly
depends on the test environment, the wiring patterns of control substrate, parts layout, and other factors;
therefore an additional confirmation on prototype is necessary.
Heat sink
C1
U
R
Breaker
3-phase
S
DIP-IPM
T
V
W
M
㪝㪦㩷
Voltage slider
I/F
Control supply
(15V single power-source)㩷
Isolation
transformer
Inverter
Noise simulator
DC supply
AC100V
Fig.3-18
㩷
Noise withstand capability evaluation circuit
Note:
C1: AC line common-mode filter 4700pF
PWM signals are inputted from microcomputer both directly and through opto-coupler
15V single power supply
Test is performed with both IM and DCBLM motors
Test conditions
VCC=300V, VD=15V, Ta=25°C, no load
Scheme of applying noise : From AC line (R, S, T), Period T=16ms, Pulse width tw=0.05-1μs, input
in random.
3.3.2 Countermeasures and Precautions
DIP-IPM improves noise withstand capabilities by means of reducing parts quantity, lowering internal wiring
parasitic inductance, and reducing leakage current.
For malfunction caused by external noise, please consider the following countermeasures:
(1) Improving power supply filtering (close to DIP-IPM terminals)
(2) Lowering impedance of input parts (reducing pull-up resistance)
(3) Connecting filter between input parts and GND (bypassing noise)
37
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
SYSTEM APPLICATION HIGHLIGHT
3.3.3 Static Electricity Withstand Capability
Super Mini DIP-IPM Ver.4 series have been confirmed to be with +/-200V or more withstand capability
against static electricity from the following tests shown in Fig.3-19 and Fig.3-20.
LVIC
R=0Ω
C=200pF
㪭N1㩷
UN
VN
WN
VNC
Fig.3-19 VN1 terminal Surge Test circuit
㩷
HVIC
R=0Ω
VP1
C=200pF
UP
VPC
Fig.3-20 VP1 terminal Surge Test circuit
38
VUFB
VG
VUFS
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
KEY PARAMETERS SELECTING GUIDANCE
CHAPTER 4
KEY PARAMETERS SELECTING GUIDANCE
4.1 Determination of Shunt Resistance
(1) Shunt resistance
The value of current sensing resistance is calculated by the following expression:
RShunt = VSC(ref)/SC
where VSC(ref) is the referenced SC trip voltage.
The maximum value of SC trip level should be set less than the IGBT minimum saturation current which is
1.7 times as large as the rated current. For example, the maximum SC trip level of PS21964 is 1.7 x 15=25.5A.
The parameters (VSC(ref), RShunt) dispersion should be considered in the design.
for example of PS21964-4, there is 0.1V dispersion in the data of VSC(ref) as shown in Table 4-1.
(unit: V)
Table 4-1. Specification for VSC(ref)
Min
Typ
Max
Specification at
Tj=25°C, VD=15V
0.43
0.48
0.53
Then, the variation of SC trip level can be calculated by the following expressions:
SC(max)= VSC(max) / RShunt(min)
SC(typ) = VSC(typ) / RShunt(typ)㩷
SC(min)= VSC(min) / RShunt(max)
Supposing shunt resistance dispersion is +/-5%, then the SC range can be obtained as shown in Table 4-2
Table 4-2. Operative SC Range
(unit: A) (RShunt=20.8mΩ(min), 21.9mΩ(typ), 23.0mΩ(max)
min.
typ.
max.
Operative SC level at Tj=25°C
18.7
21.9
25.5
It is possible that the actual SC protective level is less than the calculated one. This is considered due to
the resonant signals caused mainly by parasitic inductance and parasitic capacity. It is recommended to
make a confirmation of the resistance by prototype experiment.
(2) RC Filter Time Constant
It is necessary to set an RC filter in the SC sensing circuit in order to prevent malfunction of SC protection
due to noise interference. The RC time constant is determined depending on the applying time of noise
interference and the SCSOA of the DIP-IPM.
When the voltage drop on the external shunt resistor exceeds the SC trip level, The time (t1) that the CIN
terminal voltage rises to the referenced SC trip level can be calculated by the following expression:
VSC = R shunt ⋅ I c ⋅ (1 − ε
−
t1
τ
)
VSC
)
R shunt ⋅ I c
where Vsc is the CIN terminal input voltage, Ic the peak current, τ the RC time constant.
t1 = −τ ⋅ ln(1 −
On the other hand, the typical time delay t2 (from Vsc voltage reaches Vsc(ref) to IGBT gate shutdown) of
IC is shown in Table 4-3.
Table 4-3. Internal time delay of IC㩷
Item
min
typ
max
Unit
IC transfer delay time
0.3
0.5
1.0
μs
Therefore, the total delay time from an SC level current happened to the IGBT gate shutdown becomes:
tTOTAL=t1+t2
39
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
KEY PARAMETERS SELECTING GUIDANCE
Fig.4-1 shows the typical SCSOA performance curve of PS21962,3,4. The DIP-IPM can shutdown safely
an SC current that is about 9.5 times of its current rating under the noted conditions only if the IGBT conducting
period is less than 4.5μsec.
The SCSOA operation area will vary with the control supply voltage, DC-link voltage, and etc.
24
22
Peak Short Circuit Current: × Ic rating (A)
20
18
16
14
12
10
8
DIP-IPM ver.4 SCSOA at
VD=16.5V
VCC=400V
Tj=125㷄
6
4
2
0
0
1
2
3
4
5
6
7
8
9
Short Circuit Withstand Capability :tw(μs)
Fig.4-1
Typical SCSOA performance
40
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
KEY PARAMETERS SELECTING GUIDANCE
4.2 Single Supply Drive Scheme
4.2.1 Bootstrap Capacitor Initial Charging
Initial charge loop
P(VCC)
Bootstrap Condenser
+
HVIC
VDB
P-side IGBT
U,V,W
High voltage & high speed
recovery type diode
N-side IGBT
VD
LVIC
VIN(N)
N(GND)
Bootstrap Circuitry
VCC
PWM Start
0V
VD
0V
VDB
0V
VIN(N)
off
Bootstrap Charging Timing Chart
Fig.4-2
Initial charging loop and timing chart of bootstrap circuit
㩷
By using bootstrap circuit, conventional three isolated 15V power supply for P-side three IGBT drive can be
eliminated. The initial charge of the bootstrap capacitors is necessary to start-up the inverter. Fig.4-2 shows the
charge mechanism. The pulse width or pulse number should be large enough to make a full charge of the
bootstrap capacitor.
For reference, the charging time for the bootstrap circuit with a 100μF capacitor and 50Ωcurrent limiting
resistor is about 5msec.
41
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
KEY PARAMETERS SELECTING GUIDANCE
4.2.2 Charging and Discharging of the Bootstrap Capacitor During Inverter Operation
High-side IC
R1
D1
R1
VCC
VB
P
C1
ID
IGBT1
M1
FWDi1
M
VS
IGBT2
Q1
FWDi2
N
Fig.4-3
㩷
Inverter circuit diagram
䋨1䋩㩷 Charging operation Timing Chart of Bootstrap Capacitor (C1)
Sequence (1-1) : IGBT2 ON (Fig.4-4)
When IGBT2 is in ON state, charging voltage on C1 (VC(1)) is calculated by
VC(1) = VCC-VF1-Vsat2-ID·R1 (Transient state)
(Steady state)
VC(1) = VCC
where VCC is the charging supply voltage, VF1 the forward voltage drop of diode D1, Vsat2 the
saturation voltage of IGBT2, ID the charging current, and R1 the inrush current limitation resistance.
Then, IGBT2 is turned off. Motor current will flow through the free-wheel path of FWDi1. Once the electric
potential of VS rises near to that of P, the charging to C1 is stopped.
When IGBT1 is in ON state, the voltage of C1 gradually declines from the potential VC(1) due to the current
consumed by the drive circuit.
㩷
ON
IGBT1
OFF
ON
IGBT2
Spontaneous discharge of C1
OFF
Declining due to current
consumed by drive circuit
VC1
Potential of C1
VC(1)
VS
㩷
Fig.4-4 Timing chart of sequence (1-1)
42
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
KEY PARAMETERS SELECTING GUIDANCE
㩷
Sequence (1-2): IGBT2 OFF and FWDi2 ON (Fig.4-5)
When IGBT2 is OFF and FWDi2 is ON, the voltage on C1 (VC(2)) is calculated by:
VC(2)=VCC-VF1+VEC2
where VEC2 denotes the forward voltage drop of FWDi2. When both IGBT2 and IGBT1 are OFF, the
regenerative current flows continuously through the free-wheel path of FWDi2. Therefore the potential of
VS drops to -VEC2, then C1 is recharged to restore the declined potential. When IGBT1 is turned ON, the
potential of VS rises to that of P, the charge to C1 stops and the voltage on C1 gradually declines from the
potential V C(2) due to the current consumed by the drive circuit.
㩷
ON
IGBT1
OFF
ON
IGBT2
OFF
VC1
Potential of C1
VC(2)
Declining due to current
consumed
by
drive
circuit
VS
㩷
Fig.4-5 Timing chart of sequence (1-2)
㩷
䋨2䋩㩷 Instruction of Selecting the Bootstrap Capacitor (C1) and Resistance (R1)
The capacitance of bootstrap capacitor can be calculated by:
C1=IBS×T1/ΔV
where T1 is the maximum ON pulse width of IGBT1 and IBS is the drive current of the IC (depends on
temperature and frequency characteristics), and ΔV is the allowable discharge voltage. A certain margin
should be added to the calculated capacitance.
Resistance R1 should be basically selected such that the time constant C1R1 will enable the discharged
voltage (ΔV) to be fully charged again within the minimum ON pulse width (T2) of IGBT2.
However, if only IGBT1 has an ON-OFF-ON control mode (Fig.4-6), the time constant should be set so
that the consumed energy during the ON period can be charged during the OFF period.
!
㩷
ON
IGBT1
OFF
ON
IGBT2
OFF
Declining due to current
consumed by drive circuit
Vc1
Potential of C1
Charging area
VS
Fig.4-6 Timing Chart of ON-OFF-ON Control Mode
43
㩷
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
KEY PARAMETERS SELECTING GUIDANCE
㩷
Design example of Bootstrap circuit
Selecting bootstrap capacitor
Suppose ΔVDB(discharged voltage)=1V, the maximum ON pulse width T1 of P-side IGBT is 5msec, and
IDB is 0.55mA(Max. rating), then
C=IDB×T1/ΔVDB=2.75×10-6
the calculated bootstrap capacitance is 2.75μF. By taking consideration of dispersion and reliability, the
capacitance is generally selected as large as 2~3 times of the calculated one, for example, 10μF or above
for this case is suitable.
Selecting bootstrap resistor
Suppose the bootstrap capacitance is 10μF, VD=15V, VDB=14V, and the minimum ON pulse width t0 of
N-side IGBT (or the minimum OFF pulse width t0 of upper-side IGBT) is 20μs, then to recover VDB to 15V
during this period, the bootstrap resistance should be
R={(VD-VDB) ×t0}/(C×ΔVDB)=2
This means a 2Ωresistor is suitable.
Note:
(1) In the case of the control for DCBLM or 2-phase modulation for IM (Induction Motor), there will be a long ON time
period on the P-side IGBT, please pay attention to the bootstrap supply voltage drop.
(2) The above result is only a calculation example. It is recommended to design a system by taking consideration of the
actual control pattern and lifetime of components.
Selecting bootstrap diode
The bootstrap diode with blocking voltage over 600V is recommended. In DIP-IPM, the maximum rating
of power supply is 450V. The actual voltage applied on the diode is 500V by adding a surge voltage of about
50V. Furthermore, if considering 100V for the margin, 600V class diode is necessary. The diode is also
highly recommended to be with fast recovery characteristics (recovery time less than 100nsec).
Noise filter for control supply
It is recommended to insert a film type or ceramic type noise filter with 0.22-2μF to the control supply
terminals(VP1-VNC, VN1-VNC, VUFB-U, VVFB-V, VWFB-W). The smaller the supply parasitic impedance is, the
smaller a feasible noise filter capacitance can be . The supply circuit should be such designed that the noise
fluctuation is less than +/-1V/μs, and the ripple voltage is less than +/-2V.
Reference:
There are tow kinds of control supply in general use. The first one is DC-DC converter (3-terminal
regulator), of which input DC supply comes from AC-transformer. The other is DC-DC converter
(switching regulator), of which input DC supply is generated by a SMPS.
Note:
After bootstrap capacitor voltage has been fully charged, input one pulse in the P-side input signals to reset internal IC
state before starting formal PWM.
44
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
INTERFACE DEMO BOARD
CHAPTER 5
INTERFACE DEMO BOARD
5.1 Super Mini DIP-IPM Ver.4 Interface Demo Board
This chapter describes the interface demo board of Super Mini DIP-IPM Ver.4 as a reference for the design
of user application PCB with Super Mini DIP-IPM Ver.4.
(1) Demo Board Outline
The demo board consists the minimum necessary components such as snubber capacitor, bootstrap circuit
elements of Super Mini DIP-IPM Ver.4 interface shown in Fig.5-1.
㩷
㩷
Inrush Limit
Circuit
㩷
C2
C1
㩷
㩷
P
AC Supply
DIP-IPM
㩷
㩷
HVIC
䌾㩷
Motor
㩷
㩷
LVIC
Z
㩷
C
㩷
N
㩷
㩷
CIN
VNC
㩷
㩷
VN1
㩷
RC Filter
Super MiniDIP-IPM Ver.4
Interf ace Circuit㩷
UP-WN
㩷
Fo
㩷
㩷
㩷
GND
VD
(15V Line)
㩷
Fig.5-1 Demo board interface circuit
(2) Demo Board Photos
Top view
Side view
Fig.5-2 Demo board photo
Note: Board dimension 43.5×40×27.1mm (including snubber capacitor height and module height)
45
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
INTERFACE DEMO BOARD
5.2 Pattern Wiring
N
(1) Component Layout
U
V
W
P
<20
Fig.5-3
Demo board component layout
(2) PCB Pattern Layout
(a) Component side
Fig.5-4
(b) Solder side
Demo board PCB pattern layout
46
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
INTERFACE DEMO BOARD
5.3 Circuit Schematic and Parts List
(1) Circuit Schematic
R1
D1
C1
C4
C7
UP
R3
UP
D2
C2
C5
WP
C6
VWFB
T2
U
V
V
WP
C8
UN
VN
VN
WN
WN
FO
W
C11
N
FO
R4
+5V
W
VN1
UN
GND
U
VVFB
VP
D3
C3
+15V
P
P
VP1
R2
VP
T3-1
VUFB
DIP-IPM Ver.4
T1
ZD1
VNC(16pin)
NC(17pin)
C9
CIN
C10
R5
R6
T3-2
N1
Fig.5-5 Demo board circuit schematic
Note: Although there is no zener diode mounted to P-side three floating drive supplies (between VUFB-U, VVFB-V,
VWFB-W) on this demo board, it is highly recommend to add these zener diodes in actual system board.
47
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
INTERFACE DEMO BOARD
(2) Parts List
Table 5-1 Parts list (only for reference)
Symbol
Type Name
Description
pcs
Note
D1
U05JH44
0.5A 600V Diode
1 Toshiba, High speed type
D2
U05JH44
0.5A 600V Diode
1 Toshiba, High speed type
D3
U05JH44
0.5A 600V Diode
1 Toshiba, High speed type
ZD1
U1ZB24
24V 1W Zener Diode
1 Toshiba
C1
UFP1H220MEH
22PF50V Al electrolytic capacitor
1 Nichicon
C2
UFP1H220MEH
22PF50V Al electrolytic capacitor
1 Nichicon
C3
UFP1H220MEH
22PF50V Al electrolytic capacitor
1 Nichicon
C4
GRM188R11H102KA01
1000pF50V ceramic capacitor
1 Murata
C5
GRM188R11H102KA01
1000pF50V ceramic capacitor
1 Murata
C6
GRM188R11H102KA01
1000pF50V ceramic capacitor
1 Murata
C7
GRM188R11H102KA01
1000pF50V ceramic capacitor
1 Murata
C8
GRM188R11H102KA01
1000pF50V ceramic capacitor
1 Murata
C9
UFP1H470MEH
47PF50V Al electrolytic capacitor
1 Nichicon
C10
GRM188R11H102KA01
1000PF50V ceramic capacitor
1 Murata
C11
MDDSA2J224K
0.22PF630V snubber capacitor
1 Hitachi AIC
R1
RK73H1JTD10F
1/16W 10:F
1 KOA
R2
RK73H1JTD10F
1/16W 10:F
1 KOA
R3
RK73H1JTD10F
1/16W 10:F
1 KOA
R4
RK73H1JTD10kF
1/16W 10k:F
1 KOA
R5
RK73H1JTD2kF
1/16W 2k:F
1 KOA
R6
SL2TTE68LF
2W 0.016/0.021/0.033/0.068/0.11:F
1 KOA, Current detecting resistor
T1
BS10B-SRSS
10pin Socket
1
T2
B3P-VB-2
3-terminal connector
1
T3-1
TP42097-21
Faston® tab
1
T3-2
TP42097-21
Faston® tab
1
(3) Precaution in using the demo board for pre-evaluation
a. The accessories of the Super Mini DIP-IPM Ver.4demo board include an input signal connection cable
and a power supply cable with a connector.
Cut the input signal cable to make the connection between MCU/DSP and the demo board as short as
possible.
b. Please confirm and comply with your company's design standard when drawing upon these patterns.
(These patterns are an example for reference.)
Faston® is a registered trademark of the AMP company.
48
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
PACKAGE HANDLING
CHAPTER 6
PACKAGE HANDLING
6.1 Packaging Specification
(44)
(22)
Plastic Tube
Quantity:
DIP-IPM Ver.4
12pcs per 1 tube
(520)
5 columns
Total amount in one box (max):
Binder
6 stages
Tube Quantity: 5 × 6=30
IPM Quantity: 30 × 12=360
xxx
xxx
xxx
xxx
xxx
(250)
Mass (max):
(180) About 10g per 1pcs of DIP-IPM
About 220g per 1 tube
About 8.1kg per 1 box
Spacer
(600)
Packaging box
Fig.6-1 Super Mini DIP-IPM Ver.4 Packaging Specification㩷
㩷
49
Jan. 2008
Mitsubishi DIP-IPM Ver.4 Application Note
PACKAGE HANDLING
㩷
6.2 Handling Precautions
㧍 %CWVKQPU
Transportation
·Put package boxes in the correct direction. Putting them upside down, leaning them or
giving them uneven stress might cause electrode terminals to be deformed or resin case
to be damaged.
·Throwing or dropping the packaging boxes might cause the devices to be damaged.
·Wetting the packaging boxes might cause the breakdown of devices when operating. Pay
attention not to wet them when transporting on a rainy or a snowy day.
Storage
·We recommend temperature and humidity in the ranges 5-35°C and 45-75%,
respectively, for the storage of modules. The quality or reliability of the modules might
decline if the storage conditions are much different from the above.
Long storage
·When storing modules for a long time (more than one year), keep them dry. Also, when
using them after long storage, make sure that there is no visible flaw, stain or rust, etc. on
their exterior.
Surroundings
·Keep modules away from places where water or organic solvent may attach to them
directly or where corrosive gas, explosive gas, fine dust or salt, etc. may exist. They
might cause serious problems.
Flame
resistance
·The epoxy resin and the case materials are flame-resistant type (UL standard 94-V0), but
they are not noninflammable.
Static electricity
·ICs and power chips with MOS gate structure are used for the DIP-IPM power modules.
Please keep the following notices to prevent modules from being damaged by static
electricity.
(1)Precautions against the device destruction caused by the ESD
The ESD of human bodies and packaging and/or excessive voltage applied across the
gate to emitter may damage and destroy devices. The basis of anti-electrostatic is to
inhibit generating static electricity possibly and quick dissipation of the charged electricity.
*Containers that charge static electricity easily should not be used for transit and for
storage.
*Terminals should be always shorted with a carbon cloth or the like until just before using
the module. Never touch terminals with bare hands.
*Should not be taking out DIP-IPM from tubes until just before using DIP-IPM and never
touch terminals with bare hands.
*During assembly and after taking out DIP-IPM from tubes, always earth the equipment
and your body. It is recommended to cover the work bench and its surrounding floor with
earthed conductive mats.
*When the terminals are open on the printed circuit board with mounted modules, the
modules might be damaged by static electricity on the printed circuit board.
*If using a soldering iron, earth its tip.
(2)Notice when the control terminals are open
*When the control terminals are open, do not apply voltage between the collector and
emitter. It might cause malfunction.
*Short the terminals before taking a module off.
㩷
50
Jan. 2008
㩷
㩷
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and
more reliable, but these are always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due
consideration to safety when making your circuit designs, with appropriate measures such as (1)
placement of substitutive, auxiliary circuits, (2) use of non-flammable material or (3) prevention against
any malfunction or mishap.㩷
㩷
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