TSM2NB60 Taiwan Semiconductor N-Channel Power MOSFET 600V, 2A, 4.4Ω FEATURES ● ● KEY PERFORMANCE PARAMETERS Advanced planar process 100% avalanche tested PARAMETER VALUE UNIT VDS 600 V RDS(on) (max) 4.4 Ω Qg 9.4 nC APPLICATION ● Power Supply ● Lighting TO-220 ITO-220 TO-251(IPAK) TO-252(DPAK) Notes: Moisture sensitivity level: level 3. Per J-STD-020 ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted) LIMIT PARAMETER SYMBOL UNIT IPAK/DPAK ITO-220 TO-220 Drain-Source Voltage VDS 600 V Gate-Source Voltage VGS ±30 V Continuous Drain Current Pulsed Drain Current TC = 25°C (Note 1) 2 ID TC = 100°C (Note 2) A 1.35 IDM 8 A Single Pulsed Avalanche Energy (Note 3) EAS 55 mJ Single Pulsed Avalanche Current (Note 3) IAS 2 A EAR 4.4 mJ dv/dt 4.5 V/ns (Note 2) Repetitive Avalanche Energy Peak Diode Recovery dv/dt (Note 4) Total Power Dissipation @ TC = 25°C Operating Junction and Storage Temperature Range Document Number: DS_P0000070 PDTOT TJ, TSTG 1 44 25 - 55 to +150 70 W °C Version: E15 TSM2NB60 Taiwan Semiconductor THERMAL PERFORMANCE LIMIT PARAMETER SYMBOL Junction to Case Thermal Resistance UNIT IPAK/DPAK ITO-220 TO-220 2.87 5 1.78 RӨJC Junction to Ambient Thermal Resistance RӨJA 110 62.5 62.5 o C/W o C/W Notes: RӨJA is the sum of the junction-to-case and case-to-ambient thermal resistances. The case thermal reference is defined at the solder mounting surface of the drain pins. RӨJA is guaranteed by design while RӨCA is determined by the user’s board design. RӨJA shown below for single device operation on FR-4 PCB in still air ELECTRICAL SPECIFICATIONS (TA = 25°C unless otherwise noted) PARAMETER Static CONDITIONS SYMBOL MIN TYP MAX UNIT (Note 5) Drain-Source Breakdown Voltage VGS = 0V, ID = 250uA BVDSS 600 -- -- V Gate Threshold Voltage VDS = VGS, ID = 250uA VGS(TH) 2.5 3.6 4.5 V Gate Body Leakage VGS = ±30V, VDS = 0V IGSS -- -- ±100 nA Zero Gate Voltage Drain Current VDS = 600V, VGS = 0V IDSS -- -- 10 uA Drain-Source On-State Resistance VGS = 10V, ID = 1A RDS(ON) -- 3.9 4.4 Ω Forward Transfer Conductance VDS = 40V, ID = 1A gfs -- 1.5 -- S Qg -- 9.4 -- Qgs -- 2.2 -- Qgd -- 4.7 -- Ciss -- 249 -- Coss -- 30.7 -- Crss -- 5 -- Rg -- 8.5 -- td(on) -- 9.1 -- tr -- 9.8 -- td(off) -- 17.4 -- tf -- 12.4 -- Dynamic (Note 6) Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 480V, ID = 2A, VGS = 10V Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Switching VDS = 25V, VGS = 0V, f = 1.0MHz F = 1MHz, open drain nC pF Ω (Note 7) Turn-On Delay Time Turn-On Rise Time VGS = 10V, ID = 2A, Turn-Off Delay Time VDD = 300V, RG =25Ω Turn-Off Fall Time Document Number: DS_P0000070 2 ns Version: E15 TSM2NB60 Taiwan Semiconductor ELECTRICAL SPECIFICATIONS (TA = 25°C unless otherwise noted) PARAMETER Source-Drain Diode CONDITIONS SYMBOL MIN TYP MAX UNIT (Note 5) Diode Forward Voltage IS = 2A, VGS = 0V VSD -- 0.9 1.4 V Reverse Recovery Time VGS = 0V, IS =2A, trr -- 490 -- ns Reverse Recovery Charge dIF/dt = 100A/us Qrr -- 0.8 -- µC Source Current Integral reverse diode IS -- -- 2 A Source Current (Pulse) in the MOSFET ISM -- -- 8 A Notes: 1. Current limited by package. 2. Pulse width limited by the maximum junction temperature. o 3. L = 25mH, IAS = 2A, VDD = 50V, RG = 25Ω, Starting TJ = 25 C. 4. ISD ≤ 2A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25ºC. 5. Pulse test: PW ≤ 300µs, duty cycle ≤ 2%. 6. For DESIGN AID ONLY, not subject to production testing. 7. Switching time is essentially independent of operating temperature. Document Number: DS_P0000070 3 Version: E15 TSM2NB60 Taiwan Semiconductor ORDERING INFORMATION PACKAGE PACKING TSM2NB60CZ C0G PART NO. TO-220 50pcs / Tube TSM2NB60CI C0G TSM2NB60CH C5G ITO-220 50pcs / Tube TO-251 (IPAK) 75pcs / Tube TSM2NB60CP ROG TO-252 (DPAK) 2,500pcs / 13” Reel Note: 1. Compliant to RoHS Directive 2011/65/EU and in accordance to WEEE 2002/96/EC 2. Halogen-free according to IEC 61249-2-21 definition Document Number: DS_P0000070 4 Version: E15 TSM2NB60 Taiwan Semiconductor CHARACTERISTICS CURVES (TC = 25°C unless otherwise noted) Output Characteristics Transfer Characteristics On-Resistance vs. Drain Current Gate-Source Voltage vs. Gate Charge On-Resistance vs. Junction Temperature Document Number: DS_P0000070 Source-Drain Diode Forward Current vs. Voltage 5 Version: E15 TSM2NB60 Taiwan Semiconductor CHARACTERISTICS CURVES (TC = 25°C unless otherwise noted) Capacitance vs. Drain-Source Voltage BVDSS vs. Junction Temperature Maximum Safe Operating Area (TO-220) Maximum Safe Operating Area (ITO-220) Maximum Safe Operating Area (DPAK/IPAK) Document Number: DS_P0000070 6 Version: E15 TSM2NB60 Taiwan Semiconductor Electrical Characteristics Curves (TC = 25°C unless otherwise noted) Normalized Effective Transient Thermal Impedance Normalized Thermal Transient Impedance, Junction-to-Case (TO-220) 10 1 100 10-1 Duty=0.5 Duty=0.2 Duty=0.1 Duty=0.05 Duty=0.02 Duty=0.01 Single pulse 10-2 10-3 10-4 10-6 10-5 10-4 10-3 10-2 10-1 100 Square Wave Pulse Duration (s) Normalized Effective Transient Thermal Impedance Normalized Thermal Transient Impedance, Junction-to-Case (ITO-220) 10 1 100 10-1 Duty=0.5 Duty=0.2 Duty=0.1 Duty=0.05 Duty=0.02 Duty=0.01 Single pulse 10-2 10-3 10-4 10-6 10-5 10-4 10-3 10-2 10-1 100 Square Wave Pulse Duration (s) Normalized Effective Transient Thermal Impedance Normalized Thermal Transient Impedance, Junction-to-Case (DPAK/IPAK) 101 100 10-1 Duty=0.5 Duty=0.2 Duty=0.1 Duty=0.05 Duty=0.02 Duty=0.01 Single pulse 10-2 10-3 10-4 10-6 10-5 10-4 10-3 10-2 10-1 100 Square Wave Pulse Duration (s) Document Number: DS_P0000070 7 Version: E15 TSM2NB60 Taiwan Semiconductor PACKAGE OUTLINE DIMENSIONS (Unit: Millimeters) TO-220 MARKING DIAGRAM Y = Year Code M = Month Code for Halogen Free Product O =Jan P =Feb Q =Mar R =Apr S =May T =Jun U =Jul V =Aug W =Sep X =Oct Y =Nov Z =Dec L = Lot Code (1~9, A~Z) Document Number: DS_P0000070 8 Version: E15 TSM2NB60 Taiwan Semiconductor PACKAGE OUTLINE DIMENSIONS (Unit: Millimeters) ITO-220 MARKING DIAGRAM G Y WW F = Halogen Free = Year Code = Week Code (01~52) = Factory Code Document Number: DS_P0000070 9 Version: E15 TSM2NB60 Taiwan Semiconductor PACKAGE OUTLINE DIMENSIONS (Unit: Millimeters) TO-251(IPAK) MARKING DIAGRAM Y = Year Code M = Month Code for Halogen Free Product O =Jan P =Feb Q =Mar R =Apr V =Aug S =May T =Jun U =Jul W =Sep X =Oct Y =Nov Z =Dec L = Lot Code (1~9, A~Z) Document Number: DS_P0000070 10 Version: E15 TSM2NB60 Taiwan Semiconductor PACKAGE OUTLINE DIMENSIONS (Unit: Millimeters) TO-252(DPAK) SUGGESTED PAD LAYOUT (Unit: Millimeters) MARKING DIAGRAM Y = Year Code M = Month Code for Halogen Free Product O =Jan P =Feb Q =Mar R =Apr S =May T =Jun U =Jul V =Aug W =Sep X =Oct Y =Nov Z =Dec L = Lot Code (1~9, A~Z) Document Number: DS_P0000070 11 Version: E15 TSM2NB60 Taiwan Semiconductor Notice Specifications of the products displayed herein are subject to change without notice. TSC or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, to any intellectual property rights is granted by this document. Except as provided in TSC’s terms and conditions of sale for such products, TSC assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of TSC products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify TSC for any damages resulting from such improper use or sale. Document Number: DS_P0000070 12 Version: E15