RT9101 2.65W PWM Class-D Power Amplifier General Description Features The RT9101 is a 2.65W, high efficiency Class-D audio amplifier featuring low-resistance internal power MOSFETs and the gain can be set by an external input resistance. The filter free topology eliminates the output filter and reduces the external component count, footprint area, and system costs. z It is very suitable for power sensitive application, such as cellular handsets and battery powered devices. In addition to these features, the RT9101 provides a fast startup time to minimize audible popping during device turn-on and turnoff. Moreover, the RT9101 also integrates thermal and over current protection circuits. The RT9101 is available in WDFN-8L 3x3, and WL-CSP-9B 1.45x1.45 (BSC) packages. Ordering Information RT9101 ( 88% at 400mW ` 80% at 100mW Low Quiescent Current and Shutdown Current Optimized PWM Output Stage Eliminates LC Filter Fully Differential Design Reduces RF Rectification and Eliminates Bypass Capacitor Internally Generated 250kHz Switching Frequency Integrated Pop and Click Suppression Circuitry RoHS Compliant and Halogen Free ` z z z z z z Applications z z z z Mobile Phones Handsets PDAs Portable multimedia devices Pin Configurations (TOP VIEW) SHDN NC INP INN 3 6 4 9 5 2 7 OUTN GND VDD OUTP ) WDFN-8L 3x3 Default : WDFN-8L 3x3 C : WL-CSP-9B 1.45x1.45 (BSC) Note : Richtek products are : INP A1 VDD B1 A2 A3 OUTN B2 B3 GND C3 OUTP VDD INN C1 C2 SHDN Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) GND Package Type QW : WDFN-8L 3x3 (W-Type) WSC : WL-CSP-9B 1.45x1.45 (BSC) ` 8 1 GND Operating from a single 5V supply, the RT9101 is capable of driving 4Ω speaker load at a continuous average output of 2.65W/10% THD+N or 2W/0.5% THD+N. The RT9101 has a higher efficiency with speaker load compared to a typical class AB amplifier. With a 3.6V supply driving an 8Ω speaker, the efficiency for a 400mW power level is 88%. z Wide Operating Voltage : 2.5V to 5.5V High Efficiency With an 8Ω Ω Speaker : WL-CSP-9B 1.45x1.45 (BSC) RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. DS9101-01 April 2011 www.richtek.com 1 RT9101 Marking Information RT9101GQW RT9101CWSC 21 : Product Code FL= : Product Code FL=YM DNN YMDNN : Date Code W : Date Code 21W RT9101ZQW FL : Product Code FL YM DNN YMDNN : Date Code Typical Application Circuit RT9101 CI 2.2µF Audio Input from DAC RI 150k CI RI 2.2µF 150k SHDN OUTN INP OUTP RL VDD INN GND CS 1µF Figure 1. Application Circuit with Differential Input RT9101 CI 2.2µF Audio Input CI 2.2µF RI 150k RI 150k SHDN OUTN INP OUTP RL VDD INN GND CS 1µF Figure 2. Application Circuit with Single-Ended Input www.richtek.com 2 DS9101-01 April 2011 RT9101 Functional Pin Description Pin No. WL-CSP-9B WDFN-8L 3x3 1.45x1.45 (BSC) Pin Name Pin Function 1 C2 SHDN Shutdown Control (Active Low). 2 -- NC No Internal Connection. 3 A1 INP Positive Input of Differential Audio Signal. 4 C1 INN Negative Input of Differential Audio Signal. 5 C3 OUTP Positive Output. 6 7, 9 (Exposed Pad) 8 B1, B2 VDD A2, B3 GND Supply Voltage Input. Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum thermal dissipation. Negative Output. A3 OUTN Function Block Diagram VDD + - - INN + + VDD + - DS9101-01 April 2011 OUTP GND INP SHDN Gate Driver Gate Driver OUTN Protection Circuit www.richtek.com 3 RT9101 Absolute Maximum Ratings z z z z z z z z (Note 1) Supply Voltage, VDD ------------------------------------------------------------------------------------------------Input Voltage, INP, INN ---------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WDFN-8L 3x3 --------------------------------------------------------------------------------------------------------WL-CSP-9B 1.45x1.45 (BSC) ------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WDFN-8L 3x3, θJA ---------------------------------------------------------------------------------------------------WDFN-8L 3x3, θJC --------------------------------------------------------------------------------------------------WL-CSP-9B 1.45x1.45 (BSC), θJA ------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------- Recommended Operating Conditions z z z −0.3V to 6V −0.3V to(VDD + 0.3V) 1.429W 1.250W 70°C/W 8.2°C/W 80°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Supply Voltage, VDD ------------------------------------------------------------------------------------------------- 2.7V to 5.5V Junction Temperature Range --------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range --------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VDD = 5V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Output Offset Voltage VOS VDD = 2.5V to 5.5V -- 1 25 mV Power Supply Rejection Ratio PSRR VDD = 2.5V to 5.5V (Note 5) -- −70 −55 dB High Level Input Current Low Level Input Current ⎪ IIH ⎪ ⎪ IIL ⎪ VDD = 5.5V, VI = 5.8V VDD = 5.5V, VI = −0.3V --- --- 100 5 μA μA VDD = 5.5V, No Load 2 --- --3.4 -0.4 4.9 VDD = 3.6V, No Load -- 2.8 -- VDD = 2.5V, No Load -- 2.2 3.2 VSHDN = 0V, VDD = 2.5V to 5.5V -- -- 1 VDD = 2.5V -- 600 -- VDD = 3.6V -- 500 -- -- 400 -- Output Impedance in SHDN VDD = 5V VSHDN = 0V -- >1 -- kΩ Switching Frequency VDD = 2.5V to 5.5V 200 250 300 kHz Gain VDD = 2.5V to 5.5V Logic-High VIH SHDN Input Threshold Voltage Logic-Low VIL Quiescent Current Shutdown Current Static Drain-Source On-State Resistance Resistance from SHDN to GND IQ ISHDN RDS(ON) 284k/RI 300k/RI 316k/RI -- 200 -- V mA μA mΩ V/V kΩ To be continued www.richtek.com 4 DS9101-01 April 2011 RT9101 Operating Characteristics (Gain = 2V/V,RL= 8Ω, TA = 25°C, unless otherwise noted) Parameter Symbol Test Condition Min Typ Max VDD = 5V -- 2.65 -- VDD = 3.6V -- 1.5 -- VDD = 2.5V -- 0.52 -- VDD = 5V -- 2.08 -- VDD = 3.6V -- 1.06 -- VDD = 2.5V -- 0.42 -- VDD = 5V -- 1.45 -- VDD = 3.6V -- 0.73 -- VDD = 2.5V -- 0.33 -- VDD = 5V -- 1.19 -- VDD = 3.6V -- 0.59 -- VDD= 2.5V -- 0.26 -- VDD = 5V, PO = 1W, RL = 8Ω, f = 1kHz VDD = 3.6V, PO = 0.5W, RL = 8Ω, f = 1kHz VDD = 2.5V, PO = 200mW, RL = 8Ω, f = 1kHz -- 0.06 -- -- 0.05 -- THD+N = 10%, f = 1kHz, RL = 4Ω THD+N = 1%, f = 1kHz, RL = 4Ω Output Power PO THD+N = 10%, f = 1kHz, RL = 8Ω THD+N = 1%, f = 1kHz, RL = 8Ω Total Harmonic Distortion Plus Noise THD+N Unit W W W W % -- 0.04 -- Supply Ripple Rejection Ratio PSRR VDD = 5V, f = 217Hz, VDD-Ripple = 200mVpp -- −70 -- dB Signal-to-Noise Ratio SNR VDD = 5V, PO = 1W, RL = 8Ω, A Weighting Filter -- 95 -- dB Input Impedance Start-Up Time from Shutdown ZI 142 150 158 kΩ -- 1 -- ms VDD = 3.6V Note 1. Stresses listed as the above “ Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in natural convection at TA = 25°C on a high-effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guarantee by design. DS9101-01 April 2011 www.richtek.com 5 RT9101 Typical Operating Characteristics Efficiency vs. Output Power Efficiency vs. Output Power 90 100 VDD = 2.5V 90 80 VDD = 5V VDD = 3.6V 70 60 50 40 30 60 50 40 30 20 20 10 10 Gain = 2V/V, f = 1kHz, RL = 8Ω, 33μH Gain = 2V/V, f = 1kHz, RL = 4Ω, 33μH 0 0 0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 1 1.2 1.4 1.6 1.8 2 Output Power vs. Load Resistance Output Power vs. Load Resistance 2.5 0.8 Output Power (W) Output Power (W) 2.5 Gain = 2V/V, f = 1kHz, THD+N = 1% Gain = 2V/V, f = 1kHz, THD+N = 10% 2.0 Output Power (W) 2.0 Output Power (W) VDD = 5V VDD = 3.6V VDD = 2.5V 70 Efficiency (%) Efficiency (%) 80 1.5 1.0 VDD = 5V VDD = 3.6V 0.5 1.5 1.0 VDD = 5V VDD = 3.6V 0.5 VDD = 2.5V VDD = 2.5V 0.0 0.0 4 8 12 16 20 24 28 4 32 8 12 16 20 24 28 32 Load Resistance (dB) Load Resistance (dB) Supply Current vs. Output Power Supply Current vs. Output Power 700 300 VDD = 3.6V 600 VDD = 2.5V Supply Current (mA) Supply Current (mA) 250 VDD = 5V 200 150 100 50 VDD = 5V VDD = 3.6V 500 400 VDD = 2.5V 300 200 100 Gain = 2V/V, RL = 8Ω, 33μH Gain = 2V/V, RL = 4Ω, 33μH 0 0 0 0.2 0.4 0.6 0.8 Output Power (W) www.richtek.com 6 1 1.2 1.4 0 0.5 1 1.5 2 2.5 3 Output Power (W) DS9101-01 April 2011 RT9101 THD+N vs. Output Power THD+N vs. Output Power 20 20 10 VDD = 2.5V 10 VDD = 3.6V 2 THD+N (%/Div) THD+N (%/Div) 5 VDD = 5V 1 0.5 0.2 0.1 VDD = 3.6V 2 VDD = 5V 1 0.5 0.2 0.1 0.05 0.05 0.02 0.02 0.01 VDD = 2.5V 5 RL = 8Ω, f = 1kHz, Gain = 2V/V 10m 20m 50m 100m 200m 500m 1 2 0.01 5 RL = 4Ω, f = 1kHz, Gain = 2V/V 10m 20m 50m 2 THD+N vs. Frequency THD+N vs. Frequency 10 VDD = 5V, CI = 2.2μF, RL= 8Ω, Gain = 2V/V 5 10 VDD = 3.6V, CI = 2.2μF, RL= 8Ω, Gain = 2V/V 5 1 THD+N (%/Div) 1 PO = 50mW 0.5 0.2 0.1 PO = 250mW 0.05 0.02 PO = 1W 0.01 0.5 0.2 0.1 0.002 0.001 100 200 500 1k PO = 500mW 0.01 0.005 50 PO = 125mW 0.02 0.002 0.001 20 PO = 25mW 0.05 0.005 2k 5k 10k 20k 20 50 100 200 THD+N vs. Frequency 1k 2k 5k 10k 20k THD+N vs. Frequency 10 5 PO = 250mW, CI = 2.2μF, RL= 4Ω, Gain = 2V/V VDD = 2.5V, CI = 2.2μF, RL= 8Ω, Gain = 2V/V 2 2 1 THD+N (%/Div) 1 0.5 0.2 0.1 PO = 15mW PO = 75mW 0.05 0.02 0.01 0.5 0.2 0.1 0.02 0.005 0.002 0.002 50 100 200 500 1k 2k Frequency (Hz/Div) DS9101-01 April 2011 VDD = 4V VDD = 2.5V 0.01 PO = 200mW 20 VDD = 5V VDD = 3.6V 0.05 0.005 0.001 500 Frequency (Hz/Div) Frequency (Hz/Div) 10 5 5 2 2 THD+N (%/Div) 1 Output Power (W/Div) Output Power (W/Div) THD+N (%/Div) 100m 200m 500m 5k 10k 20k 0.001 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz/Div) www.richtek.com 7 RT9101 PSRR vs. Frequency PSRR vs. Frequency +0 VP-P = 200mV, CI = 2.2μF, RL= 8Ω, Gain = 2V/V -10 -10 -20 -20 -30 -30 PSRR (dB/Div) PSRR (dB/Div) +0 -40 -50 VDD = 2.5V -60 VDD = 3.6V -40 -50 VDD = 2.5V -60 -70 -70 -80 VDD = 5V -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k VP-P = 200mV, CI = 2.2μF, RL= 4Ω, Gain = 2V/V 10k 20k VDD = 3.6V VDD = 5V 20 50 Power Dissipation vs. Output Power 2k 5k 10k 20k Power Dissipation vs. Output Power 0.7 VDD = 5V, f = 1kHz, Gain = 2V/V 1.2 VDD = 3.6V, f = 1kHz, Gain = 2V/V 0.6 1.0 0.8 RL = 4Ω + 33μH 0.6 0.4 0.2 Power Dissipation (W) Power Dissipation (W) 500 1k Frequency (Hz/Div) Frequency (Hz/Div) 1.4 100 200 0.5 0.4 RL = 4Ω + 33μH 0.3 0.2 RL = 8Ω + 33μH 0.1 RL = 8Ω + 33μH 0.0 0 0 0.5 1 1.5 2 2.5 0 Output Power (W) GSM Power Supply Rejection vs. Time 0.2 0.4 0.6 0.8 1 1.2 Output Power (W) GSM Power Supply Rejection vs. Frequency +0 VDD = 3.6V, PK -PK = 512mV VDD = 3.6V, CI = 2.2μF, RL= 8Ω, Gain = 2V/V -20 Supply Voltage (dB/Div) -40 VDD (1V/Div) VOUT (20mV/Div) -60 -80 -100 -120 Gain = 2V/V, CI = 2.2μF, RL = 8Ω, f = 217Hz, Duty = 12% Time (2.5ms/Div) -140 -150 Output Voltage 0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k Frequency (Hz/Div) www.richtek.com 8 DS9101-01 April 2011 RT9101 Application information The RT9101 is a fully differential amplifier with differential inputs and outputs. The RT9101 integrates a differential amplifier and a common mode voltage controller. The differential amplifier ensures that the amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The RT9101 can support differential input and single ended input applications. Components Selection Input Resistors (RI) Amplifier can be resistors and the gain can be calculated as the following equation : Gain = 2 x 150kΩ RI Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the input resistors. CMRR, PSRR, and the cancellation of the second harmonic distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance or better resistors to keep the performance optimized. The input resistors should be placed very close to the RT9101 to limit noise injection on the high impedance nodes. It is recommended to set the gain at 2V/V or lower for better performance. Decoupling Capacitor The RT9101 is a high performance Class-D audio amplifier that requires adequate power supply decoupling to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients, spikes, or digital hash on the line, a good low Equivalent-Series-Resistance (ESR) ceramic capacitor, typically 1μF, placed as close as possible to the VDD pin can achieve the best performance. Placing this decoupling capacitor close to the RT9101 is very important for the efficiency of the ClassD amplifier, because any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lower frequency noise signals, it is recommended to use a 10μF or greater capacitor placed near the audio power amplifier. DS9101-01 April 2011 Input Capacitor In the typical application, an input coupling capacitor (CI) is required to allow the input signal to the proper dc level for optimum operation. However, the RT9101 is a fully differential amplifier with good CMRR so that the RT9101 does not require input coupling capacitors if using a differential input source that is biased from 0.5 V to VDD − 0.8 V. Use 1% tolerance or better gain-setting resistors if input coupling capacitors are not used. In the single-ended input application, an input capacitor, (CI), is required to allow the amplifier to bias the input signal to the proper dc level. In this case, CI and RI form a high-pass filter with the corner frequency as shown in the following equation : 1 fC = 2π RICI Gain (dB) -3dB f (Hz) fC The value of CI is important to consider as it directly affects the bass (low frequency) performance of the circuit. For example, the flat bass response requirement is 10 Hz and RI is 20kΩ, the value of CI can be calculated by the following equation : 1 CI = 2π RIfC In this example, CI is 0.8μF. A capacitance1μF or larger can be used. Under Voltage Lockout The under voltage lock out circuit operates as a voltage detector and always monitors the supply voltage (VDD) while SHND = 1. While powered on, the chip is kept still in shutdown mode until VDD rises to greater than 2.2V (typ). While powered off, the chip does not leave operation mode until VDD falls to less than 2.1V (typ). www.richtek.com 9 RT9101 Maximum Power Dissipation (W) 1 Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. 8L 3x3 packages, the thermal resistance, θJA, is 70°C/W on a standard JEDEC 51-7 four-layer thermal test board. For WL-CSP-9B 1.45x1.45 (BSC) packages, the thermal resistance, θJA, is 80°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for WDFN-8L 3x3 package PD(MAX) = (125°C − 25°C) / (80°C/W) = 1.250W for WL-CSP-9B 1.45x1.45 (BSC) package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. For the RT9101 packages, the derating curves in Figure 3 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Four-Layer PCB WDFN-8L 3x3 WL-CSP-9B 1.45x1.45 (BSC) 0 25 50 75 100 125 Ambient Temperature (°C) Figure 3. Derating Curves for RT9101 Packages Layout Considerations For best performance of the RT9101, the following PCB Layout guidelines must be strictly followed. ` Place the decoupling capacitors as close as possible to the VDD and GND pins. ` Keep the differential input and output traces as wide and short as possible. The traces of (INP & INN) and (OUTP & OUTN) should be kept equal width and length respectively. ` Connect the GND and Exposed Pad to a strong ground plane for maximum thermal dissipation and noise protection. CI RI Audio Input CI RI SHDN NC INP INN GND 8 1 3 GND For recommended operating condition specifications of the RT9101, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For WDFN- 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 6 4 9 5 2 7 OUTN GND VDD OUTP CS The decoupling capacitor (C S ) must be placed as close to the IC as possible Figure 4. PCB Layout Guide www.richtek.com 10 DS9101-01 April 2011 RT9101 Outline Dimension D2 D L E E2 1 e SEE DETAIL A b 2 1 2 1 A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 D 2.950 3.050 0.116 0.120 D2 2.100 2.350 0.083 0.093 E 2.950 3.050 0.116 0.120 E2 1.350 1.600 0.053 0.063 e L 0.650 0.425 0.026 0.525 0.017 0.021 W-Type 8L DFN 3x3 Package DS9101-01 April 2011 www.richtek.com 11 RT9101 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.525 0.625 0.021 0.025 A1 0.200 0.260 0.008 0.010 b 0.290 0.350 0.011 0.014 D 1.400 1.500 0.055 0.059 D1 E 1.000 1.400 0.039 1.500 0.055 0.059 E1 1.000 0.039 e 0.500 0.020 9B WL-CSP 1.45x1.45 Package (BSC) Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 12 DS9101-01 April 2011