APA2068 Stereo 2.6W Audio Power Amplifier (With DC_Volume Control) Features General Description • • APA2068 is a monolithic integrated circuit, which provides precise DC volume control, and a stereo bridged audio Low Operating Current with 9mA Improved Depop Circuitry to Eliminate Turn-on power amplifiers capable of producing 2.6W (1.8W) into 4Ω with less than 10% (1.0%) THD+N. The attenuator and Turn-off Transients in Outputs • • High PSRR range of the volume control in APA2068 is from 20dB (DC_Vol=0V) to -80dB (DC_Vol=3.54V) with 32 steps. The 32 Steps Volume Adjustable by DC Voltage with Hysteresis • 2.6W per Channel Output Power into 4Ω Load at • Two Output Modes Allowable with BTL and SE advantage of internal gain setting can be less components and PCB area. Both of the depop circuitry and the 5V, BTL Mode thermal shutdown protection circuitry are integrated in APA2068, that reduce pops and clicks noise during power up or shutdown mode operation. It also improves the power off pop noise and protects the chip from being Modes Selected by SE/BTL pin • Low Current Consumption in Shutdown Mode destroyed by over temperature and short current failure. To simplify the audio system design, APA2068 combines (1µA) • • Short-Circuit Protection a stereo bridge-tied loads (BTL) mode for speaker drive and a stereo single-end (SE) mode for headphone drive Thermal Shutdown Protection and Over-Current Protection Circuitry • • • • into a single chip, where both modes are easily switched by the SE/BTL input control pin signal. Maximum Output Swing Clamping Function The OUT+ Signal and the IN- Signal are Outphase Applications SOP-16P Packages with Thermal Pad Package Lead Free and Green Devices Available • • (RoHS Compliant) NBs LCD Monitor or TVs Ordering and Marking Information Package Code KA : SOP-16P Operating Ambient Temperature Range I : - 40 to 85 oC Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APA2068 Assembly Material Handling Code Temperature Range Package Code APA2068 KA : APA2068 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 1 www.anpec.com.tw APA2068 Pin Configuration MUTE SHUTDOWN RINBYPASS GND LINVOLUME VOLMAX 1 2 3 4 5 6 7 8 APA2068 16 15 14 13 12 11 10 9 ROUTVDD ROUT+ SE/BTL GND LOUT+ VDD LOUT- = Thermal Pad (Connected to GND for better heat dissipation) Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol Parameter VDD Supply Voltage Range VIN Input Voltage Range, SE/BTL, SHUTDOWN, MUTE TJ Maximum Junction Temperature TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature,10 Seconds PD Power Dissipation Rating Unit -0.3 to 6 V -0.3 to VDD+0.3 V 150 °C -65 to +150 °C 260 °C Internal Limited W Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA θJC Parameter Typical Value Unit 45 °C/W 10 °C/W Thermal Resistance from Junction to Ambient (Note 2) SOP-16P Thermal Resistance from Junction to Case (Note 3) SOP-16P Note 2: The Thermal-Pad on the bottom of the IC should soldered directly to the PCB’s Thermal-Pad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz copper thickness. Note 3: The case temperature is measured at the center of the Thermal-Pad on the underside of the SOP-16P package. Recommended Operating Conditions Symbol Range Parameter Unit Min. Max. VDD Supply Voltage 4.5 5.5 V TA Operating Ambient Temperature Range -40 85 °C TJ Operating Junction Temperature °C VIH High Level Threshold Voltage Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 2 - 125 SHUTDOWN, MUTE 2 - SE/BTL 4 - V www.anpec.com.tw APA2068 Recommended Operating Conditions (Cont.) Symbol Range Parameter VIL Low Level Threshold Voltage VICM Common Mode Input Voltage Min. Max. SHUTDOWN, MUTE - 1.0 SE/BTL - 1 VDD-1.0 - Unit V V Electrical Characteristics VDD = 5V, TA=25°C (unless otherwise noted) Symbol Parameter APA2068 Test Conditions Unit Min. Typ. Max. SE/BTL=0V - 9 20 SE/BTL=5V - 4 10 - 1 - µA IDD Supply Current ISD Supply Current in Shutdown Mode IIH High Input Current - 900 - nA IIL Low Input Current - 900 - nA Output Differential Voltage - 5 - mV - 1 - S SE/BTL=0V VOS TSTART-UP Start-Up Time from Shutdown SHUTDOWN=0V Bypass Capacitor, Cb=2.2µF mA Operating Characteristics, BTL mode VDD = 5V, TA = 25°C, RL = 4Ω, Gain = 2V/V (unless otherwise noted) Symbol PO THD+N PSRR Parameter Maximum Output Power Total Harmonic Distortion Plus Noise Power Ripple Rejection Ratio Crosstalk Channel Separation S/N Signal to Noise Ratio APA2068 Test Conditions Unit Min. Typ. Max. THD+N=10%, RL=3Ω, fin = 1kHz - 2.9 - THD+N=10%, RL=4Ω, fin = 1kHz - 2.6 - THD+N=10%, RL=8Ω, fin = 1kHz - 1.6 - THD+N=1%, RL=3Ω, fin = 1kHz - 2.4 - THD+N=1%, RL=4Ω, fin = 1kHz - 1.8 - THD+N=1%, RL=8Ω, fin = 1kHz 1 1.3 - PO = 1.2W, RL = 4Ω, fin = 1kHz - 0.07 - PO = 0.9W, RL = 8Ω, fin = 1kHz - 0.08 - Vrr = 0.1Vrms, RL = 8Ω, CB = 1µF, fin = 120Hz - 60 - dB CB = 1µF, RL = 8Ω, fin = 1kHz - 90 - dB PO = 1.1W, RL = 8Ω, A_Weighting - 95 - dB W % Operating Characteristics, SE mode. VDD = 5V,TA = 25°C, Gain = 1V/V (unless otherwise noted) Symbol PO Parameter Maximum Output Power Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 APA2068 Test Conditions Unit Min. Typ. Max. THD+N= 10%, RL = 16Ω, fin = 1kHz - 220 - THD+N= 10%, RL = 32Ω, fin = 1kHz - 120 - THD+N = 1%, RL = 16Ω, fin = 1kHz - 160 - THD+N = 1%, RL = 32Ω, fin = 1kHz - 95 - 3 mW www.anpec.com.tw APA2068 Electrical Characteristics (Cont.) Operating Characteristics, SE mode. VDD = 5V,TA = 25°C, Gain = 1V/V (unless otherwise noted) Symbol THD+N PSRR Parameter Total Harmonic Distortion Plus Noise Power Ripple Rejection Ratio Crosstalk Channel Separation S/N APA2068 Test Conditions Signal to Noise Ratio Unit Min. Typ. Max. PO = 125mW, RL = 16Ω, fin = 1kHz - 0.09 - PO = 65mW, RL = 32Ω, fin = 1kHz - 0.09 - % VIN = 0.1Vrms, RL = 8Ω, CB = 1µF, fin = 120Hz - 60 - dB CB = 1µF, RL = 32Ω, fin = 1kHz - 60 - dB PO = 75mW, SE, RL = 32Ω, A_Weighting - 100 - dB Pin Description PIN I/O FUNCTION NO. NAME 1 MUTE I Mute control signal input, hold low for normal operation, hold high to mute. 2 SHUTDOWN I It will be into shutdown mode when pull low. ISD = 1µA 3 RIN- I Right channel input terminal 4 BYPASS I Bias voltage generator 5,12 GND - Ground connection, Connected to thermal pad. 6 LIN- I Left channel input terminal 7 VOLUME I 8 VOLMAX I Input signal for internal volume gain setting. Setting the maximum output swing. Input a non-zero voltage (VC) to this pin, the output voltage swing will be clamped between VOH (the maximum positive value) VC & VOL (the minimum negative value) + VC. Disable this function when tie this pin to GND. Maximum input voltage ≤ 1/2 VDD. 9 LOUT- O Left channel negative output in BTL mode and high impedance in SE mode. 10,15 VDD - Supply voltage 11 LOUT+ O Left channel positive output in BTL mode and SE mode. 13 SE/BTL I Output mode control input, high for SE output mode and low for BTL mode. 14 ROUT+ O Right channel positive output in BTL mode and SE mode. 16 ROUT- O Right channel negative output in BTL mode and high impedance in SE mode. Control Input Table SHUTDOWN MUTE SE/BTL Operating Mode L X X Shutdown mode H L L BTL out H L H SE out H H X Mute Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 4 www.anpec.com.tw APA2068 Typical Application Circuit VDD 0.1µF VDD VOLMAX Signal 100µF GND VOLMAX LOUT+ 220 µF 1 µF L-CH Input LINVolume Control 1 µF R-Ch Input VDD RIN- Sleeve Tip Headphone Jack 2.2 µF 220 µF VOLUME 1kΩ 4Ω 100kΩ SE/BTL Signal CB BYPASS ROUT+ VDD Control Pin Ring SE/BTL Signal LOUT- BYPASS 50kΩ 1kΩ 4W 100kΩ SE/BTL Shutdown Signal MUTE Signal SHUTDOWN MUTE ROUT- SE/BTL Shutdown ckt Mute A2068_AppCkt Block Diagram VOLMAX LOUT + LINVolume Control LOUT- RINBYPASS BYPASS ROUT+ VOLUME SE/BTL SHUTDOWN MUTE ROUT- SE/BTL Shutdown ckt Mute VDD Power and Depop Circuit GND APA2068_Block Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 5 www.anpec.com.tw APA2068 Volume Control Table_BTL Mode Supply Voltage VDD= 5V Gain (dB) High (V) Low (V) 20 0.12 0.00 18 0.23 0.17 52 0.20 16 0.34 0.28 51 0.31 14 0.46 0.39 50 0.43 12 0.57 0.51 49 0.54 10 0.69 0.62 47 0.65 8 0.80 0.73 46 0.77 6 0.91 0.84 45 0.88 4 1.03 0.96 44 0.99 2 1.14 1.07 43 1.10 0 1.25 1.18 41 1.22 -2 1.37 1.29 40 1.33 -4 1.48 1.41 39 1.44 -6 1.59 1.52 38 1.56 -8 1.71 1.63 37 1.67 -10 1.82 1.74 35 1.78 -12 1.93 1.85 34 1.89 -14 2.05 1.97 33 2.01 -16 2.16 2.08 32 2.12 -18 2.28 2.19 30 2.23 -20 2.39 2.30 29 2.35 -22 2.50 2.42 28 2.46 -24 2.62 2.53 27 2.57 -26 2.73 2.64 26 2.69 -28 2.84 2.75 24 2.80 -30 2.96 2.87 23 2.91 -32 3.07 2.98 22 3.02 -34 3.18 3.09 21 3.14 -36 3.30 3.20 20 3.25 -38 3.41 3.32 18 3.36 -40 3.52 3.43 17 3.48 -80 5.00 3.54 16 5 Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 Hysteresis (mV) Recommended Voltage (V) 0 6 www.anpec.com.tw APA2068 Typical Operating Characteristics THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD = 5V AV =20dB fin = 1kHz BTL RL = 4Ω RL = 3Ω 1 THD+N (%) 1 THD+N (%) VDD = 5V AV =14dB fin = 1kHz SE RL = 8Ω 0.1 0.01 0 0.5 1 1.5 2 2.5 Output Power (W) 3 RL = 32Ω 0.1 0.01 3.5 RL = 16Ω 0 THD+N vs. Output Power THD+N vs. Output Power 10 10 80m 120m 160m 200m 240m Output Power (W) 40m VDD = 5V fin =1kHz RL =3Ω BTL VDD = 5V AV =20dB RL =3Ω BTL THD+N (%) THD+N (%) 1 AV = 20dB 0.1 1 0.5 1.5 fin= 20Hz fin= 1kHz AV = 6dB 0.01 0 fin = 20kHz 1 0.1 2 2.5 3 0.05 10m 3.5 100m Output Power (W) THD+N vs. Frequency 10 VDD = 5V RL =3Ω PO = 1.8W BTL THD+N (%) THD+N (%) 1 AV = 20dB 0.1 5 Output Power (W) THD+N vs. Frequency 10 1 VDD = 5V AV = 6dB RL =3Ω BTL 1 0.1 PO = 0.9W AV = 6dB PO = 1.8W 0.01 20 100 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 0.01 20 10k 20k 7 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2068 Typical Operating Characteristics (Cont.) THD+N vs. Output Power 10 THD+N vs. Output Power 10 VDD = 5V fin =1kHz RL =4Ω BTL fin= 20kHz 1 THD+N (%) THD+N (%) 1 VDD = 5V AV =20dB RL =4Ω BTL AV = 20dB 0.1 fin = 20Hz 0.1 fin = 1kHz AV = 6dB 0.01 0 0.5 1 1.5 2 2.5 3 0.01 10m 3.5 100m 1 Output Power (W) Output Power (W) THD+N vs. Frequency THD+N vs. Frequency 10 VDD = 5V RL=4Ω PO=1.5W BTL 1 AV = 6dB 0.1 VDD = 5V AV= 6dB RL=4Ω BTL 1 THD+N (%) THD+N (%) 10 PO = 0.8W 0.1 PO = 1.5W AV = 20dB 0.01 20 0.01 20 10k 20k 100 1k Frequency (Hz) THD+N (%) THD+N (%) 10 VDD = 5V fin= 1kHz RL=8Ω BTL 1 AV = 6dB 1k Frequency (Hz) 10k 20k VDD = 5V AV = 20dB RL=8Ω BTL 1 fin = 20kHz fin = 20Hz 0.1 0.1 fin = 1kHz AV = 20dB 0.01 100 THD+N vs. Output Power THD+N vs. Output Power 10 5 0 0.5 1 1.5 2 2.5 3 0.01 10m 3.5 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 100m 1 5 Output Power (W) 8 www.anpec.com.tw APA2068 Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Frequency 10 VDD = 5V AV = 6dB RL=8Ω BTL THD+N (%) THD+N (%) 10 1 PO = 0.5W VDD=5V RL=8Ω PO=0.9W BTL 1 0.1 AV = 6dB 0.1 PO = 0.9W 0.01 20 100 1k AV = 20dB 0.01 10k 20k 20 100 1k Frequency (Hz) Frequency (Hz) THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD=5V fin=1kHz RL=16Ω SE VDD=5V AV=14dB RL=16Ω CO=1000µF 1 SE THD+N (%) THD+N (%) 1 AV = 0dB 0.1 fin = 20kHz 0 fin = 1kHz 0.01 40m 80m 120m 160m 200m 240m 10m 50m Output Power (W) THD+N vs. Frequency THD+N vs. Frequency 10 VDD=5V RL=16Ω PO=125mW CO=1000µF 1 SE THD+N (%) THD+N (%) 100m 200m 300m Output Power (W) 10 AV = 0dB 0.1 VDD=5V AV=0dB RL=16Ω CO=1000µF 1 SE PO = 125mW 0.1 PO = 60mW AV = 14dB 0.01 fin = 20Hz 0.1 AV = 14dB 0.01 10k 20k 20 1k 100 Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 0.01 10k 20k 9 20 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2068 Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 VDD=5V AV=14dB RL=32Ω CO=1000µF SE VDD=5V fin=1kHz RL=32Ω SE 1 THD+N (%) AV = 0dB 1 fin = 20Hz fin = 20kHz 0.1 0.1 AV = 14dB 0.01 0 40m 80m fin = 1kHz 0.01 10m 120m 160m 200m 240m 50m Output Power (W) THD+N vs. Frequency THD+N vs. Frequency THD+N (%) THD+N (%) 10 VDD=5V RL=32Ω PO=65mW CO=1000µF 1 SE AV = 0dB VDD=5V AV=14dB RL=32Ω CO=1000µF 1 SE PO = 30mΩ 0.1 0.1 AV = 14dB 20 PO = 65mΩ 100 1k Frequency (Hz) 0.01 20 10k 20k 100 Frequency Response +20 +320 +320 +16 +300 +190 +8 Phase( 6dB) VDD=5V RL=4Ω PO=0.8W BTL Gain( 6dB) 100 1k 10k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 +180 Gain(dB) Phase( 20dB) Phase (Degrees) Gain(dB) +330 Gain( 20dB) +310 +0 10 10k 20k Frequency Response +16 +4 1k Frequency (Hz) +20 +330 Gain( 20dB) +12 200m300m Output Power (W) 10 0.01 100m Phase( 20dB) +12 +300 +190 +8 +170 +4 +160 Phase( 6dB) VDD=5V RL=8Ω PO=0.5W BTL +0 10 100k 200k 10 +310 100 Phase (Degrees) THD+N (%) 10 +180 Gain( 6dB) +170 1k 10k Frequency (Hz) +160 100k 200k www.anpec.com.tw APA2068 Typical Operating Characteristics (Cont.) Frequency Response Gain(14dB) +10 +210 +260 +220 +2 Gain(0dB) +200 +180 -2 VDD=5V RL=16Ω CO=1000µF PO=60mW SE -6 20 100 Phase(0dB) +6 Gain(dB) +240 Phase(14dB) Phase (Degrees) Phase(14dB) +6 -10 +220 Gain(14dB) +280 +10 Gain(dB) Frequency Response +14 +300 +160 +200 +2 -2 -6 -10 +120 100k 200k 20 VDD=5V RL=8Ω PO=0.9 W BTL -50 -60 -70 -80 -90 -100 Right to Left Left to Right -110 -120 20 100 1k Frequency (Hz) +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 Crosstalk(dB) -20 -30 Left to Right -10 -20 -40 -60 Left to Right -30 Right to Left -60 -80 -80 -90 -90 -100 20 -100 10k 20k VDD=5V RL=32Ω CO=1000µF PO=65mW SE -50 -70 Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 10k 20k -40 -70 100 1k Frequency (Hz) 1k Crosstalk vs. Response VDD=5V RL=16Ω CO=1000µF PO=125mW SE Right to Left 100 Frequency (Hz) +0 -50 +165 100k 200k Right to Left -120 20 10k 20k Crosstalk(dB) +0 1k 10k Frequency (Hz) VDD=5V RL=4Ω PO=1.5 W BTL Crosstalk vs. Response -10 100 +170 Crosstalk vs. Frequency Crosstalk(dB) Crosstalk(dB) Crosstalk vs. Frequency +0 -10 -20 -30 -40 Phase(0dB) +180 VDD=5V RL=32Ω CO=1000µF PO=30mW SE +140 1k 10k Frequency (Hz) +190 Gain(0dB) Phase (Degrees) +14 Left to Right 20 100 1k 10k 20k Frequency (Hz) 11 www.anpec.com.tw APA2068 Typical Operating Characteristics (Cont.) Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency 100µ Output Noise Voltage(V) Output Noise Voltage(V) 100µ Filter BW<22kHz 20µ A-Weighting 10µ VDD=5V AV=6dB RL=4Ω BTL 1µ 20 1k 100 Frequency (Hz) 20µ Filter BW<22kHz 10µ A-Weighting 1µ 20 10k 20k PSRR vs. Frequency PSRR(dB) -30 VDD=5V RL=4Ω Vrr=200mV AV=20dB BTL -20 -30 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 20 100 1k Frequency (Hz) -100 20 10k 20k +0 T VDD=5V -10 R =8Ω -20 V L =1Vrms IN -30 A =6dB V -40 BTL -50 -60 -70 -80 -90 -100 -110 -120 -130 20 100 100 1k Frequency (Hz) 10k 20k Shutdown Attenuation vs. Frequency Shutdown Attenuation(dB) Mute Attenuation vs. Frequency Mute Attenuation(dB) 10k 20k VDD=5V RL=32Ω Vrr=200mV AV=14dB SE -10 -40 -100 1k PSRR vs. Frequency +0 PSRR(dB) -20 100 Frequency (Hz) +0 -10 VDD=5V AV=0dB RL=32Ω SE +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 VDD=5V RL=8Ω VIN=1Vrms AV=6dB BTL -110 1k 10k -120 20 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 100 1k 10k 20k Frequency (Hz) 12 www.anpec.com.tw APA2068 Typical Operating Characteristics (Cont.) Gain vs. Volume Voltage Supply Current vs. Supply Voltage 20 10.0 10 9.0 No Load Gain(dB) -10 Supply Current (mA) 0 Down -20 Up -30 -40 -50 -60 -70 VDD=5V No Load BTL BTL 8.0 7.0 6.0 5.0 SE 4.0 3.0 -80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 DC Voltage (V) 2.0 3.0 Power Dissipation vs.Output Power 200 1.8 RL=3Ω Power Dissipation(mW) Power Dissipation(W) RL=4Ω 1.2 1.0 0.8 RL=8Ω 0.6 0.4 VDD=5V THD+N<1% BTL 0.2 0.50 1.00 1.50 2.00 5.5 160 140 120 RL=16Ω 100 80 RL=32Ω 60 VDD=5V THD+N<1% SE 40 20 0 2.50 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 5.0 RL=8Ω 180 1.6 1.4 4.0 4.5 Supply Voltage(V) Power Dissipation vs. Output Power 2.0 0.0 0.00 3.5 13 0 50 100 150 200 Output Power(W) 250 www.anpec.com.tw APA2068 Application Information BTL Operation The APA2068 output stage (power amplifier) has two pairs of operational amplifiers internally, which allows different a single supply, SE configuration. Single-Ended Operation To consider the single-supply SE configuration shown amplifier configurations. Application Circuit, a coupling capacitor is required to block the DC offset voltage from reaching the load. These caOUT+ Volume Control amplifier output signal pacitors can be quite large (approximately 33µF to 1000µF), so they tend to be expensive, occupy valuable OP1 PCB area, and have the additional drawback of limiting low-frequency performance of the system (refer to the RL Output Coupling Capacitor).The rules described still hold with the addition of the following relationship: OUT- Vbias Circuit OP2 1 CB x 150kΩ Figure 1: APA2068 Internal Configuration ≤ 1 << 1 RiC i RLCC (1) Output SE/BTL Operation (each channel) The best cost saving feature of APA2068 is that it can be switched easily between BTL and SE modes. This feature eliminates the requirement for an additional head- The power amplifier’s OP1 gain is set by internal unitygain and input audio signal comes from internal volume control amplifier while the second amplifier OP2 is inter- phone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone nally fixed in a unity-gain, inverting configuration. Figure 1 shows that the output of OP1 is connected to the input to or speakers must be accommodated. OP2, which results in the output signals of with both amplifiers with identical in magnitude but out of phase 180°. Inside of the APA2068, two separate amplifiers drive OUT+ and OUT- (see Figure 1). The SE/BTL input controls the Consequently, the differential gain for each channel is 2 x (Gain of SE mode). By driving the load differentially through outputs OUT+ and OUT-, an amplifier configuration is commonly referred operation of the follower amplifier that drives LOUT- and ROUT-. • When SE/BTL keeps low, the OP2 turns on and the APA2068 is in the BTL mode. to bridged mode is established. BTL mode operation is different from the classical single-ended SE amplifier con- • When SE/BTL keeps high, the OP2 is in a high output impedance state, which configures the APA2068 as SE figuration where one side of its load is connected to the ground. A BTL amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive to the driver from OUT+. IDD is reduced by approximately onehalf in SE mode. Control of the SE/BTL input can be a logic-level TTL source or a resistor divider network or the stereo headphone jack load, thus, doubles the output swing for aspecified supply voltage. When placed under the same conditions, a BTL amplifier with switch pin as shown in the Application Circuit. has four times the output power of a SE amplifier. A BTL configuration, such as the one used in APA2068, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUT+, ROUT-, LOUT+, and LOUT-, are biased at half-supply, it’s not necessary for DC voltage to be across the load. This eliminates the need for an output coupling capacitor which is required in Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 14 www.anpec.com.tw APA2068 Application Information (Cont.) Output SE/BTL Operation (Cont.) APA2068 DC Volume Control Curve (BTL) 20 10 1kΩ 100kΩ 0 Control Pin Forward -10 Ring Gain (dB) VDD SE/BTL Tip Sleeve -20 Backward -30 -40 -50 Headphone Jack -60 Figure 2: SE/BTL Input Selection by Phonejack Plug -70 In Figure 2, input SE/BTL operates as below : When the phonejack plug is inserted, the 1kΩ resistor is -80 0.0 disconnected and the SE/BTL input is pulled high and enables the SE mode. When the input goes high, the Figure 3: Gain Setting vs. VOLUME Pin Voltage For the highest accuracy, the voltage shown in the ‘rec- OUT- amplifier is shutdown causing the speaker to mute. The OUT+ amplifier then drives through the output ca- ommended voltage’column of the table is used to select a desired gain. This recommended voltage is exactly half- pacitor (CO) into the headphone jack. When there is no headphone plugged into the system, the contact pin of way between the two nearest transitions. The gain levels are 2dB/step from 20dB to -40dB in BTL mode, and the the headphone jack is connnected from the signal pin, the voltage divider set up by resistors 100kΩ and 1kΩ. last step at -80dB as mute mode. Resistor 1kΩ then pulls low the SE/BTL pin, enabling the BTL function. The gain for each audio input of the APA2068 is set by the 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 DC volume (V) Input Resistance, Ri internal resistors (Ri and RF) of volume control amplifier in inverting configuration. Volume Control Function The APA2068 has an internal stereo volume control that SE Gain = AV = − setting is the function of the DC voltage applied to the VOLUME input pin. The APA2068 volume control consists RF Ri (2) RF (3) Ri BTL mode operation brings the factor of 2 in the gain BTL Gain = -2 × of 32 steps that are individually selected by a variable DC voltage level on the VOLUME control pin. The range of the steps, controlled by the DC voltage, are from 20dB to -80dB. Each gain step corresponds to a specific input equation due to the inverting amplifier mirroring the voltage swing across the load. For varying gain settings, the voltage range, as shown in table. To minimize the effect of noise on the volume control pin, which can affect the se- APA2068 generates each input resistance on figure 4. The input resistance will affect the low frequency perfor- lected gain level, hysteresis and clock delay are implemented. The amount of hysteresis corresponds to mance of audio signal. The minmum input resistance is 10kΩ when gain setting is 20dB and the resistance will half of the step width, as shown in the volume control graph. ramp up when close loop gain below 20dB. The input resistance has wide variation (+/-10%) caused by process variation. Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 15 www.anpec.com.tw APA2068 Application Information (Cont.) Input Resistance, Ri (Cont.) polarity in the application. Ri vs. Gain (BTL) 160 Effective Bypass Capacitor, CB A power amplifier, proper supply bypassing, is critical for low noise performance and high power supply rejection. The capacitor location on the BYPASS pin should be as 140 120 close to the device as possible. The effect of a larger supply bypass capacitor is to improve PSRR due to in- Ri (kΩ) 100 80 creased half-supply stability. Two critical criteria of bypass capacitor (CB): 1st, it depends upon desired PSRR 60 requirements and click-and-pop performance; 2 nd, the leakage current of CB will induce the voltage drop of VBYPASS 40 20 0 -40 -30 -20 -10 0 Gain (BTL) 10 (voltage of BYPASS pin), and if the VBYPASS is less than 0.49VDD, APA2068 will enter mute condition. The value of 20 VBYPASS can be calculated as below: Figure 4: Input Resistance vs. Gain Setting VBYPASS = 0.5V DD - ILeakage × 150k Ω Input Capacitor, Ci (6) Where In the typical application, an input capacitor, Ci, is required ILeakage =Leakage current of CB to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the Therefore, it is recommended that CB‘s leakage current should be no more then 0.4µA for properly work of APA2068. minimum input impedance Ri (25kΩ) form a high-pass filter with the corner frequency determined in the follow- To avoid the start-up pop noise, the bypass voltage should rise slower than the input bias voltage and the relation- ing equation : 1 (4) 2π × 25kΩ × Ci The value of Ci is important to consider as it directly afFC(highpass ) = ship shown in equation should be maintained. 1 1 << ( CB X150k Ω ) Ci X150k Ω fects the low frequency performance of the circuit. Consider the example where Ri is 25kΩ and the specification (7) The capacitor is fed from a 150kΩ resistor inside of the amplifier and the 150kΩ is the maximum input resistance of (Ri+RF). Bypass capacitor, CB, values of 2.2µF to calls for a flat bass response down to 50Hz. Equation is reconfigured as below : 1 Ci = (5) 2π × 25kΩ × FC 10µF ceramic or tantalum low-ESR capacitors are recommended for the best THD+N and noise performance. The bypass capacitance also affects the start up time. It is determined in the following equation: When the input resistance variation is considered, the Ci is 0.13µF, therefore, a value in the range of 0.33µF to Tstart up = 5X(CBYPASS X150k Ω ) 1.0µF would be chosen. A further consideration for this capacitor is the leakage path from the input source through (8) Output Coupling Capacitor, CC the input network (Ri+RF, Ci) to the load. This leakage current creates a DC offset voltage at the input to the In the typical single-supply SE configuration, an output amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tanta- coupling capacitor (CC) is required to block the DC bias at the output of the amplifier thus preventing DC currents in lum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high- should face the amplifier input in most applications because the DC level of the amplifiers’input is held at VDD/2. pass filter governed by the equation. 1 FC(highpass ) = 2πRLCC Please note that it is important to confirm the capacitor Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 16 (9) www.anpec.com.tw APA2068 Application Information (Cont.) Output Coupling Capacitor, CC (Cont.) ship between the size of CBYPASS and the turn-on time. In a SE configuration, the output coupling capacitor, CC, is of For example, a 330µF capacitor with an 8Ω speaker would attenuate low frequencies below 60.6Hz. The main particular concern. This capacitor discharges through the internal 10KΩ disadvantage, from a performance standpoint, is the load impedance and is typically small, which drives the low- resistors. Depending on the size of CC, the time constant can be relatively large. To reduce transients in SE mode, frequency corner higher degrading the bass response. Large values of CC are required to pass low frequencies an external 1kΩ resistor can be placed in parallel with the internal 10kΩ resistor. The tradeoff for using this resistor into the load. is an increase in quiescent current. In most cases, choosing a small value of Ci in the range of 0.33µF to 1µF, Cb Power Supply Decoupling, CS The APA2068 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to being equal to 4.7µF and an external 1kΩ resistor should be placed in parallel with the internal 10kΩ resistor should ensure the output total harmonic distortion (THD+N) is as low as possible. Power supply decoupling also pre- produce a virtually clickless and popless turn-on. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain, so it is advanta- vents the oscillations being caused by long lead length between the amplifier and the speaker. The optimum geous to use low-gain configurations. decoupling is achieved by using two different types of capacitors that target on different types of noise on the Shutdown Function In order to reduce power consumption when not in use, power supply leads. For higher frequency transients, spikes, or digital hash the APA2068 contains a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1µF, is placed as close turns the amplifier off when a logic low is placed on the SHUTDOWN pin. The trigger point between a logic high and logic low level is typically 2.0V. It is best to switch as possible to the device VDD lead works best. For filtering lower-frequency noise signals, it is recommended to between the ground and the supply VDD to provide maximum device performance. place a large aluminum electrolytic capacitor of 10µF or greater near the audio power amplifier. By switching the SHUTDOWN pin to low, the amplifier Optimizing Depop Circuitry Circuitry has been included in the APA2068 to minimize enters a low-current state, IDD<1µA. APA2068 is in shutdown mode. On normal operating, SHUTDOWN pin pull the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a to high level to keep the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a definite voltage to voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully dis- avoid unwanted state changing. charged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop The APA2068 mutes the amplifier outputs when logic high circuitry. is applied to the MUTE pin. Applying logic low to the MUTE pin returns the APA2068 to normal operation. Prevent Mute Function The value of Ci will also affect turn-on pops (Refer to Effective Bypass Capacitance). The bypass voltage ramp unanticipated mute behavior by connecting the Mute pin to logic high or low. Do not let the Mute pin float. up should be slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of CBYPASS can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of CBYPASS, turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationCopyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 17 www.anpec.com.tw APA2068 Application Information (Cont.) Maximum Output Swing Clamping Function (VolMax) loads and a 5V supply, the maximum draw on the power supply is almost 3W. The APA2068 provides the maximum output swing clamping function to protect the speaker. When input a non-zero voltage (VX) to VolMax pin, BTL mode output amplitude (VOP) is be limited at VOP=VDD-2VX. A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in equation, VDD is in the denominator. This indicates SE mode output amplitude (VOP) is be limited at VOP = 1/2VDD-2VX. This function can effectively limite the output that as VDD goes down, efficiency goes up. In other words, use the efficiency analysis to choose the correct supply power across the speaker and avoid damaging the speaker. voltage and speaker impedance for the application. Table 1: Efficiency vs. Output Power in 5-V/8Ω BTL Systems. The maximum setting voltage of VolMax is Vdd/2, and when this function is not used, connect the VolMax to the GND. BTL Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. Efficiency = (10) PD (W) 2.00 0.55 0.50 47.62 0.21 2.83 0.55 1.00 66.67 0.30 4.00 0.5 1.25 78.13 0.32 4.47 0.35 tion14 states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving a specified load. PO = SE mode: PD,MAX = (11) VDD2 2π2RL (14) In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus, the maximum power dis- (12) sipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. BTL mode : PD, MAX = (13) 4VDD2 2π2RL (15) Since the APA2068 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both of equations depend on the mode of operation. Even with Table 1 calculates efficiencies for four different output power levels. this substantial increase in power dissipation, the APA2068 does not require extra heatsink. The power dis- Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load sipation from equation14, assuming a 5V-power supply and an 8Ω load, must not be greater than the power dis- is increased resulting in a nearly flat internal power dissipation over the normal operating range. sipation that results from the equation16: Note that the internal dissipation at full output power is less than in the half power range. Calculating the effi- PD, MAX = ciency for a specific system is the key to proper power supply design. For a stereo 1W audio system with 8Ω Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 VPP(V) 0.16 Whether the power amplifier is operated in BTL or SE mode, power dissipation is the major concern. Equa- Where VP × VP ( ) PO πVP 2RL = = PSUP ( VDD × 2 VP ) 4VDD πRL IDD(A) 31.25 Power Dissipation PSUP Vorms × Vorms ( VP × VP ) = 2RL RL VP Vorms = 2 2VP PSUP = VDD × LDDSVG = VDD × πRL Efficiency of a BTL configuration : Efficiency (%) 0.25 **High peak voltages cause the THD+N to increase. The following equations are the basis for calculating amplifier efficiency. 1 Po (W) 18 TJ, MAX - TA θJA (16) www.anpec.com.tw APA2068 Application Information (Cont.) Power Dissipation (Cont.) To calculate maximum ambient temperatures, first consideration is that the numbers from the Power Dissipa- For SOP16-P package with thermal pad, the thermal re- tion vs. Output Power graphs are per channel values, so the dissipation of the IC heat needs to be doubled for sistance (θJA) is equal to 45οC/W. Since the maximum junction temperature (TJ,MAX ) of APA2068 is 150οC and the ambient temperature (TA) is two-channel operation. Given θJA, the maximum allowable junction temperature (TJMAX), and the total internal defined by the power system design, the maximum power dissipation which the IC package is able to handle can be dissipation (PD), the maximum ambient temperature can be calculated with the following equation. The maximum obtained from equation16. Once the power dissipation is greater than the maximum recommended junction temperature for the APA2068 is 150°C. The internal dissipation figures are taken from limit (P D,MAX ), either the supply voltage (V DD) must be decreased, the load impedance (RL) must be increased the Power Dissipation vs. Output Power graphs. or the ambient temperature should be reduced. TAMax = TJMax -θJAPD Thermal Pad Consideration 150 - 45(0.8*2) = 78°C (16) The thermal pad must be connected to the ground. The package with thermal pad of the APA2068 requires spe- The APA2068 is designed with a thermal shutdown protection that turns the device off when the junction tem- cial attention on thermal design. If the thermal design issues are not properly addressed, the APA2068 4Ω will perature surpasses 150°C to prevent damaging the IC. go into thermal shutdown when driving a 4Ω load. The thermal pad on the bottom of the APA2068 should be soldered down to a copper pad on the circuit board. Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on the top surface of the circuit board, 8 to 10 vias of 13 mil or smaller in diameter should be used to thermally couple the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to conduct heat away from the thermal pad should be as large as practical. If the ambient temperature is higher than 25°C, a larger copper plane or forced-air cooling will be required to keep the APA2068 junction temperature below the thermal shutdown temperature (150°C). In higher ambient temperature, higher airflow rate and/or larger copper area will be required to keep the IC out of thermal shutdown. Thermal Consideration Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 19 www.anpec.com.tw APA2068 Package Information SOP-16P D SEE VIEW A h X 45o E E2 EXPOSED PAD E1 D1 b A 0.25 c L 0 GAUGE PLANE SEATING PLANE A1 A2 e VIEW A S Y M B O L SOP-16P INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.069 1.75 0.006 0.000 0.15 A1 0.00 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 9.80 10.00 0.386 0.394 D1 3.50 4.50 0.138 0.177 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 3.00 0.079 0.118 E2 0.049 2.00 e 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 θ 0o 8o 0o 8o Note : 1. Follow from JEDEC MS-012 BC. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 20 www.anpec.com.tw APA2068 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-16P A H T1 C d D W E1 F 330.0±2.00 50 MIN. 16.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.5±0.10 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.40±0.20 10.30±0.20 2.10±0.20 4.0±0.10 8.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity SOP-16P Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 21 www.anpec.com.tw APA2068 Taping Direction Information SOP-16P USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 22 www.anpec.com.tw APA2068 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 23 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APA2068 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.8 - May., 2012 24 www.anpec.com.tw