APA2070 Stereo 2.6W Audio Power Amplifier (with DC Volume Control) General Description Features • • • • • • • • • • • Low Operating Current about 9mA (typical) The APA2070 is a monolithic integrated circuit, which Improved Depop Circuitry to Eliminate Turn-on and Turn-off Transients in Outputs 32-Step Volume Adjustable by DC Voltage with Hysteresis Output Power at 1% THD+N - 2.4W, at VDD=5V, BTLMode, RL=3Ω - 2W, at VDD=5V, BTLMode, RL=4Ω at 10% THD+N - 3.1W, at VDD=5V, BTLMode, RL=3Ω - 2.6W, at VDD=5V, BTLMode, RL=4Ω Two Output Modes: BTL and SE Modes Selected by SE/BTL Pin Low Current Consumption in Shutdown Mode (1µA, typical) Short Circuit Protection Thermal Shutdown Protection and Over-Current Protection Circuitry The OUTP Signal and the INN Signal are Outphase Power Enhanced Package (DIP-16/DIP-16A) Lead Free and Green Devices Available (RoHS Compliant) provides precise DC volume control, and a stereo bridged audio power amplifiers capable of producing 2.6W (2W) into 4Ω with less than 10% (1.0%) THD+N. The attenuator range of the volume control in APA2070 is from 18dB (VVOLUME=0V) to -80dB (VVOLUME=3.54V) with 32 steps. The advantage of internal gain setting can be less components and PCB area. Both the depop circuitry and the thermal shutdown protection circuitry are integrated in the APA2070, that reduce pops and clicks noise during power up or shutdown mode operation. It also improves the power off pop noise and protects the chip being destroyed by over temperature and short current failure. To simplify the audio system design, the APA2070 combines a stereo bridge-tied load (BTL) mode for speaker drive and a stereo single-end (SE) mode for headphone drive into a single chip, where both modes are easily switched by the SE/BTL input control pin signal. Applications • • Simplified Application Circuit L-CH Input LINN R-CH Input RINN Notebook PC LCD Monitor or TV LOUTP Stereo Speaker Stereo Headphone LOUTN APA2070 ROUTP DC Volume Control VOLUME ROUTN ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 1 www.anpec.com.tw APA2070 Ordering and Marking Information Package Code J : DIP-16 / DIP-16A Operating Ambient Temperature Range I : - 40 to 85 oC Handling Code TU : Tube Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APA2070 Assembly Material Handling Code Temperature Range Package Code APA2070 J : APA2070 XXXXX XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration SHUTDOWN BYPASS RINN GND GND LINN VOLUME SE/BTL 1 2 3 4 5 6 7 8 APA2070 16 15 14 13 12 11 10 9 ROUTN VDD ROUTP GND GND LOUTP VDD LOUTN Absolute Maximum Ratings Symbol VDD (Note 1) Parameter Rating Unit -0.3 to 6 V Input Voltage (SE/BTL, SHUTDOWN, VOLUME, RINN, LINN to GND) -0.3 to VDD+ 0.3 V Output Voltage (LOUTN, LOUTP, ROUTP, ROUTN to GND) -0.3 to VDD+ 0.3 Supply Voltage (VDD to GND) TA Operating Ambient Temperature Range TJ Maximum Junction Temperature TSTG TSDR PD -40 to 85 ο 150 Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds Power Dissipation V ο -65 to +150 ο 260 ο Internally Limited C C C C W Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 2 www.anpec.com.tw APA2070 Thermal Characteristics Symbol θJA θJC Parameter Junction-to-Ambient Resistance in Free Air Junction-to-Case Resistance in Free Air Typical Value (Note 2) Unit 45 o 8 o (Note 3) C/W C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Note 3: The case temperature is measured at the center of the GND pin on the beside of the DIP-16/DIP-16A package. Recommended Operating Conditions Symbol VDD VIH VIL (Note 4) Parameter Range Supply Voltage Unit 4.5 ~ 5.5 High Level Threshold Voltage Low Level Threshold Voltage SHUTDOWN 0.4VDD ~ VDD SE/BTL 0.8VDD ~ VDD SHUTDOWN 0 ~ 1.0 SE/BTL 0 ~ 1.0 V VCIM Common Mode Input Voltage TA Ambient Temperature Range -40 ~ 80 ~ VDD-1.0 TJ Junction Temperature Range -40 ~ 125 RL Speaker Resistance RL Headphone Resistance ο C 3~ Ω 16 ~ Note 4 : Refer to the typical application circuit Electrical Characteristics Unless otherwise specified, these specifications apply over VDD=5V, VGND=0V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol IDD ISD TSTART-UP Parameter APA2070 Test Conditions Unit Min. Typ. Max. VSE/BTL =0V - 9 20 VSE/BTL=5V - 4 10 Shutdown Current VSE/BTL=0V VSHUTDOWN =0V - 1 - µA Start-Up Time from Shutdown CBYPASS=2.2µF - 1.6 - s THD+N=10%, RL=3Ω, fin=1kHz - 3.1 - THD+N =10%, RL=4Ω, fin=1kHz - 2.6 - THD+N =10%, RL=8Ω, fin=1kHz - 1.6 - THD+N =1%, RL=3Ω, fin=1kHz - 2.4 - THD+N =1%, RL=4Ω, fin=1kHz - 2 - THD+N =0.5%, RL=8Ω, fin=1kHz 1 1.3 - PO=1.2W, RL=4Ω, fin=1kHz - 0.07 - PO=0.9W, RL=8Ω, fin=1kHz - 0.08 - Supply Current mA BTL MODE. VDD=5V, GAIN=6dB (UNLESS OTHERWISE NOTED) PO THD+N Output Power Total Harmonic Distortion Pulse Noise Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 3 W % www.anpec.com.tw APA2070 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VDD=5V, VGND=0V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter APA2070 Test Conditions Unit Min. Typ. Max. BTL MODE. VDD=5V, GAIN=6dB (UNLESS OTHERWISE NOTED) (CONT.) Power Supply Rejection Ratio VDD Ripple=0.1Vrms, RL=8Ω, CBYPASS=2.2µF, fin=217Hz - 60 - dB Channel Separation CBYPASS=2.2µF, RL=8Ω, fin=1kHz - 90 - dB VOS Output Offset Voltage RL=4Ω - 5 - mV S/N Signal to Noise Ratio PO=1.1W, RL=8Ω, A_Weighting - 95 - dB PSRR Crosstalk SE MODE. VDD=5V, GAIN=0dB Po THD+N PSRR Crosstalk Output Power Total Harmonic Distortion Pulse Noise Power Supply Rejection Ratio THD+N=10%, RL=16Ω, fin=1kHz - 220 - THD+N =10%, RL=32Ω, fin=1kHz - 120 - THD+N =1%, RL=16Ω, fin=1kHz - 160 - mW THD+N =1%, RL=32Ω, fin=1kHz - 95 - PO=125mW, RL=16Ω, fin=1kHz - 0.09 - PO=65mW, RL=32Ω, fin=1kHz - 0.09 - - 60 - dB VDD Ripple =0.1Vrms, RL=32Ω, CBYPASS =2.2µF, fin=217Hz % Channel Separation CBYPASS=2.2µF, RL=32Ω, fin=1kHz - 60 - dB VOS Output Offset Voltage RL=32Ω - 5 - mV S/N Signal to Noise Ratio PO=75mW, RL=32Ω, A_Weighting - 100 - dB Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 4 www.anpec.com.tw APA2070 Typical Operating Characteristics THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD = 5V AV =12dB fin = 1kHz SE Mode RL = 4Ω 1 RL = 3Ω THD+N (%) THD+N (%) VDD = 5V AV =18dB fin = 1kHz BTL Mode RL = 8Ω 0.1 0.01 1 RL = 16Ω RL = 32Ω 0.1 0 0.5 1 1.5 2 2.5 Output Power (W) 3 0.01 3.5 0 40m VDD = 5V fin =1kHz RL =3Ω BTL Mode THD+N (%) THD+N (%) THD+N vs. Output Power 10 1 AV = 18dB VDD = 5V AV =18dB RL =3Ω BTL Mode fin = 20kHz 1 fin= 20Hz 0.1 fin= 1kHz AV = 6dB 0.01 0 1 0.5 1.5 0.1 2 2.5 3 0.05 10m 3.5 Output Power (W) THD+N vs. Frequency VDD = 5V RL =3Ω PO = 1.8W BTL Mode 1 0.1 100m Output Power (W) 1 5 THD+N vs. Frequency 10 THD+N (%) THD+N (%) 10 160m 200m 240m 120m Output Power (W) THD+N vs. Output Power 10 80m AV = 18dB VDD = 5V AV = 6dB RL =3Ω BTL Mode 1 0.1 PO = 0.9W AV = 6dB PO = 1.8W 0.01 20 100 1k 0.01 20 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 100 1k 10k 20k Frequency (Hz) 5 www.anpec.com.tw APA2070 Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 VDD = 5V f =1kHz RL =4Ω BTL Mode THD+N (%) THD+N (%) 10 1 AV = 18dB fin = 20Hz 0.1 0.1 fin = 1kHz VDD = 5V AV =18dB RL =4Ω BTL Mode 0.01 10m 100m 1 Output Power (W) AV = 6dB 0.01 fin= 20kHz 1 0 0.5 1 1.5 3 2.5 2 3.5 Output Power (W) THD+N vs. Frequency 10 THD+N vs. Frequency 10 VDD = 5V RL=4Ω PO=1.5W BTL Mode VDD = 5V AV= 6dB RL=4Ω BTL Mode 1 THD+N (%) THD+N (%) 1 AV = 6dB 0.1 PO = 0.8W 0.1 PO = 1.5W AV = 18dB 0.01 20 100 0.01 20 10k 20k 1k 100 Frequency (Hz) THD+N (%) THD+N (%) 10 VDD = 5V fin= 1kHz RL=8Ω BTL Mode 1 AV = 6dB 0.1 10k 20k VDD = 5V AV = 18dB RL=8Ω BTL Mode 1 fin = 20kHz fin = 20Hz 0.1 AV = 18dB 0.01 1k Frequency (Hz) THD+N vs. Output Power THD+N vs. Output Power 10 5 0 0.5 1 1.5 fin = 1kHz 2 2.5 3 0.01 10m 3.5 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 6 100m 1 Output Power (W) 5 www.anpec.com.tw APA2070 Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Frequency 10 VDD = 5V AV = 6dB RL=8Ω BTL Mode THD+N (%) THD+N (%) 10 1 1 PO = 0.5W 0.1 VDD=5V RL=8Ω PO=0.9W BTL Mode AV = 6dB 0.1 AV = 18dB PO = 0.9W 0.01 20 100 1k Frequency (Hz) 0.01 10k 20k 20 THD+N vs. Output Power THD+N (%) THD+N (%) 1 AV = 0dB VDD=5V AV=12dB RL=16Ω CO=1000µF 1 SE Mode fin = 20kHz 0 fin = 1kHz 0.01 40m 80m 120m 160m 200m 240m 10m 50m 100m 200m 300m Output Power (W) Output Power (W) THD+N vs. Frequency THD+N vs. Frequency 10 VDD=5V RL=16Ω PO=125mW CO=1000µF 1 SE Mode THD+N (%) THD+N (%) 10 AV = 0dB VDD=5V AV=0dB RL=16Ω CO=1000µF 1 SE Mode PO = 125mW 0.1 0.1 PO = 60mW AV = 12dB 0.01 fin = 20Hz 0.1 AV = 12dB 0.01 10k 20k 10 VDD=5V fin=1kHz RL=16Ω SE Mode 0.1 1k Frequency (Hz) THD+N vs. Output Power 10 100 20 100 1k 0.01 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 7 20 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2070 Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 VDD=5V fin=1kHz RL=32Ω SE Mode THD+N (%) 1 AV = 0dB 1 VDD=5V AV=12dB RL=32Ω CO=1000µF SE Mode fin = 20Hz fin = 20kHz 0.1 0.1 AV = 12dB 0.01 40m 0 80m fin = 1kHz 0.01 10m 120m 160m 200m 240m Output Power (W) THD+N vs. Frequency VDD=5V AV=12dB RL=32Ω CO=1000µF 1 SE Mode THD+N (%) THD+N (%) THD+N vs. Frequency VDD=5V RL=32Ω PO=65mW CO=1000µF SE Mode 1 AV = 0dB PO = 30mW 0.1 0.1 AV = 14dB 20 100 PO = 65mW 1k Frequency (Hz) 0.01 20 10k 20k 100 +220 +16 +180 Phase( 6dB) +8 +0 +140 VDD=5V RL=4Ω PO=0.8W BTL Mode 10 100 Amplitude( 6dB) 1k 10k Phase( 14dB) 8 +180 Phase( 6dB) +8 +0 10 +60 200k +220 +12 +4 +100 Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 +260 Amplitude( 14dB) Amplitude(dB) Amplitude(dB) +260 Phase( 14dB) +12 10k 20k Frequency Response +20 Phase (Degrees) Amplitude( 14dB) +16 1k Frequency (Hz) Frequency Response +20 +4 200m300m 10 10 0.01 100m 50m Output Power (W) +140 VDD=5V RL=8Ω PO=0.5W BTL Mode 100 Amplitude( 6dB) 1k 10k Frequency (Hz) Phase (Degrees) THD+N (%) 10 +100 200k +60 www.anpec.com.tw APA2070 Typical Operating Characteristics (Cont.) Frequency Response Frequency Response +14 +10 +180 Phase(0dB) 0 +140 Amplitude(0dB) VDD=5V RL=16Ω CO=1000µF PO=60mW SE Mode -4 -8 10 100 1k 10k Frequency (Hz) 200k +180 +4 Phase(0dB) +140 0 +100 -4 +60 -8 Amplitude(0dB) VDD=5V RL=32Ω CO=1000µF PO=30mW SE Mode 10 100 Crosstalk vs. Frequency VDD=5V RL=8Ω PO=0.9W BTL Mode -50 -60 -70 -80 -90 -100 Right to Left Left to Right -110 -120 20 100 1k +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -30 100 1k Frequency (Hz) VDD=5V RL=16Ω CO=1000µF PO=125mW SE Mode -10 -20 -40 Right to Left -60 Left to Right -30 -50 -80 -80 -90 -90 -100 20 -100 Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 9 Right to Left -60 -70 10k 20k VDD=5V RL=32Ω CO=1000µF PO=65mW SE Mode -40 -70 100 1k Frequency (Hz) 10k 20k Crosstalk vs. Response +0 -50 +60 Left to Right -120 20 10k 20k Crosstalk(dB) Crosstalk(dB) -20 200k Right to Left Crosstalk vs. Response -10 1k 10k Frequency (Hz) VDD=5V RL=4Ω PO=1.5W BTL Mode Frequency (Hz) +0 +100 Crosstalk vs. Frequency Crosstalk(dB) Crosstalk(dB) +0 -10 -20 -30 -40 +220 Phase(12dB) Phase (Degrees) +4 Amplitude(dB) Phase(12dB) Phase (Degrees) Amplitude(dB) +220 +260 Amplitude(12dB) Amplitude(12dB) +10 +260 +14 Left to Right 20 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2070 Typical Operating Characteristics (Cont.) Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency 100µ Output Noise Voltage(dB) Output Noise Voltage(dB) 100µ Filter BW<22kHz 20µ A-weighting 10µ VDD=5V AV=6dB RL=4Ω BTL Mode 1µ 20 100 1k 20µ Filter BW<22kHz 10µ A-weighting 1µ 20 10k 20k VDD=5V AV=0dB RL=32Ω SE Mode 100 Frequency (Hz) PSRR vs. Frequency PSRR vs. Frequency +0 PSRR(dB) VDD=5V RL=4Ω VIN=200mV AV=18dB BTL Mode -10 -20 -30 PSRR(dB) -20 -30 -40 -50 -60 -60 -80 -80 -90 -90 100 1k Frequency (Hz) -100 20 10k 20k Mute Attenuation vs. Frequency +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 100 1k Frequency (Hz) 10k 20k Shutdown Attenuation vs. Frequency +0 VDD=5V RL=8Ω VIN=1Vrms AV=6dB BTL Mode Shutdown Attenuation(dB) Mute Attenuation(dB) -50 -70 20 VDD=5V RL=32Ω VIN=200mV AV=12dB SE Mode -40 -70 -100 10k 20k Frequency (Hz) +0 -10 1k -10 -20 -30 -40 VDD=5V RL=8Ω VIN=1Vrms AV=6dB BTL Mode -50 -60 -70 -80 -90 -100 -110 20 100 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 10k -120 20 20k 10 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2070 Typical Operating Characteristics (Cont.) Gain vs. Volume Voltage 20 10.0 10 0 9.0 Supply Current (mA) No Load Down -10 Gain(dB) Supply Current vs. Supply Voltage -20 Up -30 -40 -50 -60 VDD=5V -70 No Load BTL Mode -80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 BTL 8.0 7.0 6.0 5.0 SE 4.0 3.0 2.0 3.0 3.5 DC Voltage (V) 200 1.8 180 RL=3Ω 1.6 1.4 RL=4Ω 1.2 1.0 0.8 RL=8Ω 0.6 0.4 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 5.5 RL=8Ω 160 140 120 RL=16Ω 100 80 RL=32Ω 60 40 VDD=5V BTL Mode 0.2 5.0 Power Dissipation vs. Output Power 2.0 Power Dissipation(W) Power Dissipation(W) Power Dissipation vs.Output Power 4.0 4.5 Supply Voltage(V) VDD=5V SE Mode 20 0 3.5 Output Power (W) 0 50 100 150 200 Output Power(mW) 250 Output Power vs. Supply Voltage 4.0 Output Power (W) 3.5 3.0 RL=3Ω,THD+N=10% RL=4Ω,THD+N=10% RL=3Ω,THD+N=1% 2.5 2.0 1.5 1.0 0.5 0.0 BTL Mode RL=8Ω,THD+N=1% AV=6dB RL=8Ω,THD+N=10% RL=4Ω,THD+N=1% 4.50 4.75 5.00 5.25 Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 5.50 11 www.anpec.com.tw APA2070 Pin Description PIN FUNCTION NO. NAME 1 SHUTDOWN 2 BYPASS 3 RINNN 4,5,12,13 GND Ground connection. Connect all of the GND pins to ground plane. 6 LINN Left channel input terminal 7 VOLUME 8 SE/BTL Output mode control input, high for SE output mode and low for BTL mode. 9 LOUTN Left channel negative output in BTL mode and high impedance in SE mode. 10,15 VDD 11 LOUTP Left channel positive output in BTL mode and SE mode. 14 ROUTP Right channel positive output in BTL mode and SE mode. 16 ROUTN Right channel negative output in BTL mode and high impedance in SE mode. Shutdown control pin. Pulling low the voltage on this pin shuts off the IC. In shutdown mode, the IC only draws 1µA (typical) of supply current. Bypass capacitor connection pin for the bias voltage generator. Right channel input terminal DC voltage input pin for internal volume gain setting (DC Volume control). Supply voltage input pin. Connect all of the VDD pins to supply voltage. Block Diagram LOUTP LINN DC Volume Control LOUTN RINN Bias Voltage Generator BYPASS ROUTP VOLUME ROUTN SE/BTL SHUTDOWN SE/BTL Mode Selection VDD Power and Depop circuit Shutdown circuit Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 12 GND www.anpec.com.tw APA2070 Typical Application Circuit VDD CS 0.1µ F VDD 100 µ F GND CCL LOUTP CiL 1 µF L-CH Input 220µF LINN CiR 1 µF 4Ω SHUTDOWN Sleeve Tip Headphone Jack CCR 220 µ F 100kΩ Shutdown Signal 2.2 µF VOLUME SE/BTL SE/BTL Signal BYPASS ROUTP VDD 100kΩ Control Pin Ring CBYPASS Bias Voltage Generator 50kΩ 1kΩ LOUTN RINN R-CH Input VDD 4Ω DC Volume Control SE/BTL Mode Selection 1kΩ ROUTN Shutdown circuit Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 13 www.anpec.com.tw APA2070 DC Volume Control Table_BTL Mode G a in(dB) V o ltage Range (% of V D D ) V o ltage Range (V D D = 5 V ) H igh(%) L o w (%) Recommended (%) H igh(V) L o w (V) Recommended (V) 18 2.40 0 .00 0 .00 0 .12 0 .00 0.00 17.5 4.60 3 .40 4 .00 0 .23 0 .17 0.20 17 6.80 5 .60 6 .20 0 .34 0 .28 0.31 16.5 9.20 7 .80 8 .60 0 .46 0 .39 0.43 16 11.40 10.20 10.80 0 .57 0 .51 0.54 15.5 13.80 12.40 13.00 0 .69 0 .62 0.65 15 16.00 14.60 15.40 0 .80 0 .73 0.77 14.5 18.20 16.80 17.60 0 .91 0 .84 0.88 14 20.60 19.20 19.80 1 .03 0 .96 0.99 13 22.80 21.40 22.00 1 .14 1 .07 1.10 12 25.00 23.60 24.40 1 .25 1 .18 1.22 10 27.40 25.80 26.60 1 .37 1 .29 1.33 8 29.60 28.20 28.80 1 .48 1 .41 1.44 6 31.80 30.40 31.20 1 .59 1 .52 1.56 4 34.20 32.60 33.40 1 .71 1 .63 1.67 2 36.40 34.80 35.60 1 .82 1 .74 1.78 0 38.60 37.00 37.80 1 .93 1 .85 1.89 -2 41.00 39.40 40.20 2 .05 1 .97 2.01 -4 43.20 41.60 42.40 2 .16 2 .08 2.12 -7 45.60 43.80 44.60 2 .28 2 .19 2.23 -1 0 47.80 46.00 47.00 2 .39 2 .30 2.35 -1 3 50.00 48.40 49.20 2 .50 2 .42 2.46 -1 6 52.40 50.60 51.40 2 .62 2 .53 2.57 -1 9 54.60 52.80 53.80 2 .73 2 .64 2.69 -2 2 56.80 55.00 5 6.00 2 .84 2 .75 2.80 -2 5 59.20 57.40 58.20 2 .96 2 .87 2.91 -2 8 61.40 59.60 60.40 3 .07 2 .98 3.02 -3 1 63.60 61.80 62.80 3 .18 3 .09 3.14 -3 4 66.00 64.00 65.00 3 .30 3 .20 3.25 -3 7 68.20 66.40 67.20 3 .41 3 .32 3.36 -4 0 70.40 68.60 69.60 3 .52 3 .43 3.48 -8 0 100.00 70.80 100.00 5 .00 3 .54 5.00 Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 14 www.anpec.com.tw APA2070 Function Description Bridge-Tied Load (BTL) Operation Single-Ended (SE) Operation The APA2070’s output stage of each channel, which consists of one pair of operational amplifiers, provides op- To consider the single-supply SE configuration shown in Typical Application Circuit, a coupling capacitor is required tion for BTL operation shown as figure 1. to block the DC offset voltage from reaching the load. These capacitors can be quite large (approximately 33µF to 1000µF) so they tend to be expensive, occupy valuable PCB area, and have the additional drawback of limiting OUTP Volume Control amplifier output signal low-frequency performance of the system (refer to the Output Coupling Capacitor). The rules described still hold OP1 with the addition of the following relationship: RL OUTN Bias Voltage Generator 1 Cbypass x 150kΩ OP2 ≤ 1 << 1 2RiCi 2RLCC (1) SE/BTL Mode Selection Function Figure 1: APA2070 Internal Configuration (each channel) The best saving features of APA2070 is that it can be The power amplifier’s (OP1) gain is set by internal unity switched easily between BTL and SE modes. This feature eliminates the requirement for an additional head- gain and input audio signal comes from internal volume control amplifier while the second amplifier (OP2) is in- phone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone ternally fixed in a unity-gain, inverting configuration. Figure 1 shows that the output of OP1 is connected to the or speakers must be accommodated. Inside of the APA2070, two separated amplifiers drive input to OP2, which results in the output signals of with both amplifiers with identical in magnitude but out of phase OUTP and OUTN (See Figure 1). The SE/BTL input controls the operation of the follower amplifier that drives 180°. Consequently, the differential gain for each channel is 2 x (Gain of SE mode). LOUTP and ROUTN. • By driving the load differentially through outputs OUTP and OUTN, an amplifier configuration is commonly re- • ferred to bridged mode is established. BTL mode operation is different from the classical single-ended (SE) am- When SE/BTL keeps high, the OP2 is in a high output impedance state, which configures the APA2070 as SE driver from OUTP. IDD is reduced by approximately one-half in SE mode. plifier configuration where one side of its load is connected to the ground. A BTL amplifier design has a few distinct advantages over Control of the SE/BTL input can be a logic-level TTL source or a resistor divider network or the stereo headphone the SE configuration, as it provides differential drive to the load, thus, doubles the output swing for a specified sup- jack with switch pin as shown in the Typical Application Circuit. ply voltage. When placed under the same conditions, a BTL amplifier has four times the output power of a SE ampifier. A BTL 1kΩ VDD configuration, such as the one used in APA2070, also creates a second advantage over SE amplifiers. Since 100kΩ Control Pin Ring SE/BTL the differential outputs, ROUTP, ROUTN, LOUTP, and LOUTN, are biased at half-supply, it’s not necessary for Tip DC voltage to be across the load. This eliminates the need for an output coupling capacitor which is required in Sleeve Headphone Jack Figure 2: SE/BTL Input Selection by Phonejack Plug a single supply, SE configuration. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 When SE/BTL keeps low, the OP2 turns on and the APA2070 is in the BTL mode. 15 www.anpec.com.tw APA2070 Function Description (Cont.) SE/BTL Mode Selection Function (Cont.) For the highest accuracy, the voltage shown in the ‘recommended voltage’column of the table is used to select In Figure 2, input SE/BTL operates as below: When the phonejack plug is inserted, the 1kΩ resistor is a desired gain. This recommended voltage is exactly halfway between the two nearest transitions. The gain levels disconnected and the SE/BTL input is pulled high to enable the SE mode. Meanwhile, the OUTN amplifier is shut are 32 steps from 18dB to -40dB in BTL mode, and the last step at -80dB as mute mode. down which turns the speaker to be mute. The OUTP amplifier then drives through the output capacitor into the Shutdown Function headphone jack. When there is no headphone plugged into the system, the contact pin of the headphone jack is In order to reduce power consumption while not in use, the APA2070 contains a shutdown pin to externally turn connected from the signal pin, and the voltage divider is set up by resistors 100kΩ and 1kΩ. Resistor 1kΩ then is off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the pulled low the SE/BTL pin, enabling the BTL function. SHUTDOWN pin. The trigger point between a logic high and logic low level is typically 2.0V. It would be better to DC Volume Control Function switch between the ground and the supply VDD to provide maximum device performance. The APA2070 has an internal stereo volume control that setting is the function of the DC voltage applied to the By switching the SHUTDOWN pin to low, the amplifier VOLUME input pin. The APA2070 volume control consists of 32 steps that are individually selected by a variable DC enters a low-current state, IDD<1µA. APA2070 is in shutdown mode. On normal operation, SHUTDOWN pin is voltage level on the VOLUME control pin. The range of the steps, controlled by the DC voltage, are from 18dB pulled to high level to keep the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a defi- to -80dB. Each gain step corresponds to a specific input voltage range, as shown in table. To minimize the effect of nite voltage to avoid unwanted state changing. noise on the volume control pin, which can affect the selected gain level, hysteresis and clock delay are Thermal Protection The thermal protection circuit limits the junction temperature of the APA2070. When the junction temperature ex- implemented. The amount of hysteresis corresponds to half of the step width, as shown in the volume control ceeds T J = +150 oC, a thermal sensor turns off the amplifier, allowing the devices to cool. The thermal sen- graph. sor allows the amplifier to start-up after the junction temperature down about 125 oC. The thermal protection is APA2070 DC Volume Control Curve (BTL) 20 designed with a 25oC hysteresis to lower the average TJ during continuous thermal overload conditions, which is 10 0 increasing lifetime of the IC. Gain (dB) -10 Forward -20 -30 Over-Current Protection Backward The APA2070 monitors the output current. When the cur- -40 rent exceeds the current-limit threshold, the APA2070 turns off the output to prevent the IC from damages in over- -50 -60 current or short-circuit condition. When the over-current occurs in power amplifier, the output buffer’s current will -70 -80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 be foldbacked to a low setting level, and it will release when over-current situation is no long existence. On the DC Volume (V) contrary, if the over-current period is long enough and the IC’s junction temperature reaches the thermal protection Figure 3: Gain setting vs. VOLUME pin voltage threshold, the IC will enter thermal protection mode. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 16 www.anpec.com.tw APA2070 Application Information Input Resistance (Ri) The value of Ci must be considered carefully because it The gain for each audio input of the APA2070 is set by the internal resistors (Ri and RF) of volume control amplifier directly affects the low frequency performance of the circuit. Consider the example where Ri is 30kΩ and the specification calls for a flat bass response down to 50Hz. Equation is reconfigured below : in inverting configuration. SE Gain = A V = − RF Ri (2) Ci = R BTL Gain = -2 × F (3) Ri BTL mode operation brings the factor of 2 in the gain equation due to the inverting amplifier mirroring the volt- 1 2 π × 30 k Ω × FC (5) When varitation of input resistance (Ri) is considered, the Ci should is 0.1µF, so a value in the range of 0.047µF to 0.47µF would be chosen. A further consideration for this age swing across the load. For varying gain settings, the APA2070 generates each input resistance on figure 4. capacitor is the leakage path from the input source through the input network (Ri+RF, Ci) to the load. This leakage The input resistance will affect the low frequency performance of audio signal. The minmum input resistance is current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high 30kΩ when gain setting is 18dB and the resistance will ramp up when close loop gain below 18dB. The input gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polar- resistance has wide variation (+/-10%) caused by process variation. ized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at VDD/2. Please note that it is important to confirm the capacitor polarity in the Ri vs. Gain(BTL) 160 application. 120 Effective Bypass Capacitor (CBYPASS) 100 A power amplifier, proper supply bypassing, is critical for low noise performance and high power supply rejection. The capacitor location on the BYPASS pin should be as close to the device as possible. The effect of a larger supply bypass capacitor is to improve PSRR due to increased half-supply stability. Two critical criteria of bypass capacitor (C BYPASS ): 1 st, it depends upon des i r e d P S R R r e q u i r e m e n t s an d c l i c k - an d - p o p performance; 2 nd, the leakage current of C BYPASS will induce the voltage drop of VBYPASS (voltage of BYPASS pin), and if the VBYPASS is less than 0.49VDD, the APA2070 will enter mute condition. The value of V BYPASS can be calculated as below: Ri(KΩ) 140 80 60 40 20 0 -40 -30 -20 -10 0 Gain(BTL) 10 20 Figure 4: Input resistance vs. Gain setting Input Capacitor (Ci) In the typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the VBYPASS = 0.5VDD - ILeakage × 150k Ω Where minimum input impedance Ri (30kΩ) form a high-pass filter with the corner frequency determined in the follow- ILeakage =Leakage current of CBYPASS ing equation : FC(highpass ) = 1 2π × 30kΩ × Ci Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 (6) Therefore, it is recommended that CBYPASS ’s leakage current should be no more than 0.4µA for properly work of the APA2070. (4) 17 www.anpec.com.tw APA2070 Application Information (Cont.) Effective Bypass Capacitor (CBYPASS) (Cont.) For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance To avoid the start-up pop noise, the bypass voltage should (ESR) ceramic capacitor, typically 0.1µF, is placed as close as possible to the device VDD lead works best. For filtering rise slower than the input bias voltage and the relationship shown in equation should be maintained. 1 1 << ( C BYPASS X150k Ω ) C i X150k Ω lower-frequency noise signals, it is recommended to place a large aluminum electrolytic capacitor of 10µF or (7) greater near the audio power amplifier The capacitor is fed from a 150kΩ resistor inside of the amplifier and the 150kΩ is the maximum input resis- Optimizing Depop Circuitry tance of (Ri+RF). Bypass capacitor, CBYPASS, values of 2.2µF to 10µF ceramic or tantalum low-ESR capacitors Circuitry has been included in the APA2070 to minimize the amount of popping noise at power-up and when coming are recommended for the best TH D+N and noise performance. out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate The bypass capacitance also affects the start-up time. It is determined in the following equation: clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or Tstart up = 5X(C BYPASS X150k Ω ) the shutdown function will cause the click and pop circuitry. (8) The value of Ci will also affect turn-on pops (Refer to Output Coupling Capacitor (CC) In the typical single-supply SE configuration, an output Effective Bypass Capacitance). The bypass voltage ramp up should be slower than input bias voltage. Although the coupling capacitor (CC) is required to block the DC bias at the output of the amplifier thus preventing DC currents in bypass pin current source cannot be modified, the size of CBYPASS can be changed to alter the device turn-on time the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high- and the amount of clicks and pops. By increasing the value of CBYPASS, turn-on pop can be reduced. However, the pass filter governed by the equation. 1 FC(highpass) = 2πRLCC tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relation- (9) ship between the size of CBYPASS and the turn-on time. In a SE configuration, the output coupling capacitor (CC), is of For example, a 330µF capacitor with an 8Ω speaker would attenuate low frequencies below 60.6Hz. The main disadvantage, from a performance standpoint, is the load particular concern. This capacitor discharges through the internal 10kΩ resistors. Depending on the size of CC, the time constant impedance is typically small, which drives the low-frequency corner higher degrading the bass response. can be relatively large. To reduce transients in SE mode, an external 1kΩ resistor can be placed in parallel with the Large values of CC are required to pass low frequencies into the load. Power Supply Decoupling Capacitor (CS) internal 10kΩ resistor. The tradeoff for using this resistor is an increase in quiescent current. In most cases, choos- The APA2070 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ing a small value of Ci in the range of 0.33µF to 1µF, CBYPASS being equal to 4.7µF and an external 1kΩ resistor should be placed in parallel with the internal 10kΩ resistor should produce a virtually clickless and popless turn- ensure the output total harmonic distortion (THD+N) is as low as possible. Power supply decoupling also pre- on. vents the oscillations caused by long lead length between the amplifier and the speaker. The optimum decoupling A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain, so it is advanta- is achieved by using two different types of capacitors that target on different types of noise on the power supply geous to use low-gain configurations. leads. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 18 www.anpec.com.tw APA2070 Application Information (Cont.) BTL Amplifier Efficiency Po (W) Efficiency (%) IDD(A) VPP(V) PD (W) as being equal to the ratio of power from the power supply to the power delivered to the load. 0.25 31.25 0.16 2.00 0.55 The following equations are the basis for calculating amplifier efficiency. 0.50 47.62 0.21 2.83 0.55 1.00 66.67 0.30 4.00 0.5 1.25 78.13 0.32 4.47 0.35 An easy-to-use equation to calculate efficiency starts out PO P SUP Efficiency = (10) Where PO = VO,RMS 2 RL VO, RMS = = **High peak voltages cause the THD+N to increase. VP2 Table 1. Efficiency vs. Output Power in 5-V/8Ω BTL Systems 2R L VP P SUP = V DD × I DD , AVG = V DD × Power Dissipation Whether the power amplifier is operated in BTL or SE (11) 2 2VP πR L mode, power dissipation is the major concern. Equation (14) states the maximum power dissipation point for a (12) SE mode operating at a given supply voltage and driving a specified load. Efficiency of a BTL configuration : PO P SUP VP2 πV P 2R L = = 2VP 4V DD V DD × πR L SE mode: PD, MAX = (13) VDD2 2π2RL (14) In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus, the maximum power dis- Table 1 is for calculating efficiencies for four different out- sipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. put power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load BTL mode : PD, MAX = is increased resulting in a nearly flat internal power dissipation over the normal operating range. In addition, the 4VDD2 2π2RL (15) Since the APA2070 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific of equations depend on the mode of operation. Even with this substantial increase in power dissipation, the system is the key to proper power supply design. For a stereo 1W audio system with 8Ω loads and a 5V supply, APA2070 does not require extra heatsink. The power dissipation from equation (14), assuming a 5V-power sup- the maximum draw on the power supply is almost 3W. ply and an 8Ω load, must not be greater than the power dissipation that results from the equation (16): A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note PD, MAX = that in equation, VDD is in the denominator. This indicates that as the VDD goes down, efficiency goes up. In other TJ, MAX - TA θJA (16) For DIP-16/DIP-16A package, the thermal resistance (θJA) is equal to 45οC/W. Since the maximum junction temperature (TJ,MAX) of the APA2070 is 150οC and the ambient temperature (TA) is words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. defined by the power system design, the maximum power dissipation which the IC package is able to handle can be obtained from equation16. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 19 www.anpec.com.tw APA2070 Application Information (Cont.) Power Dissipation (Cont.) 1. All components should be placed close to the APA2070. For example, the input capacitor (Ci) should be close Once the power dissipation is greater than the maximum to APA2070’s input pins to avoid causing noise coupling to APA2070’s high impedance inputs; the limit (P D,MAX ), either the supply voltage (V DD) must be decreased, the load impedance (RL) must be increased decoupling capacitor (CS) should be placed by the APA2070’s power pin to decouple the power rail noise. or the ambient temperature should be reduced. 2. The output traces should be short, wide (>50mil), and symmetric. Thermal Consideration Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. The first consideration to calculate maximum ambient temperatures is the numbers from the Power Dissipa- 3. The input trace should be short and symmetric. 4. The power trace width should be greater than 50mil. 5. The APA2070’s GND pin should be soldered on the ground plane of the PCB. tion vs. Output Power graphs are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given θJA, the maximum allowable junction temperature (TJMAX), and the total internal dissipation (PD), the maximum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the APA2070 is 150°C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graphs. TAMax = TJMax -θJAPD (16) 150 - 45(0.8*2) = 78°C The APA2070 is designed with a thermal shutdown protection that turns the device off when the junction temperature surpasses 150°C to prevent damaging the IC. Layout Consideration Via diameter =0.3mm x 24 4mm 3mm 20mm Ground plane for GND pin 16mm Figure 5: APA 2070 Land Pattern Recommendation Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 20 www.anpec.com.tw APA2070 Package Information DIP-16 E1 D 0.38 A L A1 A2 E b D1 b2 e c eA eB S Y M B O L DIP-16 MILLIMETERS MIN. INCHES MIN. MAX. A MAX. 0.210 5.33 0.015 A1 0.38 A2 2.92 4.95 0.115 0.195 b 0.36 0.56 0.014 0.022 b2 1.14 1.78 0.045 0.070 0.014 0.800 c 0.20 0.35 0.008 D 18.6 20.31 0.732 D1 0.13 E 7.62 8.26 0.300 0.325 E1 6.10 7.11 0.240 0.280 0.005 e 2.54 BSC 0.100 BSC eA 7.62 BSC 0.300 BSC eB L 0.430 10.92 2.92 0.115 3.81 0.150 Note : 1. Followed from JEDEC MS-001AB 2. Dimension D, D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 10 mil. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 21 www.anpec.com.tw APA2070 Package Information DIP-16A E1 D 0.38 A L A1 A2 E b D1 b2 e c eA eB S Y M B O L DIP-16A MILLIMETERS MIN. A A1 INCHES MAX. MIN. MAX. 5.33 0.210 0.015 0.38 A2 2.92 4.95 0.115 0.195 b 0.36 0.56 0.014 0.022 b2 1.14 1.78 0.045 0.070 0.014 0.800 c 0.20 0.35 0.008 D 18.6 20.31 0.732 D1 0.13 E 7.62 8.26 0.300 0.325 E1 6.10 7.11 0.240 0.280 0.005 e 2.54 BSC eA 7.62 BSC eB L 0.100 BSC 0.300 BSC 0.430 10.92 2.92 0.115 3.81 0.150 Note : 1. Followed from JEDEC MS-001AB 2. Dimension D, D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 10 mil. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 22 www.anpec.com.tw APA2070 Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 23 www.anpec.com.tw APA2070 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 24 www.anpec.com.tw