RT9206 High Efficiency, Synchronous Buck with Dual Linear Controllers General Description Features The RT9206 is a low cost, combo power controller, which integrates a synchronous step-down voltage-mode PWM and two HV linear controllers. Directly drive external N-MOSFET makes it easy to implement a high efficiency and cost attractive power solution. Voltage mode control loop and constant operation frequency with external compensation network provide better stability in wide operation range. Adjustable operation frequency up to 600kHz can minimize the inductor size and PCB space. It is particularly suitable in wide input voltage range (from 4.75V to 28V) and multi-output applications. l Linear controller features flexible linear power design. Delivered power can be simply decided by external N-MOSFET selection. Output voltage level is chosen via external resistor divider. The 0.8V internal reference can satisfy most of the applications. Under voltage lockout provide cost effective protection of output. l l l l l l l l l Applications l l l l l RT9206 provides complete safety protection function: soft start, over current protection, over voltage and under voltage protection. Set current limit by choosing different MOSFET. Synchronous Buck control mode provides excellent over voltage protection by turning on low side MOSFET to prevent any damage of end device from abnormal voltage stress as over voltage condition occurs. Ordering Information RT9206 Package Type S : SOP-16 Wide Input Range (4.75V to 28V) 0.8V Internal Reference High Efficiency Synchronous Buck Topology Integrate two HV Linear Controllers Low cost N-MOSFET Design Duty Cycle from 0% to 90%. Adjustable switching frequency from 200kHz to 600kHz, Default 200kHz Sense OCP by low Side MOSFET RDS(ON) Power Good Signal Output RoHS Compliant and 100% Lead (Pb)-Free LCD Monitor Desk Note IEEE1394 Client Desktop IA Broadband Pin Configurations (TOP VIEW) LDRV1 VDD LDRV2 LFB2 COMP FB PGOOD SS/EN 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 LFB1 BOOT UGATE PHS VINT LGATE GND RT SOP-16 Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) Note : Richtek products are : } RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. } Suitable for use in SnPb or Pb-free soldering processes. DS9206-13 April 2011 www.richtek.com 1 RT9206 Typical Application Circuit R1 10 C1 1µF C15 500pF R4 3.3k R2 11k VOUT1 VOUT2 3.3V Q3 1 C16 500pF C6 10µF VOUT3 2.5V C7 10µF Q4 2 3 R3 11k 4 R11 5 5.6k 6 C14 33nF R12 4.3K 390pF C13 7 8 16 LDRV1 LFB1 RT9206 15 VDD BOOT 14 LDRV2 UGATE 13 LFB2 PHS 12 COMP VINT 11 FB LGATE 10 PGOOD GND 9 SS/EN RT Q5 R10 51k 1µF CSS D11N4148 15 RBOOT VIN 12V C3 220µF C2 1µF C9 1µF Si4800BDY Q1 L1 C10 1000µF 0 R13 C11 1µF VOUT1 5V 4.7uH C8 4.7µF 0 Q2 C17 1000µF R14 RRT R8 3k EN R9 560 PGOOD Figure 1. Typical Application for 12V Input R1 10 C1 1µF Q3 VOUT2 3.3V 1 C16 500pF C6 10µF VOUT3 2.5V C7 10µF 2 Q4 3 R3 11k 4 5 R11 6 5.6k C14 33nF R12 8.2K 220pF C13 7 8 R10 51k 16 LFB1 LDRV1 RT9206 15 VDD BOOT 14 UGATE LDRV2 13 PHS LFB2 12 COMP VINT 11 FB LGATE 10 GND PGOOD 9 RT SS/EN 4.7µF CSS VIN 24V R4 3.3k R2 11k VOUT1 C3 220µF C2 1µF C15 500pF Q5 D11N4148 15 RBOOT C9 1µF 0 R13 Si4800BDY Q1 C10 L1 1000µF VOUT1 5V 33µH C8 4.7µF 0 C11 1µF Q2 R14 RRT EN R8 3k R9 560 PGOOD Figure 2. Typical Application for 24V Input Note : R BOOT is a must to suppress ringing spike. www.richtek.com 2 DS9206-13 April 2011 RT9206 Function Block Diagram 0.8V LFB1 LFB2 LCTR2 + + 0.8V + UV - BOOT COMP + GM - PGOOD DS9206-13 April 2011 Driver Control Logic UGATE PHS VINT LGATE GND OSC RT +PWM - CP RAMP Generator Soft Start SS/EN VINT + UV + UV - 0.6V 0.8V LDRV1 Thermal Protection 0.6V FB LCTR1 LDRV2 6.0V Reg VDD 0.6V + + 8uA 1V + OVP - 0.72V PG + www.richtek.com 3 RT9206 Operation Introduction Power On Reset (POR) The RT9206 is a combo controller, which integrates an adjustable frequency, voltage mode synchronous step down controller and two HV linear controllers. The synchronous step down controller consists of an internal precision reference, an internal oscillator, an error amplifier, a PWM comparator, control logic and floating gate driver, a programmable soft-start, a power good indicator, an over voltage protection, an over temperature protection and short circuit protection. The power on reset circuit assures that the MOSFET driver outputs remain in the off state whenever the VDD supply voltages lower than the POR threshold. The output voltage of the synchronous converter is set and controlled by the output of the error amplifier, which is the amplified error signal from the sensed output voltage and the voltage on non-inverting input, which is connected with internal 0.8V reference voltage. The amplified error signal is compared to a fixed frequency linear sawtooth ramp and generates fixed frequency pulse of variable dutycycle, which drivers the two N-Channel external MOSFETs. The timing of the synchronous converter is provide through an internal oscillator circuit and can be programmed between 200kHz to 600kHz via an external resistor connected between RT pin and ground. Soft-Start RT9206 has a programmable soft-start to control the output voltage rise time and limit the current surge at the startup. The soft-start will begin while VDD rises above POR threshold for correct start-up. Soft-start function operates by an internal sourcing current to charge an external capacitor to around the voltage of VINT. The soft-start signal, SS pin, is the third input non-inverting input of the PWM comparator. Before soft-start signal reach the bottom of the sawtooth ramp, inverting input of the PWM comparator, the soft-start current is twice of the normal soft-start current. Once the soft-start signal reach the bottom of the ramp, the soft-start current became normal, and start to increase duty cycle from zero to the point the feedback loop takes control. www.richtek.com 4 Over Current Protection Whenever the over-current is occurred in soft-start or in normal operation period, It will shut down PWM signal, the MOSFET driver outputs remain in the off state, and latch soft-start signal low until restart VDD supply voltage. Over Voltage Protection Once over-voltage protection occurred, it will turn on low side MOSFET and latch soft-start signal low to prevent end device form abnormal voltage stress. Restart VDD supply voltage will release the protection. Power Good Indicator The power good indicator is an open drain output to show whether the synchronous converter output ready or not. The power good indicator is available after soft-start end. Short-Circuit Protection The short-circuit phenomenon is sensed by the drop of output voltage, synchronous converter and two linear controller. Once the short-circuit occurred, the drop of output voltage lower than the under voltage threshold, 0.6V on feedback, the PWM signal will shut down and both of the external MOSFET will turn off and soft-start signal latch low. Soft-start signal, SS, is also connected to two linear controller error amplifier non-inverting input. Therefore, whenever the drop of output of the synchronous converter or two linear controllers lower than under voltage threshold, all MOSFET drivers will turn off. DS9206-13 April 2011 RT9206 Pin Description LDRV1(Pin 1) Linear controller 1 (LCTR1) driver. Connect to the gate of external N-Channel MOSFET pass transistor to form a positive linear regulator The formula between resistor setting and operational frequency are as follows: RRT = 62 × 10 8 FOSC - 200 × 10 3 VDD (Pin 2) Input supply voltage GND (Pin 10) Ground LDRV2 (Pin 3) Linear controller 2 (LCTR2) driver. Connect to the gate of external N-Channel MOSFET pass transistor to form a positive linear regulator LGATE (Pin 11) LFB2 (Pin 4) VINT (Pin 12) LDO2 feedback input. The feedback set point is 0.8V. Connect to a resistive divider between the positive linear regulator output and GND to adjust the output voltage. Internal 6.0V regulator output. The low side gate driver and control circuit and external bootstrap diode are powered by this voltage. Decouple this pin to power ground with a 4.7uF or greater ceramic capacitor close to the VINT pin. Low side gate driver. Drives low side N-MOSFET with a voltage swing between VINT and GND COMP (Pin 5) Switching regulator compensation pin. PHS (Pin 13) FB (Pin 6) Inductor connection with (-) terminal bootstrap flying capacitor connection. Switching regulator feedback input. The feedback set point is 0.8V. Connect to a resistive divider between the switching regulator output and GND to adjust the output voltage. UGATE (Pin 14) High side gate driver. Drives high side N-Channel MOSFET with a voltage swing between BOOT and PHS PGOOD (Pin 7) Open drain power good indicator. PGOOD is low when switching regulator output voltage is lower than 10% of its regulation voltage. Connect a pull high resistor between PGOOD and switching regulator output for pull high logic level voltage. BOOT (Pin 15) High side floating driver supply with (+) terminal bootstrap flying capacitor connection. Voltage swing is from a diode drop below VINT to VIN + VINT LFB1 (Pin 16) SS/EN (Pin 8) Soft start input with 8uA sourcing current and IC enable control. LDO1 feedback input. The feed back set point is 0.8V. Connect to a resistive divider between the positive linear regulator output and GND to adjust the output voltage. RT (Pin 9) Operational frequency setting. Connect a resistor between RT and GND to set operational frequency. The operational frequency will nominally run at 200kHz when open. DS9206-13 April 2011 www.richtek.com 5 RT9206 Absolute Maximum Ratings l l l l l l l l l l l l l l l (Note 1) Supply Voltage (VIN) ------------------------------------------------------------------------------------------------ −0.3 to 30V PHS --------------------------------------------------------------------------------------------------------------------- −0.6V to 30V PHS (PHS Transient Time Interval < 50ns) --------------------------------------------------------------------- −5V BOOT, UG to PHS --------------------------------------------------------------------------------------------------- −0.3V to 7V BOOT to GND -------------------------------------------------------------------------------------------------------- −0.3V to 35V LDRI1, LDRI2 --------------------------------------------------------------------------------------------------------- −0.3V to 30V Power Good Voltage ------------------------------------------------------------------------------------------------- −0.3V to 7V The other pins -------------------------------------------------------------------------------------------------------- −0.3V to 7V Power Dissipation, PD @ TA = 25°C SOP-16 ---------------------------------------------------------------------------------------------------------------- 0.625W Package Thermal Resistance SOP-16, θJA --------------------------------------------------------------------------------------- 90°C/W Junction Temperature ----------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260°C Operation Temperature Range ------------------------------------------------------------------------------------- −20°C to 85°C Storage Temperature Range --------------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------------------- 2kV MM (Machine Mode) ------------------------------------------------------------------------------------------------ 200V Recommended Operating Conditions l l (Note 3) Ambient Temperature Range -------------------------------------------------------------------------------------- 0°C to 70°C Junction Temperature Range -------------------------------------------------------------------------------------- 0°C to 125°C Electrical Characteristics (VIN = 12V, FADJ left floating, TA = 25° C, Unless Otherwise specification) Parameter Symbol Test Condition Min Typ Max Unit 4.75 -- 28 V 4.7 V System Supply Input Operation voltage Range VDD Power On Reset POR (Note 4) 3.8 Power On Reset Hysteresis 200 -- 600 mV Supply Current IDD VDD = 30V, VSS = VINT -- 1.3 4 mA Shut Down Current IDD VDD = 30V, VSS < 0.4V -- 1 3.5 mA Power Good under Threshold VFB 82 -- 92 % PG Fault Condition VPG -- -- 0.2 V IPG = −4mA, VFB = 80% Soft-Start Soft-start Current ISS 4 8 12 µA Normal Operation Voltage VSS -- VINT -- V Shut down Voltage VSS 0.4 0.7 www.richtek.com 6 -V To be continued DS9206-13 April 2011 RT9206 Parameter Symbol Test Condition Min Typ Max Unit 0.784 0.8 0.816 V PWM Section Reference Voltage Feedback Voltage VFB Internal Voltage VINT IINT = 10mA 5.0 6 6.5 V Internal Voltage Source Current IINT VIN = 12V 20 -- -- mA 160 200 240 kHz −30 -- 30 % Ramp Amplitude -- 1.9 -- V Maximum Duty Cycle 85 90 -- % GM -- 1.6 -- ms Compensation Source Current 45 90 140 µA Compensation Sink Current 45 90 140 µA PWM Section Oscillator Free Run Frequency FOSC Operation Frequency Setting FOSC By setting RT (Note 5) Error Amplifier Gate Driver Upper Gate Source (UGATE1 & 2) RUGATE -- 5 8 Ω Upper Gate Sink (UGATE1 & 2) RUGATE -- 5 8 Ω Lower Gate Source (LGATE1 & 2) RLGATE -- 3 5 Ω Lower Gate Sink (LGATE1 & 2) RLGATE -- 1.5 3 Ω Upper Gate Rising Time TR_UGATE VDD = 12V, CLOAD = 3nF -- 30 -- ns Upper Gate Falling Time TF_UGATE VDD = 12V, CLOAD = 3nF -- 30 -- ns Lower Gate Rising Time TR_LGATE VDD = 12V, CLOAD = 3nF -- 30 -- ns Lower Gate Falling Time TF_LGATE VDD = 12V, CLOAD = 3nF -- 30 -- ns -- -- 400 ns −270 −300 −330 mV Minimum On Time Protection Over Current Threshold Over Voltage Protection VFB 0.9 1 1.1 V Under Voltage Protection VFB 0.54 0.6 0.66 V Linear Controller Section Error Amplifier Feedback Voltage LFB1 / LFB2 0.780 0.8 0.824 V Output Current LDRV1 / LDRV2 10 -- -- mA 0.54 0.6 0.66 V 125 170 -- °C Protection Under Voltage Protection Over Temperature Protection DS9206-13 April 2011 LFB1 / LFB2 www.richtek.com 7 RT9206 Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution is recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. V DD − V OUT2 or VDD − V OUT3 must be higher than 4V to keep linear controller operation Note 5. RRT = 62 × 10 8 FOSC - 200 × 10 3 Note 6. The LDOs are not suitable for low noise applications www.richtek.com 8 DS9206-13 April 2011 RT9206 Typical Operating Characteristics Power On Power On IOUT1 = 4A IOUT2 = 0.5A IOUT3 = 0.5A 2V/Div 10V/Div 5V/Div VIN VIN 2V/Div 2V/Div VOUT1 VOUT1 2V/Div VOUT2 VOUT3 VOUT2 2V/Div 2V/Div VOUT3 5V/Div 5V/Div PGOOD PGOOD VIN = 24V, f = 200kHz VIN = 12V, f = 200kHz Time (100ms/Div) Time (200ms/Div) Power Off Power Off IOUT1 = 4A IOUT2 = 0.5A IOUT3 = 0.5A 5V/Div IOUT1 = 4A IOUT2 = 0.5A IOUT3 = 0.5A IOUT1 = 4A IOUT2 = 0.5A IOUT3 = 0.5A 20V/Div VIN 5V/Div 5V/Div VIN VOUT1 VOUT2 VOUT1 2V/Div 2V/Div VOUT3 2V/Div VOUT3 VOUT2 PGOOD 5V/Div PGOOD 5V/Div VIN = 24V, f = 200kHz VIN = 12V, f = 200kHz Time (20ms/Div) Time (20ms/Div) Bootstrap Wave Form Bootstrap Wave Form 10V/Div BOOT 2V/Div 20V/Div BOOT 10V/Div 5V/Div PHS PHS 10V/Div 20V/Div UGATE UGATE 5V/Div 20V/Div LGATE LGATE VIN = 24V VIN = 12V Time (1μs/Div) DS9206-13 April 2011 Time (1μs/Div) www.richtek.com 9 RT9206 Dead Time Dead Time LGATE LGATE 2V/Div 2V/Div UGATE UGATE UGATE 5V/Div 10V/Div VIN = 12V, IOUT1 = 4A VIN = 24V, IOUT1 = 4A Time (20ns/Div) Time (20ns/Div) Dead Time Dead Time UGATE 5V/Div 10V/Div LGATE LGATE 2V/Div 2V/Div VIN = 12V, IOUT1 = 4A VIN = 24V, IOUT1 = 4A Time (20ns/Div) Time (20ns/Div) Dynamic Loading Dynamic Loading UGATE UGATE 10V/Div 10V/Div LGATE LGATE 5V/Div 5V/Div VOUT1 100mV/Div VOUT1 100mV/Div IOUT1 5A/Div VIN = 12V Time (10μs/Div) www.richtek.com 10 IOUT1 5A/Div VIN = 12V Time (10μs/Div) DS9206-13 April 2011 RT9206 Soft Start vs. Temperature Short Latch 6.1 VIN = 12V f = 200kHz VIN = 12V 6.05 UGATE 20V/Div 2V/Div VSS (V) 6 5.95 5.9 VOUT1 5.85 10A/Div IL 5.8 -50 Time (20μs/Div) -25 0 25 50 75 100 125 150 Temperature (°C) Oscillator Frequency vs. Temperature Reference Voltage vs. Temperature 0.82 240 235 VIN = 12V RT = floating VIN = 12V f = 200kHz 0.815 0.81 225 220 V REF (V) Frequency (kHz)1 230 215 210 205 0.805 0.8 0.795 200 0.79 195 190 0.785 -50 -25 0 25 50 75 100 125 150 -50 -25 0 Temperature (°C) 50 75 100 125 150 Temperature (°C) POR(Rising/Falling) vs. Temperature Quiescent Current vs. Input Voltage 5 1055 VIN = 12V f = 200kHz 4.75 Rising 4 3.75 3.5 Falling 3.25 VSS = 0V Quiescent Current (uA) 4.5 4.25 POR (V) 25 3 2.75 2.5 1050 1045 1040 1035 1030 2.25 2 1025 -50 -25 0 25 50 75 100 Temperature (°C) DS9206-13 April 2011 125 150 0 4 8 12 16 20 24 28 32 VIN (V) www.richtek.com 11 RT9206 Efficiency vs. Load Current Fosc vs. RRT 96 800 600 94 Efficiency (%) A Operation Frequency (kHz) VIN = 12V 700 500 400 300 92 VIN = 12V 90 VIN = 24V 88 86 84 200 VOUT = 5V Frequency = 200kHz 82 100 80 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 RRT (kΩ) 0 1 2 3 4 5 6 7 Load Current (A) Over Current Threshold vs. Temperature 450 Over Current Threshold (mV) (-mV)1 VIN = 12V 400 350 300 250 200 -50 -25 0 25 50 75 100 125 150 Temperature (°C) www.richtek.com 12 DS9206-13 April 2011 RT9206 Application Information Synchronous Buck Converter is1 The RT9206 is specifically designed for synchronous buck converter with wide input voltage from 4.75V to 28V and operating frequency from 200kHz to 600kHz. To fully utilize its advantages, peripheral components should be appropriately selected. The following information provides basic considerations for component selection. is2 Output Inductor Selection The selection of output inductor is based on the considerations of efficiency, output power and operating frequency. Low inductance value has smaller size, but results in low efficiency, large ripple current and high output ripple voltage. Generally, an inductor that limits the ripple current (∆IL) between 20% and 50% of output current is appropriate. Figure 1 shows the typical topology of synchronous step-down converter and its related waveforms. iS1 L iS2 VIN According to Figure 1 the ripple current of inductor can be calculated as follows : VIN - VOUT = L ΔIL + VL - ; Δt = D ;D = fs VOUT VIN VOUT (1) VIN × fs × ΔIL Where : iC IOUT + rC VIN = Maximum input voltage VOUT = Output Voltage RL S2 VOUT + + VOC - Δt L = (VIN - VOUT) × iL + VOR - S1 Figure 1.The waveforms of synchronous step-down converter COUT ∆t = S1 turn on time ∆IL = Inductor current ripple - f S = Switching frequency D = Duty Cycle Ts rC = Equivalent series resistor of output capacitor V g1 T on T off Output Capacitor Selection V g2 V IN -V OUT VL -V OUT The selection of output capacitor depends on the output ripple voltage requirement. Practically, the output ripple voltage is a function of both capacitance value and the equivalent series resistance (ESR) rC. Figure 2 shows the related waveforms of output capacitor. iL IL =IOUT ΔIL DS9206-13 April 2011 www.richtek.com 13 RT9206 d iL VIN-VOUT = iL dt VOUT d iL dt = L Input Capacitor Selection L The selection of input capacitor is mainly based on its maximum ripple current capability. The buck converter draws pulsewise current from the input capacitor during the on time of S1 as shown in Figure 1. The RMS value of ripple current flowing through the input capacitor is described as : IO TS ic 1/2ΔIL ΔIL 0 Irms = IO D(1- D) (A) (6) The input capacitor must be cable of handling this ripple current. Sometime, for higher efficiency the low ESR capacitor is necessarily. VOC ΔVOC Power MOSFET Selection VOR ΔIL x r c 0 t1 t2 Figure 2. The related waveforms of output capacitor. The AC impedance of output capacitor at operating frequency is quite smaller than the load impedance, so the ripple current ( ∆IL) of the inductor current flows mainly through output capacitor. The output ripple voltage is described as : (2) ΔVOUT = ΔVOR + ΔVOC ΔVOUT = ΔIL × rC + 1 Co The selection of MOSFETs is based on consideration of maximum gate-source voltage (Vgs), drain-source voltage (Vdss), maximum drain current (Id), drain-source on-state resistance R DS(ON) and thermal management. The MOSFETs are driven by VINT that is internally regulated as 6.0V. Low threshold voltage MOSFET should be selected to guarantee that it could fully turn on at Vgs = 6.0V. The total power dissipation of external MOSFETs consists of conduction and switching losses. The conduction losses of high side and low side MOSFETs are described by equation (7) and (8), respectively. (High-side MOSFET) PH-CON = I20 × D × RDS(ON) × θr (W) (7) (Low-side MOSFET) t2 t1 ∫ ic d t (3) PL-CON = I20 × (1-D) × RDS(ON) × θr (W) (8) Where ΔVOUT = ΔIL × rC + 1 VOUT 8 COL 2 S (1- D)T (4) where ∆VOR is caused by ESR and ∆VOC by capacitance. For electrolytic capacitor application, typically 90~95% of the output voltage ripple is contributed by the ESR of output capacitor. So Equation (4) could be simplified as : ΔVOUT = ΔIL × rC (5) Users could connect capacitors in parallel to get calculated ESR. θ r is temperature dependency of Rds(on) The total switching loss is approximated as. VDS(OFF) PSW = IOUT × × (tr + tf) × fs (W) 2 Where (9) VDS(OFF) is voltage from drain to source at MOSFET off time. tr and tf are rise-time and fall-time, respectively. IOUT = Load current f s = Switching frequency www.richtek.com 14 DS9206-13 April 2011 RT9206 The MOSFET should be capable of handling the power loss over the entire operating range. Ra Design Example: VIN = 12V, VOUT = 5V, IOUT = 5A, ∆VOUT < 25mV, switching frequency = 200kHz, to determine the value of inductor and output capacitor (Using electrolytic capacitor). First, select ripple current of inductor is 20% of output current, from equation (1) 5 12 × 200K × 0.2 × 5 = 14.58 µ H Select L = 15µH 25mV=1 x rC Select two electrolytic capacitors C = 470µF,rC = 43mΩ in parallel. Setting the Current Limit The RT9206 limits output current by sensing low side MOSFET voltage drop (VSD) when it turns on. The drop voltage caused by on-state resistance RDS(ON) is described as : VSD=RDS(ON) x IL (10) When VSD >300mV, the current limit function will be activated and latch the controller. So the current limit function can be set by MOSFETs selection. The relation of maximum inductor current IL(LIM) and on-state resistance of MOSFET (RDS(ON)) is described as : -3 300 × 10 (Ω) (11) RDS(ON) = IL(LIM) The output voltage is set by external voltage divider and reference voltage. The feedback pin (FB, LFB1, and LFB2) is connected to the inverting input of error amplifier and is referenced to 0.8V reference voltage at non-inverting input as shown in Figure 3.The output voltage is set by the following equation. Rb ) × 0.8 DS9206-13 April 2011 + Rb 0.8V Figure 3. The connected diagram of external voltage divider and reference voltage If high value resistors are used, the input bias current of FB pin could cause a slight increase in output voltage. The output voltage set point can be more accurate by using precision resistor. Figure 4 shows the typical soft-start timing waveforms of RT9206. The soft-start time of Buck converter can be set by selecting the soft-start capacitance value. The delay time between input voltage applied and output voltage starting to ramp up (TDELAY) is calculated as: The total time from input voltage applied to output voltage buildup (TVR) is calculated as : TVR = 57 × CSS × 10 6 (ms) (13) The effective soft-start time (TSS) during that output voltage ramps up from zero to set voltage is calculated as : TSS = (320 × VOUT VIN ) × 10 × CSS (ms) 6 (14) Besides, appropriate soft-start capacitor should be selected so that the start-up current will not trigger the current limit function. And make sure that the input power source could supply the soft-start current. Setting the Output voltage Ra (LFB1,LFB2) Soft-start setting From equation (5) VOUT = (1+ - FB Design the power stage for a synchronous step-down converter having the following specifications: L = (12 - 5) × VOUT The total time from input voltage applied to power good signal pull-high (TPGOOD) is calculated as : TPG = 640 × CSS × 10 6 (ms) (15) (12) www.richtek.com 15 RT9206 Boost Component Selection VDD VSS The booststrap gate drive circuit is used to drive high side N-channel MOSFET. The boost capacitor should be a good quality and can operate in high frequency. The value of boost capacitor depends on the total gate charge (QHg) to turn on the MOSFETs. Assuming steady state operation, the following equation can be used to calculate the capacitance value to achieve the targeted ripple voltage ∆VBOOT . VOUT PGOOD TVR TSS CBOOT = TPGOOD QHg (F) ΔVBOOT Figure 4. The soft-stat timing diagram of RT9206 The capacitor in the range of 0.1µF to 1µF is generally adequate for most applications. For the example of CSS = 1µF, VIN = 12V, VOUT = 5V, then TVR = 57ms, TSS = 133ms and TPGOOD = 640ms. The VINT pin bypass capacitor CINT needs to charge the boost capacitor, to drive the low side MOSFET, and to power the RT9206. CINT should locate near VINT and GND pins with short and wide traces. Generally, a 4.7µF high frequency ceramic capacitor is recommended. Shutdown The power stage can be shutdown by pulling soft-start pin below 0.7V. During shutdown, both of high side MOSFET (S1) and low side MOSFET (S2) are turned off. Setting the switching frequency The switching frequency can be set by a resistor (RRT ) connecting between RT and GND pins. Equation (16) describes the relationship of RRT and switching frequency. As RT open the normally operated frequency is 200kHz. RRT = 62 × 10 8 fS - 200 × 10 3 (Ω) (16) RRT Connecting Between Feedback Compensation The RT9206 is a voltage mode controller. The control loop is a single voltage feedback loop including a transconductance error amplifier and a PWM comparator. To achieve fast transient response and accurate output regulation, appropriate feedback compensation is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin. Generally, the phase margin in a range of 45° to 60° is desirable. Figure 4 shows the simplified diagram of synchronous buck converter and control loop. RT and GND Pins www.richtek.com 16 fS(kHz) RRT (kΩ) 250 120 300 55 350 37.5 400 30.6 450 24.4 500 22.5 550 19.3 600 16.8 DS9206-13 April 2011 RT9206 iS1 + VL S1 iC iS2 IOUT + + where, Vr is the amplitude of ramp-waveform which is listed in datasheet. COUT - Sensor Gain VREF Compensator d For simplification, the transfer function of PWM generator and Buck converter can is combined. The resulting is shown in equation (20) Ra VC + G(S) = + gm Cc2 PWM Generator (19) VOUT + + VOC - RL d(S) 1 = VC(S) Vr Tm(S) = rC VOR - S2 VIN Next, deriving the transfer function d(s)/vC (s) of the direct duty ratio pulse-width modulator (PWM Generator). The transfer function Tm(s) of the modulator is given by iL L VOUT(S) = VC(S) Rc1 VIN 1 + rc x CO x S x L Vr S 2 x L + CO x S( + rc x CO) + 1 RL (20) Rb Cc1 The transfer function of Equation (20) is a second order system and Bode plot is shown in Figure 7. Gain Figure 5. The simplified diagram for synchronous Buck converter and control loop. VIN/Vr From control system point of view, the block diagram of Figure 5 is shown in Figure 6. fp f fz G(S) PWM Generator Compensator VREF + C(s) Vc(s) 1/Vr BUCK Converter d(s) Gp(s) Phase VOUT - Rb H (s) -90° Ra+Rb Sensor Gain Figure 6. The control block diagram of synchronous Buck converter First, deriving the accurate small-signal models of power stage, the equation (18) is the transfer function of vO (s)/d(s), which be obtained by space averaging technique. VOUT(S) GP(S) = = d(S) f 0° 1 + rc x CO x S x VIN L 2 S x L x CO + S( + rc x CO) + 1 RL (18) DS9206-13 April 2011 -180° Figure 7. The Bode plot of Buck power stage In Figure 7, the resonance of the output LC filter produces a double pole and −40dB/decade slop. The resonance frequency is expressed as follows : fP = 1 2π x L x CO (Hz) (21) www.richtek.com 17 RT9206 The Effective Series Resistance (ESR) of capacitor and capacitance introduces one zero into system, the zero is given as : 1 fZ = (Hz) (22) 2π x rc x CO In the voltage-mode Buck converter shown in Figure 5, the loop gain of system is 1 TL(S) = C(S) x x GP(S) x H(S) = C(S) x G(S) x H(S) (23) Vr The desired loop gain and phase margin is show in the Bode plot of Figure 8. Where the f C is zero crossover frequency defined as the frequency when the loop gain equals unity. Typically, fC be chosen in range 1/10 to 1/20 of switching frequency. f C determines how fast the dynamic load response is. The higher f C with the faster dynamic response, and the phase margin in the range of 45° to 60° is desirable. So, the transfer function of compensator C(s) must be designed to meet these requirements. In many applications, use an electrolytic capacitor as the output capacitor, if the zero (f Z) caused by Effective Series Resistance (ESR) of capacitor is a few kHz and smaller than 8 times f P, the type 2 (PI) can be used to get desired compensation. Figure 9 shows the typical type 2 trans-conductance error amplifier and the Bode plot is also shown in Figure 10. VOUT G(s) Gain Power stage VREF Ra VIN/Vr Vc + gm - Rc1 Rb Cc1 f fp Cc2 fz TL(s) Figure 9. The typical type 2 trans-conductance error amplifier. Desired loop gain fc f Gain(dB) Phase gmRc1 f 0° f Phase fcz fcp -90 ° Phase -180 ° margin Boost -90 Figure 8. The Bode plot of desired loop gain and phase margin www.richtek.com 18 f Figure 10. The Bode plot of type 2 trans-conductance error amplifier DS9206-13 April 2011 RT9206 The design procedure as following : (1). Selecting the zero crossover frequency f C is 1/10 to 1/20 switching frequency. Then according equation (24) set the resistor RC1 to determine the zero crossover frequency. Vr × L × f C V OUT (Ω) (24) R C1 ≈ × V IN × gm × r C V REF (2). Place the zero of compensator is 70% fp that is resonance frequency of power stage. The compensator capacitor Cc1 can be selected to set the zero. The equation is shown in following : Step2. Determine the zero crossover frequency and compensated type. Select desired zero-crossover frequency : fC ≤ fS/10 ~ fS/20 Select f C = 20kHz Step3. Determine desired location of poles and zeros for type2 compensator. Select: fCZ = 0.7 × fP = 0.7 × 1.34kHz = 938Hz Assume fCP = CC1 = L × CO 0.7 × RC1 = 100kHz 2 (F) (25) (3). Set a second pole to suppress the switching noise. Assume the pole is one half of switching frequency f s, which results in capacitor Cc2 as shows in following: 1 CC2 = fS π × RC1 × fs - 1 ≈ Step4. Calculate the real parameters-resistor and capacitors for type2 compensator. From equation (21), the RC1 is calculated as following : f C × L × Vr RC1 = rC × V IN × gm 1 π × RC1 × fs (F) (26) = CC1 × V OUT V REF 20kH z × 15 µ H × 1.9 22m Ω × 12V × 1.6m s × 5V 0.8V = 8.4k Ω Design example Design example of type 2 compensator: the schematic is shown in Figure 4, where the parameters as following : VIN = 12V, VOUT = 5V, IOUT = 5A, switching frequency = 200kHz, L = 15µH, C O = 940µF, r C = 22mΩ, the parameters of RT9206 as following : gm = 1.6ms, ramp amplitude = 1.9V, and reference voltage Vref = 0.8V. Step1. Determine the power stage poles and zeros. The pole caused by the output inductor and output capacitor is calculated as : fP = fZ = 1 2π L × CO 1 2π × rC × CO = = 1 2π 15 µ × 940 µ = 1.34kHz 1 2π × 22mΩ × 940 µF DS9206-13 April 2011 = 7.7kHz Select RC1 = 8.2kΩ Calculate CC1 from equation (25) CC1 = L × CO 0.7 × RC1 = 15 µ × 940 µ 0.7 × 8.2k = 20.7nF Select CC1 = 22nF Second capacitor CC2 can be calculated using equation (26) CC2 = 1 π × R C1 × fS = 1 = 194pF π × 8.2kΩ × 200kHz Select CC2 = 220pF www.richtek.com 19 RT9206 Linear Regulator Output Capacitor Selection } Solid tantalum capacitors are recommended for use on the output capacitors of LDO because their typical ESR is very close to the ideal value required for loop compensation. Tantalums also have good temperature stability: a good quality tantalum will typically show a capacitance value that varies less than 10-15% across the full temperature range of 125°C to −40°C. ESR will vary only about 2X going from the high to low temperature limits. The IC needs a bypassing ceramic capacitor C1 as a R-C filter to isolate the pulse current from power stage and supply to IC, so the ceramic capacitor C1 should be placed adjacent to the IC. } Place the high frequency ceramic decoupling close to the power MOSFETs. } The feedback part should be placed as close to IC as possible and keep away from the inductor and all noise sources. Linear Regular MOSFETs Selection } The components of bootstraps (C8, C9 and D1) should be closed to each other and close to MOSFETs. } The PCB trace from UGATE and LGATE of controller to MOSFETs should be as short as possible and can carry 1A peak current. } Place all of the components as close to IC as possible. The main consideration of pass MOSFETs of linear regulator is package selection for efficient removal of heat. The power dissipation of a linear regulator is Plinear = (VIN - VOUT) × IOUT (W) (26) The criterion for selection of package is the junction temperature below the maximum desired temperature with the maximum expected ambient temperature. Figure 11 shows the typical PCB layout of synchronous Buck converter with RT9206 controller Layout Consideration Layout is very important in high frequency switching converter design. If designed improperly, the PCB could radiate excessive noise and contribute to the converter instability. First, place the PWM power stage components. Mount all the power components and connections in the top layer with wide copper areas. The MOSFETs of Buck, inductor, and output capacitor should be as close to each other as possible. This can reduce the radiation of EMI due to the high frequency current loop. If the output capacitors are placed in parallel to reduce the ESR of capacitor, equal sharing ripple current should be considered. Place the input capacitor directly to the drain of high-side MOSFET. The MOSFETs of linear regulator should have wide pad to dissipate the heat. In multilayer PCB, use one layer as power ground and have a separate control signal ground as the reference of the all signal. To avoid the signal ground is effect by noise and have best load regulation, it should be connected to the ground terminal of output. Furthermore, follows below guidelines can get better performance of IC : www.richtek.com 20 Figure 11. The PCB layout of synchronous Buck converter with RT9206 controller DS9206-13 April 2011 RT9206 Outline Dimension H A M J B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 9.804 10.008 0.386 0.394 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.254 0.007 0.010 I 0.102 0.254 0.004 0.010 J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050 16-Lead SOP Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS9206-13 April 2011 www.richtek.com 21