APW8727/L Synchronous single PWM Controller with Multiform supply Voltage Features General Description • Adjustable Output Voltage from +0.8V to +5.0V The APW8727 is a single-phase, constant on-time, syn- - 0.8V Reference Voltage chronous PW M controller, which drives N-channel MOSFETs. The APW8727 steps down high voltage to - +0.6% Accuracy • generate low-voltage chipset, RAM supplies in notebook computers or motherboard applications. Operates from An Input Battery Voltage Range of +4V to +25V • The APW8727 provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode. Multiform Purpose Input Voltage Collocation - -VCC=5V / VIN=8~19V For NB application In Pulse Frequency Mode (PFM), the APW8727 provides very high efficiency over light to heavy loads with loading- - VCC=5~12V / VIN=5~12V For table PC application • Power-On-Reset Monitoring on VCC pin • Excellent line and load transient responses • Ultrasonic Operation Eliminated Audio Noise • PFM mode for increased light load efficiency • 300kHz Constant PWM Switching Frequency • Integrated MOSFET Drivers • Integrated Bootstrap Forward P-CH MOSFET • Integrated Soft-Start Function • Power Good Monitoring • 70% Under-Voltage Protection • 125% Over-Voltage Protection • modulated switching frequencies. In PWM Mode, the converter works nearly at constant frequency for low-noise requirements. The unique ultrasonic mode maintains the switching frequency above 37kHz, which eliminates noise in audio application. The APW8727 is equipped with accurate positive current limit, output under-voltage, and output over-voltage protections, perfect for multiform applications. The PowerOn-Reset function monitors the voltage on VCC to prevent wrong operation during power-on. The APW8727 has an internal 2ms digital soft start that ramps up the output voltage with programmable slew rate to reduce the start- Adjustable Current-limit protection up current. The enable function can let user easy to apply APW8727. - Using Sense Low-Side MOSFET’s RDS(ON) • Over-Temperature Protection • TDFN-10 3x3 package • Lead Free and Green Devices Available The APW8727 is available in 10pin TDFN 3x3 package respectively. Simplified Application Circuit (RoHS Compliant) 4.5~13.2V Applications • • VCC Notebook UGATE Table PC • Hand-Held Portable • AIO PC • Wide input DC/DC Regulators 4~25V VIN Q1 APW8727 L POK PHASE EN LGATE/ OCSET VOUT Q2 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 1 www.anpec.com.tw APW8727/L Ordering and Marking Information APW8727/L Package Code QB : TDFN3x3-10 Temperature Range I : -40 to 85 oC Handling Code Assembly Meterial Handling Code TR : Tape & Reel Assembly Meterial G : Halogen and Lead Free Device . Temperature Range Package Code QB : APW 8727 XXXXX XXXXX - Date Code APW8727L QB : APW 8727L XXXXX XXXXX - Date Code APW8727 Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration BOOT 1 BOOT 1 10 POK 10 POK PHASE 2 9 VSENSE PHASE 2 9 NC UGATE 3 8 FB UGATE 3 8 FB LGATE/OCSET 4 7 EN LGATE/OCSET 4 7 EN GND 5 GND 5 6 VCC APW8727 TDFN-10 3X3 (top view) 6 VCC APW8727L TDFN-10 3X3(top view) = GND and Thermal Pad (connected to GND plane for better heat dissipation) Absolute Maximum Ratings (Note 1) Symbol VCC VBOOT-GND VBOOT VPOK Parameter VCC Supply Voltage (VCC to GND) Rating Unit -0.3 ~ 16 V BOOT Supply Voltage (BOOT to GND) -0.3 ~ 44 V BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 16 V POK Supply Voltage (POK to GND) -0.3 ~ 16 V -0.3~7 V All Other Pins (EN, VSENSE and FB to GND) Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 2 www.anpec.com.tw APW8727/L Absolute Maximum Ratings (Cont.) (Note 1) Symbol Parameter Rating Unit -3 ~ VBOOT+3 V UGATE Voltage (UGATE to PHASE) <20ns pulse width >20ns pulse width -0.3 ~ VBOOT+0.3 <20ns pulse width >20ns pulse width -0.3 ~ VCC+0.3 <20ns pulse width >20ns pulse width -0.3 ~ 28 LGATE Voltage (LGATE to GND) -5 ~ VCC+5 V PHASE Voltage (PHASE to GND) VPHASE Maximum Junction Temperature TJ TSTG Storage Temperature TSDR Maximum Soldering Temperature, 10 Seconds -5 ~ 35 V 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Parameter Symbol Typical Value Unit Thermal Resistance -Junction to Ambient (Note 2) θJA TDFN3x3-10 °C/W 55 Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.The exposed pad of package is soldered directly on the PCB. Recommended Operating Conditions (Note 3) Symbol Parameter VIN Converter Input Voltage Range Unit 4 ~ 25 V VCC VCC Supply Voltage 4.5 ~ 13.2 V VOUT Converter Output Voltage 0.8~5 V IOUT Converter Output Current 0 ~ 20 A TA Ambient Temperature -40 ~ 85 o TJ Junction Temperature -40 ~ 125 o C C Note 3: Refer to the application circuit for further information. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 3 www.anpec.com.tw APW8727/L Electrical Characteristics These specifications apply for TA = -40oC to +85oC, unless otherwise stated. All typical specifications TA= +25oC, VCC = 12V Symbal Parameter APW8727 Test Condition Min. Typ. Max. Unit - 0.8 - V -0.6 - +0.6 % -1.0 - +1.0 % FB=0.8V - - 1 µA VCC Input Bias Current VCC Current, EN=5V, VFB=0.9V, PHASE=0.5V - 2 3 VCC Shutdown Current EN=GND, VCC=5V - 15.3 20 µA Reference VOLTAGE Reference Voltage o VREF TA = 25 C Regulation Accuracy IFB FB Input Bias Current o o TA = -40 C ~ 85 C, Line / Load Transient SUPPLY CURRENT IVCC IVCC_SHD N mA SWITCHING FREQUENCY AND DUTY TON TOFF(MIN) PWM On Time VIN=12V, VOUT=1V 222 278 333 ns Minimum off time VFB=0.75V, VPHASE=-0.1V 300 400 500 ns 25 37 - kHz Minimum Ultrasonic Skip Operating Frequency Power On Timing TSS OCP Threshold Setting Time When set the max. value - 950 - µs Internal Soft Start Time VOUT=0% to VOUT Regulation (95%) - 2 - ms 5V UG Source current VCC=5V, BOOT-UG=5V - 1.5 - A 5V UG Sink Resistance VCC=5V, UG-PHASE=1V - 1.4 - Ω 5V LG Source current VCC=5V, VCC-LG=5V - 1.5 - A 5V LG Sink Resistance VCC=5V, LG-GND=1V - 1.0 - Ω UG to LG Dead time UG falling to LG rising at VCC=5V - 40 - ns UG falling to LG rising at VCC=12V - 20 - ns GATE DRIVER LG to UG Dead time LG falling to UG rising at VCC=5V - 40 - ns LG falling to UG rising at VCC=12V - 20 - ns Bootstrap Forward Voltage VVCC – VBOOT-GND, IF = 10mA - 0.2 0.4 V Reverse Leakage VBOOT-GND = 30V, VPHASE = 25V, VVCC = 5V - - 0.5 µA BOOTSTRAP SWITCH VF IR Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 4 www.anpec.com.tw APW8727/L Electrical Characteristics (Cont.) These specifications apply for TA = -40oC to +85oC, unless otherwise stated. All typical specifications TA= +25oC, VCC = 12V Symbal Parameter APW8727 Test Condition Min. Typ. Max. Unit 4.25 4.35 4.45 V - 300 - mV - - 0.85 Enable 1.3 - - EN=5V - 0.1 1.0 µA 87 90 93 % VCC POR THRESHOLD VVCC_THR Rising VCC POR Threshold Voltage VCC POR Hysteresis CONTROL INPUTS EN Threshold EN Leakage Shutdown V POWER-OK INDICATOR POK in from Lower (POK Goes High) VPOK IPOK POK Threshold POK out from normal falling (POK Goes Low) 65 70 75 % POK out from normal rising (POK Goes Low) 120 125 130 % POK Leakage Current VPOK=5V - 0.1 1 µA POK Sink Current VPOK=0.5V 5 15 - mA POK Enable Delay Time VOUT from 0% to POK High - 2.5 - ms 9.5 10 10.5 µA CURRENT SENSE IOCSET IOCSET OCP Threshold IOCSET Sourcing TCIOCSET IOCSET Temperature Coefficient On The Basis of 25°C VROCSET Maximum Current Limit Threshold ROCSET open - 640 - mV Zero Crossing Comparator Offset VGND-PHASE Voltage -3 0 3 mV 65 70 75 % - 30 - µs ppm/ oC 2780 PROTECTION VUV UVP Threshold UVP Debounce Time VOVR TOTR UVP Enable Delay VOUT from 0% to UVP enable OVP Rising Threshold VFB rising, LG fully turn on OVP Propagation Delay VFB Rising OTP Rising Threshold (Note 4) OTP Hysteresis (Note 4) - 2.5 - ms 120 125 130 % - 2 - µs - 150 - o - o - 25 C C Note 4: Guaranteed by design. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 5 www.anpec.com.tw APW8727/L Typical Operating Characteristics Switching Frequency vs. Converter Input Voltage Switching Frequency vs. Converter Output Current 350 Switching Frequency, FSW (kHz) Switching Frequency, FSW (kHz) 400 350 300 250 200 150 0 5 10 15 20 25 250 200 150 100 50 0 0.001 30 0.01 10 1 100 Converter Input Voltage, VIN (V) Converter Output Voltage vs. Converter Output Current Converter Output Voltage vs. Converter Input Voltage Converter Output Voltage, VOUT (V) 1.080 VIN=12V 1.060 VIN=19V 1.058 1.056 1.054 1.052 1.050 Load=0A 1.070 Load=2A 1.060 1.050 1.040 1.030 1.048 0 3 6 9 12 15 18 21 24 3 6 9 12 15 18 21 24 Converter Input Voltage, VIN (V) Converter Output Current, IOUT (A) Reference Voltage vs. Junction Temperature Switching Frequency vs. Junction Temperature 350 0.81 340 Switching Frequency (kHz) VCC = 12V Reference Voltage (V) 0.1 Converter Output Current, IOUT (A) 1.062 Converter Output Voltage, VOUT (V) 300 0.805 0.8 0.795 330 320 310 300 290 280 270 260 0.79 -20 250 0 20 40 60 80 100 -20 120 20 40 60 80 100 120 Junction Temperature (oC) Junction Temperature (oC) Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 0 6 www.anpec.com.tw APW8727/L Typical Operating Characteristics Efficiency vs Load current VOUT=1.05V 95 VIN=19V Efficiency (%) 90 VIN=12V 85 80 75 70 H-Side:SM4370 x1 L-Side:SM4373 x1 65 60 0.1 1 10 100.00 Converter Output Current, IOUT (A) Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 7 www.anpec.com.tw APW8727/L Operating Waveforms Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified. Power Off Power On VIN VIN 1 1 RLOAD=20Ω VOUT 2 VOUT 2 VPHASE VPHASE 3 3 CH1: VIN, 10V/Div CH1: VIN, 10V/Div CH2: VOUT, 500mV/Div CH3: VPHASE, 10V/Div TIME: 2ms/Div CH2: VOUT, 500mV/Div CH3: VPHASE, 10V/Div TIME: 20ms/Div Shutdown Enable VEN VEN 1 1 VOUT VOUT 2 RLOAD=20Ω 2 VPHASE VPHASE 3 3 CH1: VEN, 50V/Div CH2: VOUT, 500mV/Div CH3: VPHASE, 10V/Div TIME: 1ms/Div CH1: VEN, 5V/Div CH2: VOUT, 500mV/Div CH3: VPHASE, 10V/Div TIME: 1ms/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 8 www.anpec.com.tw APW8727/L Operating Waveforms Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified. Over-Current Protection Under-Voltage Protection Rocset=7.5k RDS(low-side)=4.6mΩ 1 VOUT VSENSE 1 VLGATE 2 VUGATE 3 VLGATE 2 VUGATE 3 IL 4 4 CH1: VOUT, 10V/Div CH3:VLGATE10V/Div CH3:VUGATE20V/Div CH3: IL,10A/Div TIME: 2ms/Div VPOK CH1: Vsense, 500mV/Div CH3: VLGATE 5V/Div CH3: VUGATE 20V/Div CH3: VPOK, 5V/Div TIME: 10us/Div Load Transient POWER OK VOUT 1 1 2 VOUT VPOK 2 CH1: VOUT, 50mV/Div CH2: IOUT,5A/Div TIME: 200us/Div CH1: VOUT, 500mV/Div CH2: VPOK , 5V/Div TIME: 20ms/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 IOUT 9 www.anpec.com.tw APW8727/L Pin Description PIN No. FUNCTION Name APW8727 APW8727L 1 1 BOOT Supply Input for The UGATE Driver and An Internal Level-shift Circuit. Connect to an external capacitor to create a boosted voltage suitable to drive a logic-level N-channel MOSFET. 2 2 PHASE Junction Point of The High-side MOSFET Source, Output Filter Inductor and The Low-side MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE serves as the lower supply rail for the UG high-side gate driver. 3 3 UGATE Output of The High-side MOSFET Driver. Connect this pin to Gate of the high-side MOSFET. Output of The Low-side MOSFET Driver And Current-Limit Setting Input. Connect this pin to Gate of the low-side MOSFET. There is an internal source current 10µA through a LGATE/OCSET resistor from LGATE/OCSET pin to GND before power on. This action is used to monitor the voltage drop across the Drain and Source of the low-side MOSFET for current limit. 4 4 5 5 GND 6 6 VCC Supply Voltage Input Pin for Control Circuitry. Connect +5V~+12V from the VCC pin to the GND. Decoupling at least 1µF of a MLCC capacitor from the VCC pin to the GND. 7 7 EN Enable/Shutdown Pin. When EN=1, enable the PWM controller, EN=0, shutdown the PWM controller. When the EN is floating, it will pull up to high logic automatically. 8 8 FB Output Voltage Feedback Pin. This pin is connected to the resistive divider in remote side that set the desired output voltage. In APW8727L, The POK, UVP, and OVP circuits detect this signal to report output voltage status. 9 - VSENSE Output Voltage Sense Pin. It is used to sense the output voltage. The VSENSE pin is the input of over-voltage, under-voltage and POK detecting comparator. Connect a resistor diver from output to GND to set the OVP and UVP thresholds. VSENSE should not be left floating. - 9 NC 10 10 POK Exposed pad Exposed pad GND Signal Ground for The IC No Connect Power Good Output. POK is an open drain output used to indicate the status of the output voltage. Connect the POK in to +5V~+12V through a pull-high resistor. Signal Ground for The IC Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 10 www.anpec.com.tw APW8727/L Block Diagram POK PHASE BOOT VREF x 125% BOOT Voltage Sense Circuit POR VIN OK Signal To Sample and Hold VIN Voltage Sense Circuit Sense Low -Side BOOT OK Signal To Sample and Hold VREF x 70 % VSENSE/FB 125 % VREF Fault Latch Logic BOOT UGATE PWM Sign al Con tro ller 70% VREF Thermal Shutdown FB On-Time Generator ZC Error Comparator PHASE V CC Digital Soft Start LGATE VREF VCC POR EN VROCSET Current Limit OV UV VCC POR Sample and Hold VROCSET Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 PHASE 10µA GND To LGATE 11 www.anpec.com.tw APW8727/L Typical Application Circuit Circuit 1 VCC Supply 5V~12 V R VCC 2R2 C VCC 1µF 6 POK R POK 100kΩ Enable signal ON OFF 7 5 BOOT VCC 10 5V/12V PullHigh Source VIN=5V~19V APW8727 (TDFN3*3-10) UGATE PHASE EN C IN 10µF X 3 C BOOT 0.1µF 1 Q1 SM4370 L1 3 2 VOUT =1.05V 1.0µ H LGATE/ 4 OCSET GND VSENSE 9 Q2 SM4373 R TOP 10kΩ R OCSET FB 8 C OUT2 330µF 330µF RGND 32kΩ R TOP 10kΩ RGND 32kΩ C OUT1 Circuit 2 VCC Supply 5V ~12V C VCC 1 µF 5V/12V PullHigh Source Enable signal ON OFF R VCC 2R2 VIN=5V~19V APW8727L (TDFN3x3-10) 6 10 RPOK 100kΩ 7 5 VCC POK EN BOOT UGATE PHASE 1 C IN 10µ F X 3 C BOOT 0.1µF Q1 SM4370 L1 3 2 V OUT=1.05V 1.0µH GND LGATE/ 4 OCSET NC 9 FB 8 Q2 SM4373 R OCSET R TOP 10kΩ COUT1 COUT2 330µF 330µF R GND 32kΩ Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 12 www.anpec.com.tw APW8727/L Function Description Constant-On-Time PWM Controller with Input Feed-Forward Where FSW is the nominal switching frequency of the converter in PWM mode. The load current at handoff from PFM to PWM mode is given by: The constant-on-time control architecture is a pseudofixed frequency with input voltage feed-forward. This architec- 1 VIN − VOUT × × TON-PFM 2 L V − VOUT V 1 = IN × x OUT 2L FSW VIN ture relies on the output filter capacitor’s effective series resistance (ESR) to act as a current-sense resistor, so ILOAD(PFM to PWM) = the output ripple voltage provides the PWM ramp signal. In PFM operation, the high-side switch on-time controlled by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input volt- Power-On-Reset A Power-On-Reset (POR) function is designed to prevent wrong logic controls when the VCC voltage is low. The age and directly proportional to output voltage. In PWM operation, the high-side switch on-time is determined by POR function continually monitors the bias supply voltage on the VCC pin if at least one of the enable pins is set a switching frequency control circuit in the on-time generator block. high. When the rising VCC voltage reaches the rising VCC POR Threshold (4.35V, typical), the POR signal goes The switching frequency control circuit senses the switching frequency of the high-side switch and keeps regulat- high and the chip initiates soft-start operations. There is a hysteresis to POR voltage threshold (about 300mV ing it at a constant frequency in PWM mode. The design improves the frequency variation and is more outstand- typical). When VCC voltage drops lower than 4.05V (typical), the POR disables the chip. ing than a conventional constant-on-time controller, which has large switching frequency variation over input voltage, output current, and temperature. Both in PFM and PWM, the on-time generator, which senses input voltage on EN Pin Control PHASE pin, provides very fast on-time response to input line transients. When V EN is above the EN high threshold (1.3V, minimum), the converter is enabled. When VEN is below the EN low threshold (0.85V, maximum), the chip is in the Another one-shot sets a minimum off-time (400ns, typical). The on-time one-shot is triggered if the error com- shutdown and only low leakage current is taken from VCC. When EN pin is in float state, it will pull up high logic parator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time oneshot automatically. has timed out. Digital Soft-Start Pulse-Frequency Modulation (PFM) In PFM mode, an automatic switchover to pulse-fre- The APW8727integrates digital soft-start circuits to ramp quency modulation (PFM) takes place at light loads. This switchover is affected by a comparator that truncates the up the output voltage of the converter to the programmed regulation setpoint at a predictable slew rate. The slew low-side switch on-time at the inductor current zero crossing. This mechanism causes the threshold between rate of output voltage is internally controlled to limit the inrush current through the output capacitors during soft- PFM and PWM operation to coincide with the boundary between continuous and discontinuous inductor-current start process. The figure 1 shows soft-start sequence. When the EN pin is pulled above the rising EN threshold operation (also known as the critical conduction point). The on-time of PFM is given by: voltage, the device initiates a soft-start process to ramp up the output voltage. The soft-start interval is 2ms (typical) and independent of the UGATE switching frequency. TON-PFM = V 1 × OUT FSW VIN Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 13 www.anpec.com.tw APW8727/L Function Description (Cont.) Under-Voltage Protection (UVP) V In the operational process, if a short-circuit occurs, the output voltage will drop quickly. When load current is bigger than current-limit threshold value, the output voltage will fall out of the required regulation range. The underVCC voltage protection circuit continually monitors the VSENSE voltage after soft-start is completed. If a load step is strong POK POK Enable Delay Time=2.5ms enough to pull the output voltage lower than the undervoltage threshold, the under-voltage threshold is 70% of Soft Start Time=2ms Power Ready Detection & OCP Setting VOUT the nominal output voltage, the internal UVP delay counter starts to count. After 30µs debounce time, the device turns EN off both high-side and low-side MOSEFET with latched. Toggling enable pin to low or recycling VCC, will clear the latch and bring the chip back to operation. In APW8727L, the FB pin is also used for monitoring this function. Over-Voltage Protection (OVP) T The over-voltage function monitors the output voltage by Figure 1. Soft-Start Sequence VSENSE pin. When the VSENSE voltage increases over 125% of the reference voltage due to the high-side During soft-start stage before the PGOOD pin is ready, the under-voltage protection is prohibited. The over-voltage and current-limit protection functions are enabled. If MOSFET failure or for other reasons, the over-voltage protection comparator designed with a 2µs noise filter will the output capacitor has residue voltage before start-up, both low-side and high-side MOSFETs are in off-state force the low-side MOSFET gate driver fully turn on and latch high. This action actively pulls down the output until the internal digital soft-start voltage equals to the VFB voltage. This will ensure that the output voltage starts voltage. This OVP scheme only clamps the voltage overshoot and from its existing voltage level. does not invert the output voltage when otherwise activated with a continuously high output from low-side Power OK Indicator MOSFET driver. It’s a common problem for OVP schemes with a latch. Once an over-voltage fault condition is set, it The APW8727 features an open-drain POK pin to indicate output regulation status. In normal operation, when the output voltage rises 90% of its target value, the POK can only be reset by toggling EN, VCC power-on-reset signal. In APW8727L, the FB pin is also used for monitoring this function. goes high. When the output voltage outruns 70% or 125% of the target voltage, POK signal will be pulled low immediately. In APW8727L, since the FB pin is used for both feedback and monitoring purposes, the output voltage deviation can be coupled directly to the FB pin by the capacitor in parallel with the voltage divider as shown in the typical applications. In order to prevent false POK from dropping, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 14 www.anpec.com.tw APW8727/L Function Description (Cont.) Over-Current Protection of the PWM Converter ILIMIT > IOUT(MAX ) + The over-current function protects the switching converter against over-current or short-circuit conditions. The con- ∆I 2 Where ∆I = output inductor ripple current - The overshoot and transient peak current also should troller senses the inductor current by detecting the drainto-source voltage which is the product of the inductor’s be considered. current and the on-resistance of the low-side MOSFET during it’s on-state. This method enhances the converter’s Over-Temperature Protection (OTP) efficiency and reduces cost by eliminating a current sensing resistor required. When the junction temperature increases above the rising threshold temperature TOTR, the IC will enter the over- A resistor (ROCSET), connected from the LGATE/OCSET to GND, programs the over-current trip level. Before the IC temperature protection state that suspends the PWM, which forces the UGATE and LGATE gate drivers output initiates a soft-start process, an internal current source, IOCSET (10µA typical), flowing through the ROCSET develops low. The thermal sensor allows the converters to start a start-up process and regulate the output voltage again a voltage (VROCSET) across the ROCSET. The device holds VROCSET and stops the current source IOCSET during normal after the junction temperature cools by 25oC. The OTP is designed with a 25oC hysteresis to lower the average TJ operation. When the voltage across the low-side MOSFET exceeds the VROCSET, the APW8727 shuts off the converter during continuous thermal overload conditions, which increases lifetime of the APW8727. and then initiates a new soft-start process. After 4 overcurrent events are counted, the device turns off both high- The On-Time Control and PWM Switching Frequency side and low-side MOSFETs and the converter’s output is latched to be floating. The APW8727 has an internal OCP voltage, VOCP_MAX, and The APW8727 does not use a clock signal to produce PWM. The device uses the constant-on-time control architecture to produce pseudo-fixed frequency with input voltage feed-forward. The on-time pulse width is propor- the value is 0.64V (typical). When the ROCSET x IOCSET exceed 0.64V or the ROCSET is floating or not connected, the tional to output voltage VOUT and inverses proportional to input voltage VIN. When VIN is 12V, VOUT is 1V, the switch- VROCSET will be the default value 0.64V. The over current threshold would be 0.64V across low-side MOSFET. The ing frequency is 300kHz at PWM operation. APW8727 doesn’t have VIN pin to calculate on-time pulse threshold of the valley inductor current-limit is therefore given by: ILIMIT = width. Therefore, monitoring VPHASE voltage as input voltage to calculate on-time when the high-side MOSFET is IOCSET × ROCSET RDS(ON) (low − side) turned on. For the over-current is never occurred in the normal operating load range, the variation of all parameters in the above equation should be considered: - The RDS(ON) of low-side MOSFET is varied by temperature and gate to source voltage. Users should determine the maximum RDS(ON) by using the manufacturer’s datasheet. - The minimum IOCSET (9.5µA) and minimum ROCSET should be used in the above equation. - Note that the ILIMIT is the current flow through the lowside MOSFET; ILIMIT must be greater than peak inductor current which is output current add the half of inductor ripple current. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 15 www.anpec.com.tw APW8727/L Application Information Output Voltage Setting saturation. In some types of inductors, especially core The output voltage is adjustable from 0.8V to 5V with a that is made of ferrite, the ripple current will increase abruptly when it saturates. This results in a larger output resistor-divider connected with FB, GND, and converter’s output. Using 1% or better resistors for the resistor-di- ripple voltage. Besides, the inductor needs to have low DCR to reduce the loss of efficiency. vider is recommended. The output voltage is determined by: R TOP V OUT = 0.8 × 1 + R GND Output Capacitor Selection Output voltage ripple and the transient voltage deviation are factors which have to be taken into consideration when selecting an output capacitor. Higher capaci- Where 0.8 is the reference voltage, RTOP is the resistor connected from converter’s output to FB, and RGND is the tor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high per- resistor connected from FB to GND. Suggested RGND is in the range from 1k to 20kΩ. To prevent stray pickup, locate formance low ESR capacitors is recommended for switching regulator applications. In addition to high resistors RTOP and RGND close to APW8727. frequency noise related to MOSFET turn-on and turnoff, the output voltage ripple includes the capacitance Output Inductor Selection The duty cycle (D) of a buck converter is the function of the voltage drop ∆VCOUT and ESR voltage drop ∆VESR caused by the AC peak-to-peak inductor’s current. These two input voltage and output voltage. Once an output voltage is fixed, it can be written as: voltages can be represented by: V D = OUT VIN The inductor value (L) determines the inductor ripple IRIPPLE 8COUTFSW = IRIPPLE × RESR ∆VCOUT = ∆VESR current, IRIPPLE, and affects the load transient reponse. Higher inductor value reduces the inductor’s ripple cur- These two components constitute a large portion of the rent and induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by: total output voltage ripple. In some applications, multiple capacitors have to be paralleled to achieve the desired ESR value. If the output of the converter has to support another load with high pulsating current, more capaci- VIN - VOUT VOUT × FSW × L VIN Where FSW is the switching frequency of the regulator. Although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff exists between the inductor’s ripple current and the regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (F SW ) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, selecting an inductor which is capable of carrying the required peak current without going into IRIPPLE = Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 tors are needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. A small decoupling capacitor (1µF) in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors are also must be considered. To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing the voltage excursion during load step change. Another aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the rated RMS current specified on the capacitors in order to prevent the capacitor from over-heating. Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, selecting the capacitor voltage rating to be at least 1.3 times 16 www.anpec.com.tw APW8727/L Application Information (Cont.) 2 Input Capacitor Selection (Cont.) Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW 2 Plow-side = IOUT (1+ TC)(RDS(ON))(1-D) Where higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2, where IOUT is the load current. During power-up, the input capacitors have to handle great amount of surge current. I is the load current OUT TC is the temperature dependency of RDS(ON) For low-duty notebook appliactions, ceramic capacitor is recommended. The capacitors must be connected be- FSW is the switching frequency tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction losses while tween the drain of high-side MOSFET and the source of low-side MOSFET with very low-impeadance PCB layout. MOSFET Selection the high-side MOSFET includes an additional transition loss. The switching interval, tSW , is the function of the reverse The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs should transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and can be be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET: extracted from the “RDS(ON) vs. Temperature” curve of the power MOSFET. For the low-side MOSFET, before it is turned on, the body diode has been conducting. The low-side MOSFET driver Layout Consideration In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. will not charge the miller capacitor of this MOSFET. In the turning off process of the low-side MOSFET, the With power devices switching at higher frequency, the resulting current transient will cause voltage spike across load current will shift to the body diode first. The high dv/ dt of the phase node voltage will charge the miller capaci- the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition tor through the low-side MOSFET driver sinking current path. This results in much less switching loss of the low- of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off, side MOSFETs. The duty cycle is often very small in high battery voltage applications, and the low-side MOSFET current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic diode. Any parasitic will conduct most of the switching cycle; therefore, when using smaller RDS(ON) of the low-side MOSFET, the con- inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and verter can reduce power loss. The gate charge for this MOSFET is usually the secondary consideration. The wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. high-side MOSFET does not have this zero voltage switching condition; in addition, because it conducts for less Besides, signal and power grounds are to be kept separating and finally combined using ground plane construc- time compared to the low-side MOSFET, the switching loss tends to be dominant. Priority should be given to the tion or single point grounding. The best tie-point between the signal ground and the power ground is at the nega- MOSFETs with less gate charge, so that both the gate driver loss and switching loss will be minimized. tive side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not The selection of the N-channel power MOSFETs are determined by the R DS(ON), reversing transfer capaci- recommended. Below is a checklist for your layout: • Keep the switching nodes (UGATE, LGATE, BOOT, tance (CRSS) and maximum output current requirement. The losses in the MOSFETs have two components: and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. conduction loss and transition loss. For the high-side and low-side MOSFETs, the losses are approximately Therefore, keep traces to these nodes as short as possible and there should be no other weak signal given by the following equations: traces in parallel with theses traces on any layer. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 17 www.anpec.com.tw APW8727/L Application Information (Cont.) Layout Consideration (Cont.) ThermalVia diameter 12mil X 5 • The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and discharging current. The traces from the gate drivers 0. 3 0mm 2.70mm • Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. 0.50mm the node. In addition, the large layout plane between the drain of the MOSFETs (VIN and PHASE nodes) can • 0.275mm 0.75mm to the MOSFETs (UGATE and LGATE) should be short and wide. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of Ground plane for ThermalPAD 1.75mm get better heat sinking. The GND is the current sensing circuit reference TDFN3X3 -10 ground and also the power ground of the LGATE lowside MOSFET. On the other hand, the GND trace should be a separate trace and independently go to the source of the low-side MOSFET. Besides, the current sense resistor should be close to OCSET pin to avoid parasitic capacitor effect and noise coupling. • Decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. (For example, place the decoupling ceramic capacitor close to the drain of the high-side MOSFET as close as possible.) • The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output bulk capacitors should be close to the loads. The input capacitor’s ground should be close to the grounds of the output capacitors and low-side MOSFET. • Locate the resistor-divider close to the FB pin to minimize the high impedance trace. In addition, FB pin traces can’t be close to the switching signal traces (UGATE, LGATE, BOOT, and PHASE). Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 18 www.anpec.com.tw APW8727/L Package Information TDFN3x3-10 D E A b Pin 1 A1 D2 A3 NX aaa C L K E2 Pin 1 Corner e S Y M B O L A TDFN3x3-10 MILLIMETERS INCHES MIN. MAX. MIN. MAX. 0.70 0.80 0.028 0.031 0.05 0.000 0.002 A1 A3 0.00 b 0.18 0.30 0.008 REF 0.007 0.012 D 2.90 3.10 0.114 0.122 2.70 0.087 0.106 3.10 0.114 0.122 1.75 0.055 0.069 0.50 0.016 BSC 0.012 0.020 D2 E E2 0.20 REF 2.20 2.90 1.40 e L 0.30 K 0.20 0.50 BSC aaa 0.008 0.08 0.003 Note : 1. Followed from JEDEC MO-229 VEED-5. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 19 www.anpec.com.tw APW8727/L Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TDFN3x3-10 A H T1 C d D 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 W E1 12.0±0.30 1.75±0.10 F 5.5±0.05 (mm) Devices Per Unit Package Type TDFN3x3-10 Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 Unit Tape & Reel Quantity 3000 20 www.anpec.com.tw APW8727/L Taping Direction Information TDFN3x3-10 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 21 www.anpec.com.tw APW8727/L Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3 °C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 22 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW8727/L Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 23 www.anpec.com.tw