SN75LPE185 LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS WITH ENABLE SLLS256D – DECEMBER 1996 – REVISED OCTOBER 1998 D D D D D D D D D D D D Single-Chip RS-232 Interface for IBM PC Compatible Serial Port Designed to Transmit and Receive 4-µs Pulses (Equivalent to 256 kbit/s) Standby Power Is Less Than 750 µW Maximum Wide Supply-Voltage Range . . . 4.75 V to 15 V Driver Output Slew Rates Are Internally Controlled to 30-V/µs Maximum RS-232 Bus-Pin ESD Protection Exceeds: – 15 kV, Human-Body Model – 8-kV IEC1000-4-2, Contact – 15-kV IEC1000-4-2, Air Gap Receiver Input Hysteresis . . . 1000 mV Typical Three Drivers and Five Receivers Meet or Exceed the Requirements of TIA/EIA-232-F and ITU v.28 Standards Complements the SN75LP196 One Receiver Remains Active During WAKE-UP Mode (100 µA Maximum) Matches the Flow-Through Pinout of the Industry-Standard SN75185, SN75C185, and SN75LP185, With Additional Control Pins Package Options Include Plastic Shrink Small-Outline (DB), Small-Outline (DW), Thin Shrink Small-Outline (PW), and Standard Plastic (NT) DIPs DB, DW, NT, OR PW PACKAGE (TOP VIEW) VDD RA1 RA2 RA3 DY1 DY2 RA4 DY3 RA5 VSS EN MODE 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC RY1 RY2 RY3 DA1 DA2 RY4 DA3 RY5 GND NC NC NC – No internal connection description The SN75LPE185 is a low-power bipolar device containing three drivers and five receivers, with 15-kV ESD protection on the bus pins, with respect to each other. Bus pins are defined as those pins that tie directly to the serial-port connector, including GND. The pinout matches the flow-through design of the industry-standard SN75185, SN75C185, and SN75LP185, with the addition of four pins for control signals. The flow-through pinout of the device allows easy interconnection of the UART and serial-port connector of the IBM PC compatibles. The SN75LPE185 provides a rugged, low-cost solution for this function with the combination of bipolar processing and 15-kV ESD protection. The SN75LPE185 has an internal slew-rate control to provide a maximum rate of change in the output signal of 30 V/µs. The driver output swing is clamped at ±6 V to enable the higher data rates associated with this device and reduce EMI emissions. Although the driver outputs are clamped, the outputs can handle voltages up to ±15 V without damage. The device has flexible control options for power management when the serial port is inactive. A common disable for all of the drivers and receivers is provided with the active-low enable (EN) input. The mode control (MODE) input selects between the STANDBY and WAKE-UP modes. With a low-level input on the MODE pin and a high-level input on the EN pin, one receiver remains active while the remaining drivers and receivers are Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IBM and PC are trademarks of International Business Machines Corporation. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN75LPE185 LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS WITH ENABLE SLLS256D – DECEMBER 1996 – REVISED OCTOBER 1998 description (continued) disabled to implement the WAKE-UP mode. With a high-level input on both the MODE and EN pins, all drivers and receivers are disabled to implement the STANDBY mode. The outputs of the drivers are in a high-impedance state when the device is powered off. To ensure the outputs of the receivers are in a known output level (as listed in the Application Information section of this data sheet) when the device is powered off, in STANDBY, or WAKE-UP mode, external pullup/pulldown circuitry must be provided. All the logic inputs accept 3.3-V or 5-V input signals. The SN75LPE185 complies with the requirements of TIA/EIA-232-F and ITU v.28 standards. These standards are for data interchange between a host computer and peripheral at signaling rates up to 20 kbit/s. The switching speeds of the SN75LPE185 support rates up to 256 kbit/s. The SN75LPE185 is characterized for operation from 0°C to 70°C. Function Tables DRIVERS INPUT DA ENABLE EN OUTPUT DY Z X H H L L L L H Open L L H Open L L Open H H = high level, L = low level, X = irrelevant, Z = high impedance (off) RECEIVERS INPUTS ENABLE INPUTS OUTPUTS RA1–RA4 RA5 EN MODE RY1–RY4 H H L X L L L L L X H H X H H L Z L X L H L Z H X X H H Z Z Open Open L X H H H H L Open L L L L L Open H H X H H Open Z L H X L H Open Z H H Open X L L L L Open X H H H = high level, L = low level, X = irrelevant, Z = high impedance (off) 2 RY5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LPE185 LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS WITH ENABLE SLLS256D – DECEMBER 1996 – REVISED OCTOBER 1998 functional logic diagram (positive logic) RA1 RA2 RA3 DY1 DY2 RA4 DY3 RA5 EN MODE 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 RY1 RY2 RY3 DA1 DA2 RY4 DA3 RY5 11 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN75LPE185 LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS WITH ENABLE SLLS256D – DECEMBER 1996 – REVISED OCTOBER 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Positive supply voltage range: VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 15 V Negative supply voltage range, VSS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to –15 V Receiver input voltage range, VI (RA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 V to 30 V Driver input voltage range, VI (DA, EN, MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.4 V Receiver output voltage range, VO (RY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Driver output voltage range, VO (DY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to 15 V Electrostatic discharge, bus pins: Machine model (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, 500 V Human-body model (see Note 2) . . . . . . . . . . . . . . . . . . . . . . Class 3, 15 kV IEC1000-4-2: contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, 8 kV IEC1000-4-2: airgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, 15 kV Electrostatic discharge, all pins: Human-body model (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . Class 3, 5 kV Machine model (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, 200 V Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to network ground terminal unless otherwise noted. 2. Per MIL-STD-883 Method 3015.7 3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions Supply voltage, VCC (see Note 4) Supply voltage, VDD Supply voltage, VSS High level input voltage, VIH DA, EN, MODE Low level input voltage, VIL DA, EN, MODE Receiver input voltage range, VI RA High level output current, IOH RY Low level output current, IOL RY Operating free air temperature, TA NOM MAX UNIT 5 5.25 V 9 12 15 V –9 –12 –15 V 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 0.8 –25 0 NOTE 4: VCC cannot be greater than VDD. 4 MIN 4.75 V 25 V –1 mA 2 mA 70 °C SN75LPE185 LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS WITH ENABLE SLLS256D – DECEMBER 1996 – REVISED OCTOBER 1998 supply currents over the recommended operating conditions (unless otherwise noted) PARAMETER ICC IDD Supply y current for VCC Supply y current for VDD TEST CONDITIONS No load, All inputs at minimum VOH or maximum VOL No load, All inputs at minimum VOH or maximum VOL MIN TYP VDD = 9 V, VSS = –9 V, EN at GND, See Note 5 ISS Supply y current for VSS UNIT 1000 VDD = 12 V, VSS = –12 V, EN at GND EN, MODE at VCC 1000 µA µ 650 EN at VCC, MODE at GND 700 VDD = 9 V, VSS = –9 V, EN at GND, See Note 5 800 VDD = 12 V, VSS = –12 V, EN at GND EN, MODE at VCC 800 µA µ 20 EN at VCC, MODE at GND No load, All inputs at minimum VOH or maximum VOL MAX 20 VDD = 9 V, VSS = –9 V, EN at GND, See Note 5 –625 VDD = 12 V, VSS = –12 V, EN at GND –625 EN, MODE at VCC µA µ –50 EN at VCC, MODE at GND NOTE 5: Minimum RS-232 driver output voltages are not attained with ±5-V supplies. –50 driver electrical characteristics over the recommended operating conditions (unless otherwise noted) PARAMETER VOH VOL IIH IIL TEST CONDITIONS High-level g output voltage VI = 0.8 V,, RL = 3 kΩ,, See Figure 1 Low-level output voltage VI = 2 V,, RL = 3 K,, See Figure 1 High-level input current VI at VCC VI at GND Low-level input current MIN TYP MAX VDD = 9 V, VSS = –9 V, EN at GND, See Note 5 5 5.8 6.6 VDD = 12 V, VSS = –12 V, EN at GND, See Note 6 5 5.8 6.6 VDD = 9 V, VSS = –9 V, EN at GND, See Note 5 –5 –5.8 –6.9 VDD = 12 V, VSS = –12 V, EN at GND, See Note 6 –5 –5.8 –6.9 UNIT V V 1 µA –1 µA ±100 µA IOZ High-impedance output current VCC = 5 V, VDD = 12 V, VSS = –12 V, –5 V ≤ VO ≤ 5 V IOS(H) Short-circuit high-level output current VO = GND or VSS, See Figure 2 and Note 7 –30 –55 mA IOS(L) Short-circuit low-level output current VO = GND or VSS, See Figure 2 and Note 7 30 55 mA VDD = VSS = VCC = 0, VO = 2 V 300 Ω NOTES: 5. Minimum RS-232 driver output voltages are not attained with ±5-V supplies. 6. Maximum output swing is limited to ±5.5 V to enable the higher data rates associated with this device and to reduce EMI emissions. 7. Not more than one output should be shorted at one time. ro Output resistance POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN75LPE185 LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS WITH ENABLE SLLS256D – DECEMBER 1996 – REVISED OCTOBER 1998 driver switching characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER tPHL Propagation delay time, high-to low-level output tPLH Propagation delay time, low-to high-level output tPZL Driver output-enable time to low-level output tPZH Driver output-enable time to high-level output tPLZ Driver output-disable time from low-level output tPHZ Driver output-disable time from high-level output tTLH Transition time,, low-to high-level output TEST CONDITIONS RL = 3 kΩ to 7 kΩ, kΩ STANDBY or WAKE-UP modes,, See Figures 1, 6, and Note 6 RL = 3 kΩ to 7 kΩ,, CL = 15 pF STANDBY or WAKE-UP modes,, See Figures 1, 6, and Note 6 Using 10%-to-90% transition region, Driver speed = 250 kbit/s CL = 15 pF Using ±3-V transition region, Driver speed = 250 kbit/s CL = 15 pF Using ±2-V transition region, Driver speed = 250 kbit/s CL = 15 pF Using ±3-V transition region, Driver speed = 125 kbit/s CL = 2500 pF Using 10%-to-90% transition region, Driver speed = 250 kbit/s CL = 15 pF tTHL Transition time,, high-to low-level output VCC = 5 V, VDD = 12 V, VSS = –12 12 V V, RL = 3 kΩ to 7 kΩ See Figure 1 and Note 6 TYP MAX 300 800 1600 300 800 1600 50 100 50 100 50 100 CL = 15 pF, pF See Figure 1 RL = 3 kΩ to 7 kΩ,, CL = 15 pF VCC = 5 V, VDD = 12 V, VSS = –12 12 V V, RL = 3 kΩ to 7 kΩ, See Figure 1 and Note 6 MIN Using ±3-V transition region, Driver speed = 250 kbit/s CL = 15 pF Using ±2-V transition region, Driver speed = 250 kbit/s CL = 15 pF ns µs µs 50 SR Output slew rate Using ±3-V transition region, Driver speed = 0 to 250 kbit/s 100 375 2240 200 1500 ns 133 1000 2750 375 2240 200 1500 ns 133 1000 Using ±3-V transition region, Driver speed = 125 kbit/s CL = 2500 pF VCC = 5 V, VDD = 12 V, VSS = –12 V, RL = 3 kΩ to 7 kΩ, CL = 15 pF, See Note 6 UNIT 2750 4 20 30 V/µs NOTE 6: Maximum output swing is limited to ±5.5 V to enable the higher data rates associated with this device and to reduce EMI emissions. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LPE185 LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS WITH ENABLE SLLS256D – DECEMBER 1996 – REVISED OCTOBER 1998 receiver electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.6 2 2.55 V 0.6 1 1.45 600 1100 VIT+ VIT– Positive-going input threshold voltage See Figure 3 Negative-going input threshold voltage See Figure 3 VHYS VOH Input hysteresis, VIT+ – VIT– See Figure 3 High-level output voltage 2.5 3.9 VOL Low-level output voltage IOH = –1 mA, IOL = 2 mA, IIH High level input current High-level VI = 3 V VI = 25 V IIL Low level input current Low-level VI = –3 V VI = –25 V IOS(H) IOS(L) Short-circuit high-level output current IOZ RIN High-impedance output current Short-circuit low-level output current VO = 0, VO = VCC, V 0.33 0.5 0.43 0.6 1 3.6 5.1 8.3 –0.43 –0.6 –1 –3.6 –5.1 –8.3 V mA mA See Figure 5 and Note 7 –20 mA See Figure 5 and Note 7 20 mA ±100 µA 7 kΩ VCC= 0 or 5 V, 0.3 V ≤ VO ≤ VCC VI = ±3 V to ±25 V Input resistance V mV 3 5 NOTE 7: Not more than one output should be shorted at one time. receiver switching characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX tPHL tPLH Propagation delay time, high- to low-level output 400 900 Propagation delay time, low- to high-level output 400 900 tTLH tTHL Transition time low- to high-level output 200 500 Transition time high- to low-level output 200 400 tSK(P) tPZL Pulse skew |tPLH – tPHL| 200 425 50 100 tPZH tPLZ Receiver output-enable time to high-level output 50 100 Receiver output-disable time from low-level output 50 100 tPHZ tPHL Receiver output-disable time from high-level output 50 100 Propagation delay time, high- to low-level output (WAKE-UP mode) 500 1500 tPLH Propagation delay time, low- to high-level output (WAKE-UP mode) 500 1500 STANDBY mode CL = 50 pF, S Figures See Fi 4 and d7 Receiver output-enable time to low-level output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns µs µs ns 7 SN75LPE185 LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS WITH ENABLE SLLS256D – DECEMBER 1996 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION tw Inputs Outputs 3V 50% VI 50% 0V II IO VI CL VO tPLH VO RL tPHL VTR+ VTR+ 50% VTR– 50% VTR– VOH VOL tTHL tTLH NOTES: A. The pulse generator has the following characteristics: For CL < 1000 pF: tw = 4 µs, PRR = 250 kbit/s, ZO = 50 Ω, tr = tf < 50 ns. For CL = 2500 pF: tw = 8 µs, PRR = 125 kbit/s, ZO = 50 Ω, tr = tf < 50 ns. B. CL includes probe and jig capacitance. Figure 1. Driver Parameter Test Circuit and Waveform Inputs Outputs II VDD VCC GND VSS IO VI VO Figure 2. Driver IOS Test Inputs Outputs II VI IO VO Figure 3. Receiver VIT Test tw Inputs Outputs II 50% VIL IO tPLH CL VI VIH 50% VI VO VO tPHL 50% 10% 90% tTLH 90% 50% 10% 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VOL tTHL NOTES: A. The pulse generator has the following characteristics: tw = 4 µs, PRR = 250 kbit/s, ZO = 50 Ω, tr = tf < 50 ns. B. CL includes probe and jig capacitance. Figure 4. Receiver Parameter Test Circuit and Waveform VOH SN75LPE185 LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS WITH ENABLE SLLS256D – DECEMBER 1996 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION Inputs Outputs II IO VI VCC GND VO Figure 5. Receiver IOS Test From Output Under Test 3V CL = 15 pF (see Note A) RL 50% VI 0V tPZL LOAD CIRCUIT 50% 0V VO Waveform 1 (see Note B) 50% tPZH VO Waveform 2 (see Note B) tPLZ VOL + 0.3 V VOL tPHZ 50% VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, tr = tf < 50 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 6. Driver 3-State Parameter Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN75LPE185 LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS WITH ENABLE SLLS256D – DECEMBER 1996 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION 4V From Output Under Test S1 5k Ω TEST S1 tPHL/tPLH tPLZ/tPZL tPHZ/tPZH Open 4V GND Open GND CL = 50 pF (see Note A) LOAD CIRCUIT 3V 50% VI 50% 0V tPZL 4V VO Waveform 1 (see Note B) 50% tPZH VO Waveform 2 (see Note B) tPLZ VOL + 0.3 V VOL tPHZ 50% VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, tr = tf < 50 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 7. Receiver 3-State Parameter Test Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LPE185 LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS WITH ENABLE SLLS256D – DECEMBER 1996 – REVISED OCTOBER 1998 APPLICATION INFORMATION receiver output states RECEIVER KNOWN OUTPUT STATES DURING POWER-DOWN, STANDBY, OR WAKE-UP MODES RECEIVER NUMBER SIGNAL NAME RECEIVER OUTPUT RY1 DCD HIGH RY2 DSR HIGH RY3 RX LOW RY4 CTS HIGH RY5 RI HIGH fault protection during power down Diodes placed in series with the VDD and VSS leads protect the SN75LPE185 in the fault condition, in which the device outputs are shorted to ±15 V and the power supplies are at low voltage and provide low-impedance paths to ground. VDD Output SN75LPE185 Output SN75LPE185 VSS Figure 8. Power-Supply Protection to Meet Power-Off Fault Conditions of TIA/EIA-232-F POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN75LPE185 LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS WITH ENABLE SLLS256D – DECEMBER 1996 – REVISED OCTOBER 1998 APPLICATION INFORMATION WAKE-UP mode While in the WAKE-UP mode, all the drivers and receivers of the SN75LPE185 device are in the high-impedance state, except for receiver 5, which can be used as a Ring Indicator function. In this mode, the current drawn from the power supplies is low, to conserve power. In today’s PCs, board designers are becoming more concerned about power consumption. The flexibility of the SN75LPE185 during WAKE-UP mode allows the designer to operate the device at auxiliary power-supply voltages below specified levels. The SN75LPE185 functions properly during WAKE-UP mode, using the following power-supply conditions: (a) VCC = 4.75 V, VDD = 9 V, and VSS = –9 V (data-sheet specifications) (b) VCC = 5 V, VDD = 5 V, and VSS = –5 V (c) VCC = 5 V, VDD = open, and VSS = open (d) VCC = 5 V, VDD = 5 V, and VSS is shorted to the most negative supply. Condition (a) describes the minimum supply voltages necessary for the device to comply fully to specifications. Conditions (b) and (d) describe the condition where a –5-V supply is not available during auxiliary power. In this case, VSS must be shorted to the most negative supply (i.e., GND or a voltage source close to, but below GND). Condition (c) states VDD and VSS power supplies can be shut off. In all cases, GND is understood to be 0 V, and the power supply voltages should never exceed the absolute maximum ratings. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated