HD151BF854 2.5 V PLL Clock Buffer for DDR Application REJ03D0809-0500 (Previous: ADE-205-696D) Rev.5.00 Apr 07, 2006 Description The HD151BF854 is a high-performance, low-skew, low-jitter, PLL clock buffer. It is specifically designed for use with DDR (Double Data Rate) PC motherboard application. Features • • • • • • • Designed for DDR200/266/333/400 PC mother board clock buffering Supports 60 MHz to 210 MHz operation range Distributes one to six differential clock outputs pairs Spread spectrum clock compatible External feedback pin (FBIN) is used to synchronize the outputs to the clock input Supports 2.5 V analog supply voltage (AVDD), and 2.5 V VDD Ordering Information Part Name HD151BF854SSEL Package Code (Previous Code) Package Type SSOP-28 pin Package Abbreviation SS PRSP0028JA-A (FP-28DSAV) Taping Abbreviation (Quantity) EL (1,000 pcs / Reel) Key Specifications • Supply voltages: VDD = AVDD = 2.5 V±0.2 V • Output clock cycle to cycle jitter = ±75 ps • Output clock pin to pin skew = 150 ps Function Table Inputs Outputs PLL AVDD CLK Yn Yn FBOUT GND L L H L Bypass / Off GND H H L H Bypass / Off 2.5 V (typ.) L L H L Running 2.5 V (typ.) H H L H Running H: High level L: Low level Rev.5.00 Apr 07, 2006 page 1 of 7 HD151BF854 Pin Arrangement Y0 1 28 GND Y0 2 27 Y5 VDD 3 26 Y5 Y1 4 25 Y4 Y1 5 24 Y4 GND 6 23 VDD NC 7 22 NC CLKIN 8 21 NC NC 9 20 FBIN AVDD 10 19 FBOUT AGND 11 18 NC VDD 12 17 Y3 Y2 13 16 Y3 Y2 14 15 GND (Top view) Pin Functions Pin name AGND AVDD No. 11 10 Type Ground Power CLKIN 8 Input Clock input. CLKIN provides the clock signal to be distributed by the HD151BF854 clock buffer. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN 20 Input Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLKIN and FBIN so that there is nominally zero phase error between CLKIN and FBIN. FBOUT 19 Output GND VDD Y 6, 15, 28 3, 12, 23 Ground Power Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. Ground Power supply 2, 4, 13, 17, 24, 26 Output Clock outputs. (+Clock) These outputs provide low-skew copies of CLK. Y 1, 5, 14, 16, 25, 27 Output Bar clock outputs. (–Clock) These outputs provide low-skew copies of CLK. NC 7, 9, 18, 21, NC 22 Rev.5.00 Apr 07, 2006 page 2 of 7 Description Analog ground. AGND provides the ground reference for the analog circuitry. Analog power supply. AVDD provides the power reference for the analog circuitry. In addition, AVDD can be used to bypass the PLL for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Don’t connect any VDD or GND. HD151BF854 Logic Diagram AVDD 10 2 1 Y0 4 5 Y1 Y1 Test Logic 13 14 Y2 Y2 17 16 Y3 24 25 Y4 26 27 Y5 19 FBOUT Y3 Y4 8 CLKIN PLL FBIN Y0 Y5 20 Note: All inputs and outputs are associated with VDDQ = 2.5 V. Absolute Maximum Ratings Item Symbol VDD Ratings –0.5 to 3.6 Unit V Output voltage *1 VIC VI VO –0.5 to 3.6 –0.5 to VDD+0.5 –0.5 to VDD+0.5 V V V Input clamp current Output clamp current Continuous output current IIK IOK IO –50 –50 ±50 mA mA mA 0.7 W –65 to +150 °C Supply voltage Input voltage Maximum power dissipation at Ta = 55°C (in still air) Storage temperature Notes: Tstg Conditions CLKIN VI < 0 VO < 0 VO = 0 to VDD Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Rev.5.00 Apr 07, 2006 page 3 of 7 HD151BF854 Recommended Operating Conditions Item Supply voltage Output supply voltage DC input signal voltage High level input voltage High level input voltage Low level input voltage Output differential cross point voltage Output current Symbol AVDD VDD VIH VIH VIL VOX IOH IOL SR Ta Input clock slew rate Operating temperature Min 2.3 2.3 –0.3 1.7 1.7 –0.3 Typ 2.5 2.5 — — — — Max 2.7 2.7 VDD+0.3 3.6 VDD+0.3 0.7 Unit V V V V V V 0.5×VDD –0.2 — — 1 0 — 0.5×VDD +0.2 –12 12 — 70 V — — — — Conditions All pins CLKIN FBIN CLKIN, FBIN mA V/ns °C Note: Unused inputs must be held high or low to prevent them from floating. Electrical Characteristics VIK Min — Typ *1 — Max –1.2 Unit V VOH VDD–0.2 — VDD 0.2 0.6 10 IOH = –100 µA, VDD = 2.3 to 2.7 V IOH = –12 mA, VDD = 2.3 V IOL = 100 µA, VDD = 2.3 to 2.7 V IOL = 12 mA, VDD = 2.3 V II — — — — — V 1.7 — — –10 µA VI = 0 V or 2.7 V, VDD = 2.7 V, CLKIN, FBIN Analog supply current AICC — — 12 mA VDD = AVDD = 2.7 V, 170 MHz Dynamic supply current DICC — 250 300 mA CI CDi 2.5 –0.25 — — 3.5 0.25 pF pF VDD = AVDD = 2.7 V, 170 MHz, All Yn, Yn, = open CLKIN and FBIN Item Input clamp voltage (All inputs) Output voltage Symbol VOL Input current Input capacitance*2 Delta input capacitance*2 Test Conditions II = –18 mA, VDD = 2.3 V Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. 2. Target of design, not 100% tested in production. Rev.5.00 Apr 07, 2006 page 4 of 7 HD151BF854 Switching Characteristics Ta = 25°C, VDD = AVDD = 2.5V Item Symbol tPER tHPER tCC tsPE tsk fCLK(O) fCLK(A) Min Typ Max Unit Test Conditions & Notes Period jitter — |75| — ps *7, 8 Half period jitter — |120| — ps *8 Cycle to cycle jitter — |75| — ps Static phase offset — |150| — ps *4, 5 Output clock skew — 150 — ps Operating clock frequency 60 — 210 MHz *1, 2 Application clock frequency 80 166 210 MHz *1, 3 Slew rate 1.0 — 2.0 V/ns 20% to 80% Stabilization time — — 0.1 ms *6 Notes: Target of design, not 100% tested in production. 1. The PLL must be able to handle spread spectrum induced skew. (the specification for this frequency modulation can be found in the latest Intel PC100 Registered DIMM specification) 2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) 3. Application clock frequency indicates a range over which the PLL must meet all timing parameters. 4. Assumes equal wire length and loading on the clock output and feedback path. 5. Static phase offset does not include jitter. 6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of it’s feedback signal to it’s reference signal after power on. 7. Period jitter defines the largest variation in clock period, around a nominal clock period. 8. Period jitter and half period jitter are separate specifications that must be met independently of each other. Rev.5.00 Apr 07, 2006 page 5 of 7 HD151BF854 Zo = 60 Ω Yn *1 RT = 120 Ω Yn C = 14 pF Zo = 60 Ω *1 C = 14 pF Note: 1. SDRAM Cin 3.5 pF ×4 Figure 1 Clock outputs test circuit Yn Yn tcycle n+1 tcycle n t CC = (tcycle n) - (tcycle n+1) Figure 2 Cycle to cycle jitter Yx Yx Yy Yy tsk Figure 3 Output clock skew (Differential clock output) Rev.5.00 Apr 07, 2006 page 6 of 7 HD151BF854 Package Dimensions JEITA Package Code P-SSOP28-5.3x10.2-0.65 RENESAS Code PRSP0028JA-A *1 Previous Code FP-28DSA/FP-28DSAV MASS[Typ.] 0.255g D F 28 15 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. HE c1 Index mark c *2 E bp b1 Terminal cross section 1 14 e *3 bp x M L1 A Z Reference Dimension in Millimeters Symbol A1 θ y Rev.5.00 Apr 07, 2006 page 7 of 7 L Detail F D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 10.20 10.50 5.30 0.00 0.10 0.20 2.10 0.24 0.32 0.40 0.30 0.17 0.22 0.27 0.20 0° 8° 7.70 7.90 8.10 0.65 0.13 0.10 1.025 0.45 0.60 0.75 1.30 Sales Strategic Planning Div. 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