HD74CDCV857A 2.5-V Phase-lock Loop Clock Driver REJ03D0136–0300Z (Previous ADE-205-693B (Z)) Rev.3.00 Oct.09.2003 Description The HD74CDCV857A is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is specifically designed for use with DDR (Double Data Rate) synchronous DRAMs. Features • • • • • • • • • DDR333 / PC2700-Compliant, also meets DDR266 / PC2100 requirement. Supports 60 MHz to 170 MHz operation range Distributes one differential clock input pair to ten differential clock outputs pairs Supports spread spectrum clock requirements meeting the PC100 SDRAM registered DIMM specification External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input Supports 2.5V analog supply voltage (AVCC), and 2.5 V VDDQ No external RC network required Sleep mode detection 48pin TSSOP (Thin Shrink Small Outline Package) Function Table Inputs AVCC PWRDWN CLK GND GND X X 2.5 V 2.5 V 2.5 V H H L L H H X L H H L L H H L L H H L Input clock frequency 60 to 170 MHz → 0 MHz H: L: X: Z: Notes: CLK : Outputs : Y Y FBOUT FBOUT : PLL : : : : : : : L H Z Z L H Z H L Z Z H L Z L H Z Z L H Z Bypassed / off *1 Bypassed / off *1 off off on on off High level Low level Don’t care High impedance 1. Bypassed mode is used for RENESAS test mode. Rev.3.00, Oct.09.2003, page 1 of 12 H L Z Z H L Z : : : : : : : HD74CDCV857A Pin Arrangement 48 GND GND 1 Y0 2 47 Y5 Y0 3 46 Y5 V DDQ 4 45 V DDQ Y1 5 44 Y6 Y1 6 43 Y6 GND 7 42 GND GND 8 41 GND Y2 9 40 Y7 Y2 10 39 Y7 V DDQ 11 38 V DDQ V DDQ 12 37 PWRDWN CLK 13 36 FBIN CLK 14 35 FBIN V DDQ 15 34 V DDQ AV CC 16 33 FBOUT AGND 17 32 FBOUT 31 GND GND 18 Y3 19 30 Y8 Y3 20 29 Y8 V DDQ 21 28 V DDQ Y4 22 27 Y9 Y4 23 26 Y9 GND 24 25 GND (Top view) Rev.3.00, Oct.09.2003, page 2 of 12 HD74CDCV857A Pin Function Pin name No. Type Description AGND 17 Ground Analog ground. AGND provides the ground reference for the analog circuitry. AVCC 16 Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. This bypass mode is used for RENESAS test. CLK, CLK 13, 14 I Clock input. CLK provides the clock signal to be distributed by the HD74CDCV857A clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. Differential input FBIN, FBIN 35, 36 I Differential input FBOUT, FBOUT 32, 33 O Differential output Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. PWRDWN 37 I Output bank enable. PWRDWN is the output enable for all outputs. When PWRDWN is low, VCO will stop and all outputs are disabled to a high impedance state. When PWRDWN will be returned high, PLL will re-synchroniz to CLK frequency and all outputs are enabled. GND 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 Ground Ground VDDQ 4, 11, 12, 15, 21, 28, 34, 38, 45 Power Power supply Y 3, 5, 10, 20, O 22, 27, 29, Differential 39, 44, 46 output Clock outputs. These outputs provide low-skew copies of CLK. Y 2, 6, 9, 19, 23, 26, 30, 40, 43, 47 Clock outputs. These outputs provide low-skew copies of CLK. O Differential output Rev.3.00, Oct.09.2003, page 3 of 12 HD74CDCV857A Logic Diagram PWRDWN AVCC CLK CLK 37 16 Power down and Test Logic 13 14 PLL FBIN FBIN 36 35 Note: All inputs and outputs are associated with VDDQ = 2.5 V. Rev.3.00, Oct.09.2003, page 4 of 12 3 2 Y0 5 6 Y1 10 9 Y2 20 19 Y3 22 23 Y4 46 47 Y5 44 43 Y6 39 40 Y7 29 30 Y8 27 26 Y9 32 33 FBOUT Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 FBOUT HD74CDCV857A Absolute Maximum Ratings Item Symbol Ratings Supply voltage VDDQ –0.5 to 3.6 V Input voltage VI –0.5 to VDDQ+0.5 V Output voltage *1 VO –0.5 to VDDQ +0.5 V Input clamp current IIK –50 mA VI < 0 Output clamp current IOK –50 mA VO < 0 Continuous output current IO ±50 mA VO = 0 to VDDQ Supply current through each VDDQ or GND IVDDQ or IGND ±100 mA Maximum power dissipation at Ta = 55°C (in still air) 0.7 W –65 to +150 °C Storage temperature Notes: Tstg Unit Conditions Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Rev.3.00, Oct.09.2003, page 5 of 12 HD74CDCV857A Recommended Operating Conditions Item Symbol Min Typ Max Unit Conditions Notes Output supply voltage VDDQ 2.3 2.5 2.7 V Supply voltage AVCC VDDQ–0.12 VDDQ 2.7 V DC input signal voltage VIN –0.3 — VDDQ+0.3 V All pins High level input voltage VIHG 1.7 — VDDQ+0.3 V PWRDWN input pin Low level input voltage VILG –0.3 — 0.7 V PWRDWN input pin Input differential voltage VID 0.36 — VDDQ+0.6 V Output differential voltage VOD 0.70 — VDDQ+0.6 V Input differential-pair cross voltage VIX VDDQ/2 –0.2 — VDDQ/2 +0.2 V 2, 3 Output differential-pair cross voltage VOX VDDQ/2 –0.15 — VDDQ/2 +0.15 V 2, 3 Output current IOH — — –12 mA IOL — — 12 mA Input clock slew rate tSL(I) 1 — 4 V/ns 20% – 80% 3 Operating temperature Ta 0 — 70 °C Notes: 1 3 3 Inputs pins must be prevent from floating. Feedback inputs (FBIN, FBIN) may float when the device is in low power mode. 1. DC input signal voltage specifies the allowable dc execution of differential input. 2. Differential cross point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing. (See figure1) 3. Guaranteed by design, not 100% tested in production. CLK VID CLK Crossing point Figure 1 Differential input levels Rev.3.00, Oct.09.2003, page 6 of 12 HD74CDCV857A Electrical Characteristics Item Symbol Min Typ *1 Max Unit Test Conditions — –1.2 V II = –18 mA, VDDQ = 2.3 V V IOH = –100 µA, VDDQ = 2.3 to 2.7 V Input clamp CLK, CLK VIK voltage FBIN, FBIN, G — Output voltage VDDQ–0.1 — — 1.7 — — IOH = –12 mA, VDDQ = 2.3 V — — 0.1 IOL = 100 µA, VDDQ = 2.3 to 2.7 V — — 0.6 IOL = 12 mA, VDDQ = 2.3 V VOH VOL Notes Input current II –10 — 10 µA VI = 0 V to 2.7 V, VDDQ = 2.7 V Input capacitance CI — 2.5 — pF CLK and CLK, FBIN and FBIN 2 Supply current DICC — 200 350 mA 3 AICC — 9 12 f = 170 MHz, VDDQ = AVCC = 2.7 V ICCpd — 100 200 Supply current in power down mode Note: µA 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. 2. Guaranteed by design, not 100% tested in production. 3. All outputs are loaded as shown in Figure2. Rev.3.00, Oct.09.2003, page 7 of 12 HD74CDCV857A Switching Characteristics Item Symbol Min Period jitter tPER –75 Half period jitter tHPER –100 Cycle to cycle jitter tCC –75 Static phase offset tSPE Output clock skew tsk Typ Max Unit Test Conditions Notes — 75 ps See figure 6, 9 7, 8 — 100 ps See figure 7, 9 8, 10 — 75 ps See figure 5, 9 10 –50 — 50 ps See figure 3, 9 4, 5, 9, 10 — — 100 ps See figure 4, 9 Operating clock frequency fCLK(O) 60 — 200 MHz See figure 9 1, 2 Application clock frequency fCLK(A) 80 167 170 MHz See figure 9 1, 3 Input clock duty cycle tDC 40 — 60 % Output clock Slew rate tSL(O) 1.0 — 2.0 V/ns See figure 9 20% – 80% PLL stabilization time tSTAB — — 0.1 ms See figure 9 SSC modulation frequency 30 — 50 KHz 10 SSC clock input frequency deviation 0.00 — –0.50 % 10 PLL loop bandwidth — 3 — MHz 10 10 6, 10 Notes: 1. The PLL must be able to handle spread spectrum induced skew (the specification for this frequency modulation can be found in the latest Intel PC100 Registered DIMM specification) 2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. 3. Application clock frequency indicates a range over which the PLL must meet all timing parameters. 4 Assumes equal wire length and loading on the clock output and feedback path. 5. Static phase offset does not include jitter. 6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. 7. Period jitter defines the largest variation in clock period, around a nominal clock period. 8. Period jitter and half–period jitter are independent from each other. 9. Conditions at VDDQ = 2.5 V, Ta = 25°C. 10. Guaranteed by design, not 100% tested in production. Rev.3.00, Oct.09.2003, page 8 of 12 HD74CDCV857A Differential clock outputs are directly terminated by a 120 Ω resistor. Figure 2 is typical usage conditions of outputs load. V DDQ V DDQ Device under OUT test RT = 120 Ω C = 14 pF OUT C = 14 pF Figure 2 Differential signal using direct termination resistor CLKIN CLKIN FBIN FBIN tSPE Figure 3 Static phase offset FBOUT FBOUT Yx Yx tsk Yx Yx Yx' Yx' tsk Figure 4 Output skew Rev.3.00, Oct.09.2003, page 9 of 12 HD74CDCV857A Yx, FBOUT Yx, FBOUT t cycle n t cycle n+1 t cc = t cycle n - t cycle n+1 Figure 5 Cycle to cycle jitter Yx, FBOUT Yx, FBOUT t cycle n Yx, FBOUT Yx, FBOUT 1 fo t PER = t cycle n - 1 fo Figure 6 Period jitter Yx, FBOUT Yx, FBOUT t half period n t half period n+1 Yx, FBOUT Yx, FBOUT 1 fo t HPER = t half period n - 1 2*fo Figure 7 Half period jitter Rev.3.00, Oct.09.2003, page 10 of 12 HD74CDCV857A Yx, FBOUT Yx, FBOUT t half cycle n t half cycle n+1 t HCC = t half cycle n - t half cycle n+1 Figure 8 Half cycle to cycle jitter V DDQ V DDQ /2 AVCC AVCC /2 Device under OUT test OUT AGND GND Z = 60 Ω Z = 60 Ω -VDDQ /2 V DDQ V DDQ AVCC AV CC Device under OUT test Oscillo scope RT = 10 Ω C= 14 pF -VDDQ /2 RT = 10 Ω C= 14 pF -VDDQ /2 Z = 60 Ω Z = 60 Ω AGND GND Figure 9 Output load test circuit Rev.3.00, Oct.09.2003, page 11 of 12 RT = 50 Ω Z = 50 Ω RT = 50 Ω RT = 120 OUT Z = 50 Ω C= 14 pF C= 14 pF HD74CDCV857A Package Dimensions As of January, 2002 12.5 12.7 Max Unit: mm 25 6.10 48 1 *0.19 ± 0.05 0.50 24 0.08 M 1.0 8.10 ± 0.20 0.65 Max *Pd plating Rev.3.00, Oct.09.2003, page 12 of 12 0.10 ± 0.05 0.10 *0.15 ± 0.05 1.20 Max 0˚ – 8˚ 0.50 ± 0.1 Package Code JEDEC JEITA Mass (reference value) TTP–48DBV — — 0.20 g Sales Strategic Planning Div. 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