™ Le79R70 Ringing Subscriber Line Interface Circuit VE580 Series APPLICATIONS Device1 Integrated Access Devices (IADs) Network Interface Units (NIUs) Cable Modems DSL Modems Set Top / House Side Boxes Pain Gain Tube Le79R70-1DJC 32-pin PLCC, Pol. Rev. (Green package) Tube Le79R70-1FQC 32-pin QFN, Pol. Rev. (Green package) Tray 1. Zarlink reserves the right to fulfill all orders for this device with parts marked with the "Am" part number prefix until all inventory bearing this mark has been depleted. Note that parts marked with either the "Am" or the "Le" part number prefix are equivalent devices in terms of form, fit, and function—the prefix appearing on the topside mark is the only difference. 2. The green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment. 3. Due to size constraints, QFN devices are marked by omitting the “Le” prefix and the performance grade dash character. For example, Le79R70-1QC is marked 79R701QC. 4. For delivery using a tape and reel packing system, add a "T" suffix to the OPN (Ordering Part Number) when placing an order. Voice over ISDN or T1/E1 Smart Residential Gateways Ideal for ISDN-TA and set top applications On-chip ringing with on-chip ring-trip detector Low Standby state power Battery operation: Packing4 32-pin PLCC, No Pol. Rev. (Green package) FXS Cards WLL, APON, FITL, NGN, and all other short-loop CPE/ Enterprise telephony applications Package Type2, 3 Le79R70DJC Intelligent PBX FEATURES ORDERING INFORMATION — VBAT1: –40 V to –67 V — VBAT2: –19 V to VBAT1 On-chip battery switching and feed selection On-hook transmission Polarity reversal option Programmable constant-current feed Programmable open circuit voltage Programmable loop-detect threshold Current gain = 1000 Two-wire impedance set by single component Ground-key detector Tip Open state for ground-start lines Internal VEE regulator (no external –5 V power supply required) Two on-chip relay drivers and snubber circuits Space-saving package options (8x8 QFN) RELATED LITERATURE DESCRIPTION The Le79R70 Ringing Subscriber Line Interface Circuit (RSLIC) device is a bipolar monolithic SLIC that offers on-chip ringing. Designers can achieve significant cost reductions at the system level for short-loop applications by integrating the ringing function on chip. Examples of such applications would be ISDN Terminal Adaptors and set top boxes. Using a CMOScompatible input waveform and wave shaping R-C network, the Le79R70 Ringing SLIC device can provide trapezoidal wave ringing to meet various design requirements. See the Le79R70 Block Diagram, on page 3. 080917 VE790 Series RSLIC Device Product Brief 080158 Le79R70/79/100/101 Ringing SLIC Devices Technical Overview 080255 Le71HE0040J Evaluation Board User’s Guide 080753 Le58QL02/021/031 QLSLAC™ Data Sheet Document ID#: 080211 Date: Sep 19, 2007 Rev: J Version: 2 Distribution: Public Document Le79R70 Data Sheet TABLE OF CONTENTS Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Environmental Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Relay Driver Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Ring-Trip Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Test Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 32-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision A to B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision B to C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision C to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision D to E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision E to F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision F to G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision G1 to H1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision H1 to I1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision I1 to J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision J1 to J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2 Zarlink Semiconductor Inc. Le79R70 Data Sheet PRODUCT DESCRIPTION The Zarlink family of subscriber line interface circuit (SLIC) products provide the telephone interface functions required throughout the worldwide market. Zarlink SLIC devices address all major telephony markets including central office (CO), private branch exchange (PBX), digital loop carrier (DLC), fiber-in-the-loop (FITL), radio-in-the-loop (RITL), hybrid fiber coax (HFC), and video telephony applications. The Zarlink SLIC devices offer support of BORSHT (battery feed, over voltage protection, ringing, supervision, hybrid, and test) functions with features including current limiting, on-hook transmission, polarity reversal, tip-open, and loop-current detection. These features allow reduction of line card cost by minimizing component count, conserving board space, and supporting automated manufacturing. The Zarlink SLIC devices provide the two- to four-wire hybrid function, DC loop feed, and two-wire supervision. Two-wire termination is programmed by a scaled impedance network. Transhybrid balance can be achieved with an external balance circuit or simply programmed using a companion Zarlink codec/filter, such as the Le58QL0xx Quad SLAC (QLSLAC™) device. The Le79R70 Ringing SLIC device is a bipolar monolithic SLIC that offers on-chip ringing. Now designers can achieve significant cost reductions at the system level for short-loop applications by integrating the ringing function on chip. Examples of such applications would be ISDN Terminal Adaptors and set top boxes. Using a CMOS-compatible input waveform and wave shaping R-C network, the Le79R70 Ringing SLIC can provide trapezoidal wave ringing to meet various design requirements. In order to further enhance the suitability of this device in short-loop, distributed switching applications, Zarlink has maximized power savings by incorporating battery switching on chip. The Le79R70 Ringing SLIC device switches between two battery supplies such that in the Off-hook (active) state, a low battery is used to save power. In order to meet the Open Circuit voltage requirements of fax machines and maintenance termination units (MTU), the SLIC automatically switches to a higher voltage in the On-hook (standby) state. Like all of the Zarlink SLIC devices, the Le79R70 Ringing SLIC device supports on-hook transmission, ring-trip detection and programmable loop-detect threshold. The Le79R70 Ringing SLIC device is a programmable constant-current feed device with two on-chip relay drivers to operate external relays. This unique device is available in the proven Zarlink 75 V bipolar process. Figure 1. Le79R70 Block Diagram Relay Driver RTRIP1 RTRIP2 RYOUT2 RYE Relay Driver A(TIP) Ring-Trip Detector Ground-Key Detector HPA Two-Wire Interface Input Decoder and Control D1 D2 C1 C2 C3 Off-Hook Detector E1 DET Signal Transmission RD VTX RSN HPB B(RING) RYOUT1 Power-Feed Controller RINGIN RDC RDCR VBAT2 VBAT1 RSGL RSGH B2EN Switch Driver VCC VNEG BGND AGND/DGND 3 Zarlink Semiconductor Inc. Le79R70 Data Sheet VBAT2 BGND B(RING) 3 2 1 32 RD VCC 4 A(TIP) RYOUT2 CONNECTION DIAGRAM 31 30 RYE 5 29 RTRIP1 RYOUT1 6 28 RTRIP2 B2EN 7 27 HPB VBAT1 8 26 HPA 25 RINGIN 32-Pin PLCC E1 10 24 RDCR C3 11 23 VTX C2 12 22 VNEG DET 13 21 RSN RYE RSGL RD 29 28 27 26 AGND/DGND RSGH A(TIP) 30 RDC NC B(RING) 31 32 1 19 20 RTRIP1 D2 BGND 16 17 18 VBAT2 15 VCC 14 C1 9 RYOUT2 D1 25 24 RTRIP2 RYOUT1 2 23 HPB B2EN 3 22 HPA VBAT1 4 21 RINGIN 32-pin QFN D1 5 20 RDCR E1 6 19 VTX C3 7 18 VNEG C2 8 13 C1 D2 N/C RSGH 14 15 RDC 12 17 16 RSN AGND/ DGND 11 RSGL 10 DET Exposed Pad 9 Notes: 1. Pin 1 is marked for orientation. 2. NC = No connect 3. RSVD = Reserved. Do not connect to this pin. 4. The thermally enhanced QFN package features an exposed pad on the underside which must be electrically tied to VBAT1. 4 Zarlink Semiconductor Inc. Le79R70 Data Sheet Pin Descriptions Pin Names Type Description AGND/DGND Gnd Analog and digital ground are connected internally to a single pin. A(TIP) Output Output of A(TIP) power amplifier. B2EN Input VBAT2 enable. Logic Low enables operation from VBAT2. Logic High enables operation from VBAT1. TTL compatible. BGND Gnd Battery (power) ground B(RING) Output Output of B(RING) power amplifier. C3–C1 Input Decoder. TTL compatible. C3 is MSB and C1 is LSB. D1 Input Relay1 control. TTL compatible. Logic Low activates the Relay1 relay driver. D2 Input (Option) Relay2 control. TTL compatible. Logic Low activates the Relay2 relay driver. DET Output Detector. Logic Low indicates that the selected detector is tripped. Logic inputs C3–C1 and E1 select the detector. Open-collector with a built-in 15 kΩ pull-up resistor. E1 Input (Option) A logic High selects the off-hook detector. A logic Low selects the ground-key detector. TTL compatible. HPA Capacitor High-pass filter capacitor. A(TIP) side of high-pass filter capacitor. HPB Capacitor High-pass filter capacitor. B(RING) side of high-pass filter capacitor. RD Resistor Detect resistor. Threshold modification and filter point for the off-hook detector. RDC Resistor DC feed resistor. Connection point for the DC-feed current programming network, which also connects to the receiver summing node (RSN). VRDC is negative for normal polarity and positive for reverse polarity. RDCR — Connection point for feedback during ringing. RINGIN Input Ring Signal Input. Pin for ring signal input. Square-wave shaped by external RC filter. Requires 50% duty cycle. CMOS-compatible input. RSGH Input Saturation Guard High. Pin for resistor to adjust Open Circuit voltage when operating from VBAT1. RSGL Input Saturation Guard Low. Pin for resistor to adjust the anti-saturation cut-in voltage when operating from both VBAT1 and VBAT2. RSN Input The metallic current (AC and DC) between A(TIP) and B(RING) is equal to 1000 x the current into this pin. The networks that program receive gain, two-wire impedance, and feed resistance all connect to this node. RTRIP1 Input Ring-trip detector. Ring-trip detector threshold set and filter pin. RTRIP2 Input Ring-trip detector threshold offset (switch to VBAT1). For power conservation in any non-ringing state, this switch is open. RYE Output Common Emitter of RYOUT1/RYOUT2. Emitter output of RYOUT1 and RYOUT2. Normally connected to relay ground. RYOUT1 Output Relay/switch driver. Open-collector driver with emitter internally connected to RYE. RYOUT2 Output (Option) Relay/switch driver. Open-collector driver with emitter internally connected to RYE. VBAT1 Battery Battery supply and connection to substrate. VBAT2 Battery Power supply to output amplifiers. Connect to off-hook battery through a diode. VCC Power Positive analog power supply. VNEG Power Negative analog power supply. This pin is the return for the internal VEE regulator. VTX Output Transmit Audio. This output is a 0.5066 gain version of the A(TIP) and B(RING) metallic AC voltage. VTX also sources the two-wire input impedance programming network. Exposed Pad Battery This must be electrically tied to VBAT1. 5 Zarlink Semiconductor Inc. Le79R70 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Storage temperature –55 to +150°C Ambient temperature under bias 0 to +70°C VCC with respect to AGND/DGND 0.4 to + 7 V VNEG with respect to AGND/DGND 0.4 V to VBAT2 VBAT2 VBAT2 to GND VBAT1 with respect to AGND/DGND: Continuous +0.4 to -80 V 10 ms +0.4 to -85 V BGND with respect to AGND/DGND +3 to -3 V A (TIP) or B (RING) to BGND: Continuous VBAT1 – 5 V+ 1 V 10 ms (F = 0.1 Hz) VBAT1 – 10 V+ 5 V 1 µs (F = 0.1 Hz) VBAT1 – 15 V+ 8 V 250 ns (F = 0.1 Hz) VBAT1 – 20 V+ 12 V Current from A (TIP) or B (RING) ± 150 mA RYOUT1, RYOUT2 current 75 mA RYOUT1, RYOUT2 voltage RYE to +7 V RYOUT1, RYOUT2 transient RYE to +10 V RYE voltage BGND to VBAT1 C3-C1, D2-D1, E1, B2EN and RINGIN: -0.4 V to VCC + 0.4 V Input voltage 1: Maximum continuous power dissipation, TA = 70° C In 32-pin PLCC package 1.67 W In 32-pin QFN package 3.00 W θJA Thermal Data: In 32-pin PLCC package 45° C/W 2 25° C/W In 32-pin QFN package ESD Immunity (Human Body Model) JESD22 Class 1C compliant Note: 1. Thermal limiting circuitry on the chip will shut down the circuit at a junction temperature of about 165ºC. Continuous operation above 145ºC junction temperature may degrade device reliability. 2. The thermal performance of a thermally enhanced package is assured through optimized printed circuit board layout. Specified performance requires that the exposed thermal pad be soldered to an equally sized exposed copper surface, which, in turn, conducts heat through multiple vias to a large internal copper plane. Package Assembly Green package devices are assembled with enhanced, environmental compatible lead-free, halogen-free, and antimony-free materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer leadfree board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly. Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile. OPERATING RANGES Environmental Ranges Zarlink guarantees the performance of this device over the commercial (0º C to 70º C) temperature range by conducting electrical characterization and by conducting a production test with single insertion coupled to periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component Reliability Assurance Requirements for Telecommunications Equipment. 6 Zarlink Semiconductor Inc. Le79R70 Data Sheet Environmental Ranges Ambient Temperature 0 to 70° C Electrical Ranges VCC 4.75 V to 5.25 V VNEG -4.75 V to VBAT2 VBAT1 -40 to -67 V VBAT2 -19 V to VBAT1 AGND/DGND 0V BGND with respect to AGND/DGND -100 mV to +100 mV Load resistance on VTX to GND 20 kΩ min Note: The Operating Ranges define those limits between which the functionality of the device is guaranteed. 7 Zarlink Semiconductor Inc. Le79R70 Data Sheet ELECTRICAL CHARACTERISTICS Description Test Conditions (See Note 1) Min 200 Hz to 3.4 kHz (Test Circuit D) 26 Typ Max Unit Note 3 20 dB 1, 4, 6 Ω 4 +50 mV 20 Ω 4 Transmission Performance 2-wire return loss ZVTX, analog output impedance VVTX, analog output offset voltage –50 ZRSN, analog input impedance 1 Overload level, 2-wire and 4-wire, off hook Active state 2.5 Vpk 2a Overload level, 2-wire On hook, RLAC = 600 Ω 0.88 Vrms 2b THD (Total Harmonic Distortion) +3 dBm, BAT2 = –24 V THD, on hook, OHT state 0 dBm, RLAC = 600 Ω, BAT1 = –67 V dB 5 –64 –50 –40 Longitudinal Performance (See Test Circuit C) Longitudinal to metallic L-T, L-4 balance 200 Hz to 3.4 kHz 40 Longitudinal signal generation 4-L 200 Hz to 800 Hz, Normal polarity 40 Longitudinal current per pin (A or B) Active or OHT state 12 Longitudinal impedance at A or B 0 to 100 Hz, TA = +25°C dB 28 mArms 25 Ω/pin 4 Idle Channel Noise C-message weighted noise +7 +14 dBrnC Psophometric weighted noise –83 –76 dBmp 4 Insertion Loss and Four- to Four-Wire Balance Return Signal (See Test Circuits A and B) Gain accuracy 4- to 2-wire 0 dBm, 1 kHz –0.20 0 +0.20 Gain accuracy 2- to 4-wire and 4- to 4-wire 0 dBm, 1 kHz –6.22 –6.02 –5.82 Gain accuracy 4- to 2-wire OHT state, on hook –0.35 0 +0.35 Gain accuracy 2- to 4-wire and 4- to 4-wire OHT state, on hook –6.37 –6.02 –5.77 Gain accuracy over frequency 300 to 3400 Hz relative to 1 kHz –0.10 +0.10 Gain tracking +3 dBm to –55 dBm relative to 0 dBm –0.10 +0.10 3, 4 Gain tracking OHT state, on hook 0 dBm to –37 dBm +3 dBm to 0 dBm –0.10 –0.35 +0.10 +0.35 3, 4 3 Group delay 0 dBm, 1 kHz 3 8 Zarlink Semiconductor Inc. 3 dB µs 1, 4, 6 Le79R70 Data Sheet ELECTRICAL CHARACTERISTICS (CONTINUED) Description Test Conditions (See Note 1) Min Typ Max 1.1IL Unit Note Line Characteristics IL, Loop-current accuracy IL in constant-current region, B2EN = 0 0.87IL IL IL, Long loops, Active state RLDC = 600 Ω, RSGL = open RLDC = 750 Ω, RSGL = short 20 20 21.7 0.8IL IL IL, Accuracy, Standby state V BAT1 – 10 V I L = -------------------------------------R L + 400 mA IL = constant-current region TA = 25°C ILLIM 1.2IL 18 Active, A and B to ground OHT, A and B to ground 27 39 55 55 110 4 IL, Loop current, Open Circuit state RL = 0 100 IA, Pin A leakage, Tip Open state RL = 0 100 IB, Pin B current, Tip Open state B to ground VA, Standby, ground-start signaling A to –48 V = 7 kΩ, B to ground = 100 Ω 34 –7.5 µA mA –5 4 V VAB, Open Circuit voltage 42 7 Power Supply Rejection Ratio (VRIPPLE = 100 mVrms), Active Normal State VCC 50 Hz to 3400 Hz 33 50 VNEG 50 Hz to 3400 Hz 30 40 VBAT1 50 Hz to 3400 Hz 30 50 VBAT2 50 Hz to 3400 Hz 30 50 dB 5 Power Dissipation On hook, Open Circuit state VBAT1 48 100 On hook, Standby state VBAT2 55 80 On hook, OHT state VBAT1 200 300 On hook, Active state VBAT1 220 350 Off hook, Standby state VBAT1 or VBAT2 RL = 300 Ω 2000 2800 Off hook, OHT state VBAT1 RL = 300 Ω 2000 2200 Off hook, Active state VBAT2 RL = 300 Ω 550 750 9 mW 9 Supply Currents ICC, On-hook VCC supply current Open Circuit state Standby state OHT state Active state–normal 3.0 3.2 6.2 6.5 4.5 5.5 8.0 9.0 INEG, On-hook VNEG supply current Open Circuit state Standby state OHT state Active state–normal 0.1 0.1 0.7 0.7 0.2 0.2 1.1 1.1 Open Circuit state Standby state OHT state Active state–normal 0.45 0.6 2.0 2.7 1.0 1.5 4.0 5.0 IBAT, On-hook VBAT supply current 9 Zarlink Semiconductor Inc. mA Le79R70 Data Sheet ELECTRICAL CHARACTERISTICS (continued) Description Test Conditions (See Note 1) Min Typ Max Unit Note Logic Inputs (C3–C1, D2–D1, E1, and B2EN) VIH, Input High voltage 2.0 VIL, Input Low voltage 0.8 IIH, Input High current –75 IIL, Input Low current –400 40 V µA Logic Output DET VOL, Output Low voltage IOUT = 0.8 mA, 15 kΩ to VCC 0.40 VOH, Output High voltage IOUT = –0.1 mA, 15 kΩ to VCC 2.4 BAT1 – 1- + 24 µA • 335 IRTD = -------------------------- RRT1 –10 VAB, Ringing Bat1 = –67 V, ringload = 1570 Ω 57 VAB Ringing offset VRINGIN = 2.5 V V Ring-Trip Detector Input Ring detect accuracy +10 % Ring Signal ∆VAB/∆VRINGIN (RINGIN gain) 61 Vpk 0 V 180 — Ground-Key Detector Thresholds Ground-key resistive threshold B to ground Ground-key current threshold B to ground 2 5 10 11 kΩ mA Loop Detector RLTH, Loop-resistance detect threshold Active, VBAT1 Active, VBAT2 Standby –20 –20 –12 20 20 12 % 8 Relay Driver Output (RELAY1 and 2) VOL, On voltage (each output) IOL = 30 mA +0.25 +0.4 VOL, On voltage (each output) IOL = 40 mA +0.30 +0.8 IOH, Off leakage (each output) VOH = +5 V Zener breakover (each output) IZ = 100 µA Zener on voltage (each output) IZ = 30 mA 100 6.6 7.9 11 RELAY DRIVER SCHEMATIC RYOUT2 RYOUT1 RYE BGND BGND 10 Zarlink Semiconductor Inc. V µA V 4 Le79R70 Data Sheet Notes: 1. Unless otherwise noted, test conditions are BAT1 = –67 V, BAT2 = –24 V, VCC = +5 V, VNEG = –5 V, RL = 600 Ω, RDC1 = 80 kΩ, RDC2 = 20 kΩ, RD = 75 kΩ, no fuse resistors, CHP = 0.018 µF, CDC = 1.2 µF, D1 = D2 = 1N400x, two-wire AC input impedance (ZSL) is a 600 Ω resistance synthesized by the programming network shown below. RSGL = open, RSGH = open, RDCR = 2 kΩ, RRT1 = 430 kΩ, RRT2 = 12 kΩ, CRT = 1.5 µF, RSLEW = 150 kΩ, CSLEW = 0.33 µF. VTX RT1 = 150 kΩ RT2 = 150 kΩ CT1 = 60 pF RSN RRX = 300 kΩ ~ VRX 2. a. Overload level is defined when THD = 1%. b. Overload level is defined when THD = 1.5%. 3. Balance return signal is the signal generated at VTX by VRX. This specification assumes that the two-wire AC load impedance matches the programmed impedance. 4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests. 5. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization. 6. Group delay can be greatly reduced by using a ZT network such as that shown in Note 1 above. The network reduces the group delay to less than 2 µs and increases 2WRL. The effect of group delay on line card performance may also be compensated for by synthesizing complex impedance with the QSLAC or DSLAC device. 7. Open Circuit VAB can be modified using RSGH. 8. RD must be greater than 56 kΩ. Refer to Table 2 for typical value of RLTH. 9. Lower power is achieved by switching into low-battery state in standby. Standby loop current is returned to VBAT1 regardless of the battery selected. Table 1. SLIC Decoding (DET) Output State C3 C2 C1 2-Wire Status E1 = 1 E1 = 0 Battery Selection 0 0 0 0 Open Circuit Ring trip Ring trip 1 0 0 1 Ringing Ring trip Ring trip 2 0 1 0 Active Loop detector Ground key 3 0 1 1 On-hook TX (OHT) Loop detector Ground key 4 1 0 0 Tip Open Loop detector Ground key B2EN = 1** 5 1 0 1 Standby Loop detector Ground key VBAT1 6* 1 1 0 Active Polarity Reversal Loop detector Ground key 7* 1 1 1 OHT Polarity Reversal Loop detector Ground key Notes: * Only –1 performance grade devices support polarity reversal. ** For correct ground-start operation using Tip Open, VBAT1 on-hook battery must be used. 11 Zarlink Semiconductor Inc. B2EN B2EN Le79R70 Table 2. Data Sheet User-Programmable Components Z T = 500 ( Z 2WIN – 2R F ) ZT is connected between the VTX and RSN pins. The fuse resistors are RF, and Z2WIN is the desired 2-wire AC input impedance. When computing ZT, the internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account. 1000 • ZT ZL Z RX = ------------ • -------------------------------------------------G 42L Z T + 500 ( Z L + 2R F ) ZRX is connected from VRX to RSN. ZT is defined above, and G42L is the desired receive gain. 2500 R DC1 + R DC2 = --------------I LOOP RDC1, RDC2, and CDC form the network connected to the RDC pin. ILOOP is the desired loop current in the constant-current region. 3000 R DCR1 + R DCR2 = ---------------------Iringlim RDCR1, RDCR2, and CDCR form the network connected to the RDCR pin. See Applications Circuit for these components. R DC1 + R DC2 C DC = 19 ms • --------------------------------R DC1 R DC2 C DCR R DCR1 + R DCR2 = ---------------------------------------- • 150 µs R DCR1 R DCR2 R D = R LTH • 12.67 for high battery state CDCR sets the ringing time constant, which can be between 15 µs and 150 µs. RD is the resistor connected from the RD pin to GND and RLTH is the loop-resistance threshold between on-hook and off-hook detection. RD should be greater than 56 kΩ to guarantee detection will occur in the Standby state. Choose the value of RD for high battery state; then use the equation for RLTH to find where the threshold is for low battery. Loop-Threshold Detect Equations RD - for high battery R LTH = -----------12.67 This is the same equation as for RD in the preceding equation, except solved for RLTH. RD R LTH = ------------ for low battery 11.37 For low battery, the detect threshold is slightly higher, which will avoid oscillating between states. V BAT1 – 10 R LTH = ----------------------------- • R D – 400 – 2R F 915 RLTH standby < RLTH active VBAT1 < RLTH active VBAT2, which will guarantee no unstable states under all operating conditions. This equation will show at what resistance the standby threshold will be; it is actually a current threshold rather than a resistance threshold, which is shown by the Vbat dependency. 12 Zarlink Semiconductor Inc. Le79R70 Data Sheet DC FEED CHARACTERISTICS 50 5) VAPPH High Battery Anti-Sat 4) VASH VAB (Volts) 40 30 1) Constant-Current Region 20 3) VAPPL Low Battery Anti-Sat 2) VASL 10 0 30 IL (mA) Figure 1. Typical VAB vs. IL DC Feed Characteristics R DC = R DC1 + R DC2 = 20 kΩ + 80 kΩ = 100 kΩ ( V BAT1 = – 67 V , V BAT2 = – 24 V ) Notes: 1. Constant-current region: 2500 V AB = I L R L = ------------- R L ; where R L = R L + 2R F RDC 2. Low battery 1000 • ( 104 • 10 + R SGL ) V ASL = ------------------------------------------------------------------- ; where RSGL = resistor to GND, B2EN = logic Low. 3 6720 • 10 + ( 80 • R SGL ) 3 3 Anti-sat region: V ASL 1000 • ( R SGL – 56 • 10 ) = --------------------------------------------------------------- ; where RSGL = resistor to VCC, B2EN = logic Low. 3 6720 • 10 + ( 80 • R SGL ) RSGL to VCC must be greater than 100 kΩ. 3. V APPL = 4.17 + V ASL V APPL I LOOPL = -----------------------------------------------------------------------------( R DC1 + R DC2 ) -------------------------------------- + 2R F + R LOOP 600 4. High battery V ASH = V ASHH + V ASL 3 Anti-sat region: V ASHH 1000 • ( 70 • 10 + R SGH ) = ----------------------------------------------------------------------- ; where RSGH = resistor to GND, B2EN = logic High. 3 1934 • 10 + ( 31.75 • R SGH ) V ASHH 1000 • ( R SGH + 2.75 • 10 ) = ----------------------------------------------------------------------- ; where RSGH = resistor to VCC, B2EN = logic High. 3 1934 • 10 + ( 31.75 • R SGH ) 3 RSGH to VCC must be greater than 100 kΩ. 5. V APPH = 4.17 + V ASH V APPH I LOOPH = -----------------------------------------------------------------------------( R DC1 + R DC2 ) -------------------------------------- + 2R F + R LOOP 600 13 Zarlink Semiconductor Inc. Le79R70 Data Sheet RING-TRIP COMPONENTS R RT2 = 12 kΩ C RT = 1.5 µF V BAT1 R RT1 = 320 • CF • ------------------------------------------------------------------------------------------------------------------------------------------ • ( R LRT + 150 + 2R F ) V BAT1 – 5 – ( 24 µA • 320 • CF • ( R LRT + 150 + 2R F ) ) where RLRT = Loop-detection threshold resistance for ring trip and CF = Crest factor of ringing signal (≈ 1.25) RSLEW, CSLEW Ring waveform rise time ≈ 0.214 • (RSLEW • CSLEW) ≈ tr. For a 1.25 crest factor @ 20 Hz, tr ≈ 10 mS. ∴ (RSLEW = 150 kΩ, CSLEW = 0.33 µF.) CSLEW should be changed if a different crest factor is desired. Ringing Reference (Input to RSLEW) 0 B(RING) A(TIP) Battery This is the best time for switching between RINGING and other states for minimizing detect switching transients. Figure 2. Ringing Waveforms A a RL IL RSN SLIC RDC2 b RDC1 B RDC Feed current programmed by RDC1 and RDC2 Figure 3. Feed Programming 14 Zarlink Semiconductor Inc. CDC Le79R70 Data Sheet TEST CIRCUITS A(TIP) RL 2 VTX SLIC VAB VL AGND RL RT RRX 2 B(RING) RSN IL2-4 = 20 log (VTX / VAB) A. Two- to Four-Wire Insertion Loss A(TIP) VTX SLIC VAB RL AGND RT RRX B(RING) RSN VRX IL4-2 = 20 log (VAB / VRX) BRS = 20 log (VTX / VRX) B. Four- to Two-Wire Insertion Loss and Four- to Four-Wire Balance Return Signal 1 ωC A(TIP) << RL S1 RL C SLIC 2 VL VL VTX VAB AGND RL RT S2 2 B(RING) RSN S2 Open, S1 Closed L-T Long. Bal. = 20 log (VAB / VL) S2 Closed, S1 Open 4-L Long. Sig. Gen. = 20 log (VL / VRX) L-4 Long. Bal. = 20 log (VTX / VL) C. Longitudinal Balance 15 Zarlink Semiconductor Inc. RRX VRX Le79R70 Data Sheet TEST CIRCUITS (continued) ZD A(TIP) R VTX RT1 SLIC VS VM R AGND ZIN CT1 RT2 B(RING) RSN RRX ZD: The desired impedance; e.g., the characteristic impedance of the line Return loss = –20 log (2 VM / VS) D. Two-Wire Return Loss Test Circuit VCC 6.2 kΩ A(TIP) A(TIP) DET B(RING) 15 pF RL = 600 Ω RG B(RING) E1 E. Loop-Detector Switching L1 F. Ground-Key Switching 200 Ω C1 RF1 50 Ω A RF2 50 Ω 200 Ω HF GEN 1.5 Vrms 80% Amplitude Modulated 100 kHz to 30 MHz CAX 33 nF B 50 Ω C2 L2 CBX 33 nF VTX SLIC under test G. RFI Test Circuit 16 Zarlink Semiconductor Inc. Le79R70 Data Sheet TEST CIRCUITS (continued) +5 V –5 V CRT 1.5 µF RRT2 12 kΩ RRT1 430 kΩ CAX 2.2 nF RTRIP2 A(TIP) HPA A(TIP) CHP RTRIP1 VCC VNEG RD RSGH RSGL VTX 18 nF HPB B(RING) B(RING) RD 75 kΩ VRX 2.0 kΩ RYE BAT1 VBAT1 D2 0.1 µF VBAT2 BAT2 0.1 µF BGND RDC2 20 kΩ RDCR RDCR RYOUT2 D1 RRX 300 kΩ RSN RDC RYOUT1 RSGL open VTX RT 300 kΩ RDC1 80 kΩ CBX 2.2 nF RSGH open B2EN C1 C2 C3 D1 D2 E1 DET CDC 1.2 µF RSLEW 100 kΩ RINGIN AGND/ DGND See Note. CSLEW 0.33 µF BATTERY GROUND ANALOG GROUND Note: The input should be 50% duty cycle CMOS-compatible input. DIGITAL GROUND H. Le79R70 Test Circuit 17 Zarlink Semiconductor Inc. Le79R70 Data Sheet APPLICATION CIRCUIT +5 V –5 V CRT 1.5 µF RRT2 12 kΩ K1 Bat1 RTRIP2 A(TIP) K1 G TISP A 61089 A RING RFB = 50 Ω RTRIP1 CAX = 2.2 nF RFA = 50 Ω TIP RRT1 515 kΩ K2 CHP 18 nF K2 VCC VNEG RD RSGH RSGL VTX HPA HPB RSN RD 66 kΩ RSGH open RT1 125 kΩ CBX = 2.2 nF RT2 CT RDC2 50 kΩ RDC RYOUT1 CDC 820 nF CDCR RDCR1 RDCR 15 kΩ RYOUT2 RYE D1 BAT1 VBAT1 D2 0.1 µF BAT2 VBAT2 0.1 µF B2EN C1 C2 C3 D1 D2 E1 RINGIN AGND/ DGND Assumptions: 1. 1.25 CF 2. 25 mA ILOOP 3. 100 mA Ringing Current Limit VRX RDCR2 15 kΩ 10 nF RSLEW 150 kΩ DET BGND VTX RRX 125 kΩ 250 kΩ RDC1 50 kΩ B(RING) RSGL open See Note. CSLEW 0.33 µF 4. 5.2 kΩ High Battery Loop Threshold 5. 925 Ω Ringing Loop Threshold 6. 600 Ω Two-wire Impedance, 600 Ω ZL Note: The input should be 50% duty cycle CMOS-compatible input. I. Application Circuit 18 Zarlink Semiconductor Inc. 7. G42L = 1 8. –67 V Vbat1, –24 V Vbat2 BATTERY GROUND ANALOG GROUND DIGITAL GROUND Le79R70 Data Sheet PHYSICAL DIMENSIONS 32-Pin PLCC NOTES: 32-Pin PLCC JEDEC # MS-016 Min Nom Symbol A 0.125 -A1 0.075 0.090 D 0.485 0.490 D1 0.447 0.450 D2 0.205 REF E 0.585 0.590 E1 0.547 0.550 E2 0.255 REF Ԧ 0 deg -- 1 Dimensioning and tolerancing conform to ASME Y14,5M-1994. 2 To be measured at seating plan - C - contact point. 3 Dimensions “D1” and “E1” do not include mold protrusion. Allowable mold protrusion is 0.010 inch per side. Dimensions “D” and “E” include mold mismatch and determined at the parting line; that is “D1” and “E1” are measured at the extreme material condition at the upper or lower parting line. 0.595 0.553 4 Exact shape of this feature is optional. 10 deg 5 Details of pin 1 identifier are optional but must be located within the zone indicated. 6 Sum of DAM bar protrusions to be 0.007 max per lead. 7 Controlling dimension : Inch. 8 Reference document : JEDEC MS-016 Max 0.140 0.095 0.495 0.453 32-Pin PLCC Note: Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the device. Markings will vary with the mold tool used in manufacturing. 19 Zarlink Semiconductor Inc. Le79R70 Data Sheet 32-Pin QFN Symbol A A2 b D D2 E E2 e L N A1 A3 aaa bbb ccc Min 0.80 0.18 5.70 5.70 0.43 0.00 32 LEAD QFN Nom 0.90 0.57 REF 0.23 8.00 BSC 5.80 8.00 BSC 5.80 0.80 BSC 0.53 32 0.02 0.20 REF 0.20 0.10 0.10 Max 1.00 0.28 5.90 5.90 0.63 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. is in degrees. 3. N is the total number of terminals. 4. The Terminal #1 identifier and terminal numbering convention shall conform to JEP 95-1 and SSP-012. Details of the Terminal #1 identifier are optional, but must be located within the zone indicated. The Terminal #1 identifier may be either a mold or marked feature. 5. Coplanarity applies to the exposed pad as well as the terminals. 6. Reference Document: JEDEC MO-220. 7. Lead width deviates from the JEDEC MO-220 standard. 0.05 32-Pin QFN Note: Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the device. Markings will vary with the mold tool used in manufacturing. 20 Zarlink Semiconductor Inc. Le79R70 Data Sheet REVISION HISTORY Revision A to B • Minor changes were made to the data sheet style and format to conform to Zarlink standards. Revision B to C • The 28-pin SOIC information and package was added to the Ordering Information and the Connection Diagrams sections. • The physical dimensions (PL032 and SOW28) were added to the Physical Dimensions section. • Updated the Pin Description table to correct inconsistencies. Revision C to D • Changed Ring-Trip Components equation from: V BAT1 R RT1 = 300 • CF • ------------------------------------------------------------------------------------------------------------------------------------------ • ( R LRT + 150 + 2R F ) Vbat – 3.5 – ( 15 µA • 300 • CF • ( R LRT + 150 + 2R F ) ) To: V BAT1 R RT1 = 320 • CF • ------------------------------------------------------------------------------------------------------------------------------------- • ( R LRT + 150 + 2R F ) Vbat – 5 – ( 24 µA • 320 • CF • ( R LRT + 150 + 2R F ) ) Revision D to E • In “Ordering Information” section, added description for wafer foundry facility optional character. Revision E to F • Updated device name from “Am79R70” to “Le79R70” throughout document. • Added QFN package to “Connection Diagram,” “Absolute Maximum Ratings,” and “Physical Dimensions.” • Removed reference to PLCC package type in “General Description.” • Ordering Information: Temperature statement updated to standard. • Absolute Maximum Ratings: Notes updated to standard. • Operating Ranges: Temperature statement updated to standard. Revision F to G1 • • Added green package OPNs to Ordering Information, on page 1 Added Package Assembly, on page 6 Revision G1 to H1 • • Added "Packing" column and Note 5 to Ordering Information, on page 1 Updated 32QFN drawing in Physical Dimensions, on page 19 Revision H1 to I1 • • • Added green package OPNs and removed OPN for SOIC package in Ordering Information, on page 1 Removed SOIC drawing in Physical Dimensions, on page 19 Added note to Physical Dimensions, on page 19 Revision I1 to J1 • • Removed the following OPNs from Ordering Information, on page 1: Le79R70JC, Le79R70-1JC, Le79R70QC, Le79R701QC. Changed IL Loop-Current Accuracy from 0.9 to 0.871 in Electrical Characteristics. Revision J1 to J2 • • Enhanced format of package drawings in Physical Dimensions, on page 19 Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007 21 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. TECHNICAL DOCUMENTATION - NOT FOR RESALE