CEZ3R02 N-Channel Enhancement Mode Field Effect Transistor PRELIMINARY FEATURES 30V, 135A, R DS(ON) = 2.3mΩ @VGS = 10V. RDS(ON) = 3.8mΩ @VGS = 4.5V. D D D D 8 7 6 5 1 S 2 S 3 S 4 G Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. D D D D Surface mount Package. G S S S PR-PACK (5*6) ABSOLUTE MAXIMUM RATINGS Parameter TA = 25 C unless otherwise noted Symbol Limit Drain-Source Voltage VDS 30 Units V Gate-Source Voltage VGS ± 20 V Drain Current-Continuous ID @TA 36 A Drain Current-Continuous 135 A Drain Current-Pulsed a ID @TC IDM @TA Drain Current-Pulsed a IDM @TC 144 540 A A Maximum Power Dissipation PD 83 W Single Pulsed Avalanche Energy e EAS IAS 800 40 mJ A TJ,Tstg -55 to 150 C Symbol Limit Units RθJC 1.5 C/W RθJA 20 C/W Single Pulsed Avalanche Current e Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient b This is preliminary information on a new product in development now . Details are subject to change without notice . 1 Rev 1. 2011.Aug http://www.cetsemi.com CEZ3R02 Electrical Characteristics Parameter TA = 25 C unless otherwise noted Symbol Test Condition Min Drain-Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA 30 Zero Gate Voltage Drain Current IDSS Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse Typ Max Units VDS = 30V, VGS = 0V 1 µA IGSSF VGS = 20V, VDS = 0V 100 nA IGSSR VGS = -20V, VDS = 0V -100 nA Off Characteristics V On Characteristics c Gate Threshold Voltage Static Drain-Source On-Resistance Gate input resistance VGS(th) RDS(on) Rg VGS = VDS, ID = 250µA 3 V VGS = 10V, ID =30A 1 1.9 2.3 mΩ VGS = 4.5V, ID =20A 3.0 3.8 mΩ f=1MHz,open Drain 2.1 Ω 4100 pF 980 pF 600 pF Dynamic Characteristics d Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss VDS = 15V, VGS = 0V, f = 1.0 MHz Switching Characteristics d Turn-On Delay Time td(on) Turn-On Rise Time tr Turn-Off Delay Time td(off) VDD = 15V, ID = 15A, VGS = 10V, RGEN = 1Ω 44 88 ns 38 76 ns 63 126 ns Turn-Off Fall Time tf 30 60 ns Total Gate Charge Qg 51 66 nC Gate-Source Charge Qgs Gate-Drain Charge Qgd VDS = 15V, ID = 15A, VGS = 4.5V 14 nC 22 nC Drain-Source Diode Characteristics and Maximun Ratings Drain-Source Diode Forward Current b IS Drain-Source Diode Forward Voltage c VSD VGS = 0V, IS = 20A Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Surface Mounted on FR4 Board, t < 10 sec. c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. d.Guaranteed by design, not subject to production testing. e.L = 1mH, IAS =40A, VDD = 24V, RG = 25Ω, Starting TJ = 25 C 2 80 A 1 V CEZ3R02 200 VGS=10,8,6V 80 ID, Drain Current (A) ID, Drain Current (A) 100 60 40 20 0 VGS=3V 0 0.2 0.4 0.6 40 0 1 -55 C 2 4 5 6 Figure 1. Output Characteristics Figure 2. Transfer Characteristics RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) Ciss 2400 1600 Coss 800 Crss 0 5 10 15 20 25 2.2 1.9 ID=30A VGS=10V 1.6 1.3 1.0 0.7 0.4 -100 -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) TJ, Junction Temperature( C) Figure 3. Capacitance Figure 4. On-Resistance Variation with Temperature VDS=VGS ID=250µA 1.1 1.0 0.9 0.8 0.7 0.6 -50 TJ=125 C VGS, Gate-to-Source Voltage (V) IS, Source-drain current (A) C, Capacitance (pF) VTH, Normalized Gate-Source Threshold Voltage 80 0 3000 1.2 120 VDS, Drain-to-Source Voltage (V) 4000 1.3 160 0.8 4800 0 25 C -25 0 25 50 75 100 125 150 VGS=0V 10 1 10 0 10 -1 0.4 0.6 0.8 1.0 1.2 1.4 TJ, Junction Temperature( C) VSD, Body Diode Forward Voltage (V) Figure 5. Gate Threshold Variation with Temperature Figure 6. Body Diode Forward Voltage Variation with Source Current 3 5 VDS=15V ID=10A 4 3 2 1 0 0 10 3 10 2 10 1 10 0 10 -1 RDS(ON)Limit ID, Drain Current (A) VGS, Gate to Source Voltage (V) CEZ3R02 12 24 36 48 60 10ms 100ms 1s DC TA=25 C TJ=150 C Single Pulse 10 -2 10 -1 10 0 10 1 10 Qg, Total Gate Charge (nC) VDS, Drain-Source Voltage (V) Figure 7. Gate Charge Figure 8. Maximum Safe Operating Area VDD t on V IN RL D VGS RGEN toff tr td(on) td(off) tf 90% 90% VOUT VOUT 10% INVERTED 10% G 90% S VIN 50% 50% 10% PULSE WIDTH Figure 10. Switching Waveforms Figure 9. Switching Test Circuit r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 10 0.2 -1 0.1 0.05 10 PDM 0.02 0.01 -2 t1 Single Pulse 10 -3 10 -4 t2 1. RθJA (t)=r (t) * RθJA 2. RθJA=See Datasheet 3. TJM-TA = P* RθJA (t) 4. Duty Cycle, D=t1/t2 10 -3 10 -2 10 -1 10 0 Square Wave Pulse Duration (sec) Figure 11. Normalized Thermal Transient Impedance Curve 4 10 1 10 2 2