128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM SYNCHRONOUS DRAM MODULE MT9LSDT1672A(I) – 128MB MT18LSDT3272A(I) – 256MB For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/modules Features • • • • • • • • • • • • • • • Figure 1: 168-Pin DIMM (MO–161) PC100- and PC133-compliant 168-pin, dual in-line memory module (DIMM) Unbuffered, ECC-optimized pinout 128MB (16 Meg x 72) and 256MB (32 Meg x 72) Single +3.3V power supply Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal SDRAM banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto Precharge, includes Concurrent Auto Precharge, and Auto Refresh Modes Self Refresh Mode 64ms, 4,096-cycle refresh LVTTL-compatible inputs and outputs Serial Presence-Detect (SPD) Gold edge contacts Table 1: Low Profile 1.125in./28.58mm Options 133 MHz 133 MHz 100 MHz 5.4ns – 9ns – 5.4ns 7.5ns SETUP TIME HOLD TIME 1.5 1.5 2ns 0.8 0.8 1ns NOTE: Table 2: Marking • Self-Refresh Standard None Low Power L1 • Package 168-pin DIMM (Standard) G Y1 168-pin DIMM (Lead-free) • Frequency/CAS Latency 7.5ns (133 MHz)/CL = 2 -13E 7.5ns (133 MHz)/CL = 3 -133 10ns (100 MHz)/CL = 2 -10E • PCB Standard (1.375in./34.93mm) See note on page 2 Low-Profile (1.125in./28.58mm) See note on page 2 Timing Parameters ACCESS TIME MODULE CLOCK MARKING FREQUENCY CL = 2 CL = 3 -13E -133 -10E Standard 1.375in./34.93mm 1. Consult Micron for product availability. Address Table Refresh Count Device Banks Device Configuration Row Addressing Column Addressing Module Ranks 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 128MB 256MB 4K 4 (BA0, BA1) 128Mb (16 Meg x 8) 4K (A0–A11) 1K (A0–A9) 1 (S0, S2) 4K 4 (BA0, BA1) 128Mb (16 Meg x 8) 4K (A0–A11) 1K (A0–A9) 2 (S0, S2; S1, S3) 1 ©2004 Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Table 3: Part Numbers PART NUMBER MT9LSDT1672AG-13E_ MT9LSDT1672AY-13E_ MT9LSDT1672AG-133_ MT9LSDT1672AY-133_ MT9LSDT1672AG-10E_ MT9LSDT1672AY-10E_ MT18LSDT3272AG-13E_ MT18LSDT3272AY-13E_ MT18LSDT3272(L)AG-133_ MT18LSDT3272(L)AY-133_ MT18LSDT3272AG-10E_ MT18LSDT3272AY-10E_ MODULE DENSITY CONFIGURATION SYSTEM BUS SPEED 128MB 128MB 128MB 128MB 128MB 128MB 256MB 256MB 256MB 256MB 256MB 256MB 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 133 MHz 133 MHz 133 MHz 133 MHz 100 MHz 100 MHz 133 MHz 133 MHz 133 MHz 133 MHz 100 MHz 100 MHz NOTE: Designators for component and PCB revision are the last two characters of each part number Consult factory for current revision codes. Example: MT9LSDT1672G-133B1. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Table 4: Pin Assignment (168-Pin DIMM Front) Table 5: Pin Assignment (168-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 CB1 VSS NC NC VDD WE# DQMB0 DQMB1 S0# NC VSS A0 A2 A4 A6 A8 A10 BA1 VDD VDD CK0 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 VSS NC S2# DQMB2 DQMB3 NC VDD NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC CKE1 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC NC SDA SCL VDD VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 106 CB5 127 VSS 148 107 VSS 128 CKE0 149 108 NC 129 S3# 150 109 NC 130 DQMB6 151 110 VDD 131 DQMB7 152 111 CAS# 132 NC 153 154 112 DQMB4 133 VDD 113 DQMB5 134 NC 155 114 S1# 135 NC 156 115 RAS# 136 CB6 157 116 VSS 137 CB7 158 117 A1 138 VSS 159 118 A3 139 DQ48 160 119 A5 140 DQ49 161 120 A7 141 DQ50 162 121 A9 142 DQ51 163 122 BA0 143 VDD 164 123 A11 144 DQ52 165 124 VDD 145 NC 166 125 CK1 146 NC 167 126 NC 147 NC 168 VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VDD Figure 2: 168-Pin DIMM Pin Locations Front View U10 U2 U1 U3 U4 U5 U6 U7 U8 PIN 41 PIN 1 U9 PIN 84 Back View (Populated only for 256MB module) U11 U12 U13 U14 Indicates a VDD pin U17 U18 U19 PIN 85 PIN 125 PIN 168 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN U16 U15 Indicates a VSS pin 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Table 6: Pin Descriptions Pin numbers may not correlate with symbols. Refer to the Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION 27, 111, 115 Input 42, 79, 125, 163 RAS#, CAS#, WE# CK0–CK3 Input 63, 128 CKE0, CKE1 Input 30, 45,114, 129 S0#–S3# Input 28, 29, 46, 47, 112, 113, 130, 131 DQMB0–DQMB7 Input 39, 122 BA0, BA1 Input 33–38, 117–121, 123 A0–A11 Input 83 SCL Input 165–167 SA0–SA2 Input 21, 22, 52, 53, 105, 106, 136, 137 2–5, 7–11, 13–17, 19, 20, 55–58, 60, 65–67, 69–72, 74– 77, 86–89, 91–95, 97–101, 103, 104, 139–142, 144, 149–151, 153–156,158–161 82 CB0–CB7 Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Clock: CK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all device banks idle) or CLOCK SUSPEND OPERATION (burst access in progress). CKE is synchronous except after the device enters powerdown and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CK, are disabled during power-down and self refresh modes, providing low standby power. Chip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Input/Output Mask: DQMB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (twoclock latency) when DQMB is sampled HIGH during a READ cycle. Bank Address: BA0 and BA1 define to which device bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto prcharge bit (A10) for READ/WRITE commands, to select one location out of the memory arrary in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Check Bits. ECC, 1-bit error detection and correction. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN DQ0–DQ63 SDA Input/ Output Input/ Data I/O: Data bus. Output Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to Output transfer addresses and data into and out of the presencedetect portion of the module. 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Table 6: Pin Descriptions Pin numbers may not correlate with symbols. Refer to the Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL 6, 18, 26, 40, 41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 24, 25, 31, 44, 48, 50, 51 61, 62, 80, 81, 108, 109, 126, 132, 134, 135, 145,146, 147 VDD Supply Power Supply: +3.3V ±0.3V. VSS Supply Ground. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN NC TYPE – DESCRIPTION Not Connected: These pins are not connected on these module. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Figure 3: Functional Block Diagram – Single Rank S0# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB4 DQM CS# DQ U1 DQ DQ DQ DQ DQ DQ DQ DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQM CS# DQ U2 DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQM CS# DQ U3 DQ DQ DQ DQ DQ DQ DQM CS# DQ U4 DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM CS# DQ U5 DQ DQ DQ DQ DQ DQ DQ S2# DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB6 DQM CS# DQ U7 DQ DQ DQ DQ DQ DQ DQ DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMB7 DQM CS# DQ U9 DQ DQ DQ DQ DQ DQ DQ RAS# RAS#: SDRAMs VDD CAS# CAS#: SDRAMs 2.2µF CKE0 CKE0: SDRAMs WE# WE#: SDRAMs A0-A11 A0-A11: SDRAMs BA0 BA0: SDRAMs BA1 BA1: SDRAMs DQM CS# DQ U8 DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 SDRAMs CK0 U1 U2 U3 U4 U5 CK2 U6 U7 U8 U9 2.2µF VSS SDRAMs SPD U10 A0 A1 A2 SCL WP SA0 SA1 SA2 Note: 1. All resistor values are 10Ω unless otherwise specified. 2. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at www.micron.com/ SDA 3.3pF CK1, CK3 10pF Standard modules use the following SDRAM devices: MT48LC16M8A2TG Lead-free modules use the following SDRAM devices: MT48LC16M8A2TG support/numbering.html. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN DQM CS# DQ U6 DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Figure 4: Functional Block Diagram – Dual Rank S0# S1# DQMB0 DQMB4 DQM CS# DQ U1 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U19 DQ DQ DQ DQ DQ DQ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS# DQ U3 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U17 DQ DQ DQ DQ DQ DQ CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQM CS# DQ U5 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U15 DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB1 DQM CS# DQ U2 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U18 DQ DQ DQ DQ DQ DQ DQM CS# DQ U4 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U16 DQ DQ DQ DQ DQ DQ DQM CS# DQ U6 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U14 DQ DQ DQ DQ DQ DQ DQM CS# DQ U8 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U12 DQ DQ DQ DQ DQ DQ DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 S2# S3# DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB6 DQM CS# DQ U7 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U13 DQ DQ DQ DQ DQ DQ DQM CS# DQ U9 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U11 DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 VDD VDD 10K CKE1 CKE0 CKE0: SDRAMs CAS# CAS#: SDRAMs RAS# RAS#: SDRAMs WE# WE#: SDRAMs A0-A11 VSS SDRAMs SPD U10 A0 A1 A2 SCL WP BA0: SDRAMs BA1 BA1: SDRAMs CK1 U15 U16 U17 U18 U19 SDA A0-A11: SDRAMs BA0 CK0 U1 U2 U3 U4 U5 SDRAMs CKE1: SDRAMs SA0 SA1 SA2 CK2 3.3pF CK3 3.3pF U6 U7 U8 U9 U11 U12 U13 U14 Standard modules use the following SDRAM devices: MT48LC16M8A2TG NOTE: 1. All resistor values are 10Ω unless othersise specified. 2. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at www.micron.com/ Lead-free modules use the following SDRAM devices: MT48LC16M8A2TG support/numbering.html. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM General Description 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. The MT9LSDT1672 and MT18LSDT3272A modules are high-speed CMOS, dynamic random-access, 128MB and 256MB DIMMs organized in a x72 (ECC) configuration. SDRAM modules use internally configured quad-bank SDRAM devices with a synchronous interface (all signals are registered on the positive edge of the clock signals). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select the device bank, A0–A11 select the device row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. SDRAM modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst sequence. SDRAM modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one device bank while accessing one of the other three device banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM modules are designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to syn-chronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal device banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 128Mb SDRAM component data sheet. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All device banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. Mode Register Definition The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 5, Mode Register Definition Diagram, on page 9. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write Serial Presence-Detect Operation These modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 7, Burst Definition Table, on page 10. burst mode, and M10 and M11 are reserved for future use. Address A12 (M12) is undefined but should be driven LOW during loading of the mode register. The mode register must be loaded when all device banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Figure 5: Mode Register Definition Diagram A11 A10 A9 A8 A6 A7 A5 A4 A3 A1 A2 Address Bus A0 Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 5, Mode Register Definition Diagram, on page 9. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in Table 7, Burst Definition Table, on page 10. The block is uniquely selected by A1–A9 when the burst length is set to two; by A2–A9 when the burst length is set to four; and by A3–A9 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached, as shown in Table 7, Burst Definition Table, on page 10. 11 10 9 Reserved* WB 6 7 5 4 CAS Latency 3 1 2 BT 0 Mode Register (Mx) Burst Length *Should program M11, M10 = “0, 0” to ensure compatibility with future devices. Burst Length M2 M1 M0 9 M3 = 1 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Burst Type 0 Sequential 1 Interleaved M6 M5 M4 Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. M3 = 0 0 M3 Burst Type 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 8 Op Mode CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Table 7: BURST LENGTH Burst Definition Table STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL A0 0 1 A1 A0 0 0 4 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 8 1 0 0 1 0 1 1 1 0 1 1 1 Full Page n= A0-A9 (y) (location 0-y) 2 Figure 6: CAS Latency Diagram T0 T1 T2 T3 READ NOP NOP CLK COMMAND TYPE = INTERLEAVED tLZ tOH DOUT DQ tAC 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2 Cn+3, Cn+4... ...Cn-1, Cn... 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 CAS Latency = 2 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CAS Latency = 3 DON’T CARE UNDEFINED CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ will start driving after T1 and the data will be valid by T2, as shown in Figure 6, CAS Latency Diagram. Table 8, CAS Latency Table, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Not Supported NOTE: 1. For full-page accesses: y = 1,024 2. For a burst length of two, A1–A9 select the block of two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2–A9 select the block of four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3–A9 select the block of eight burst; A0–A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0–A9 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0–A9 select the unique column to be accessed, and Mode Register bit M3 is ignored.For a full-page burst, the full row is selected and A0–A8 select the starting column. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Table 8: Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. ALLOWABLE OPERATING CLOCK FREQUENCY (MHz) Write Burst Mode When M9 = 0, the burst length programmed via M0M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN CAS Latency Table 11 SPEED CAS LATENCY = 2 CAS LATENCY = 3 -13E -133 -10E ≤ 133 ≤ 100 ≤ 100 ≤ 143 ≤ 133 N/A Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Commands The Truth Table, below, provides a quick reference of available commands. This is followed by written description of each command. For a more detailed Table 9: description of commands and operations, refer to the 128Mb SDRAM component data sheet. SDRAM Commands and DQMB Operation Truth Table CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) CS# RAS# CAS# WE# DQMB ADDR DQ NOTES X X X 1 X Valid 2 2 COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) H L L X H L X H H X H H X X X READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z L L H H L L H L L/H L/H X X Bank/ Row Bank/Col Bank/Col L L L H L L H H L L L H X X X X Code X Active X X 3 4, 5 L – – L – – L – – L – – X L H Op-code – – X Active High-Z 6 7 7 NOTE: 1. A0–A11 provide row address; BA0–BA1 determine which device bank is made active. 2. A0–A9 provide column address; A10 HIGH enables the auto-precharge feature (nonpersistent), while A10 LOW disables the auto-precharge feature; BA0–BA1 determine which device bank is being read from or written to. 3. A10 LOW: BA0–BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and BA0, BA1 are “Don’t Care.” 4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 6. A0–A11 define the op-code written to the mode register. 7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD, VDDQ Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . -1V to +4.6V Voltage on Inputs NC or I/O Pins Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +4.6V Operating Temperature TOPR (Commercial - ambient) . . . . .. 0°C to +65°C TOPR (Industrial - ambient) . . . . . . .-40°C to +85°C Storage Temperature (plastic) . . . . . . -55°C to +150°C Table 10: DC Electrical Characteristics and Operating Conditions – 128MB Notes: 1, 5, 6; notes appear on page 18; VDD, VDDQ = +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT: DQ pins are disabled; 0V ≤ VOUT ≤ VDDQ OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) SYMBOL MIN MAX UNITS NOTES VDD, VDDQ VIH VIL 3 2 -0.3 3.6 VDD + 0.3 0.8 V V V 22 22 -45 45 25 20 5 5 µA 33 IOZ -25 -20 -5 -5 µA 33 VOH VOL 2.4 – – 0.4 V V Command and Address Inputs, CKE0 CK0, S0# CK2, S2# DQMB DQ II Table 11: DC Electrical Characteristics and Operating Conditions – 256MB Notes: 1, 5, 6; notes appear on page 18; VDD, VDDQ = +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT: DQ pins are disabled; 0V ≤ VOUT ≤ VDDQ OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN Command and Address Inputs CKE0, CKE1 CK0, CK1, S0#, S1# CK2, CK3, S2#, S3# DQMB DQ 13 SYMBOL MIN MAX UNITS NOTES VDD, VDDQ VIH VIL 3 2 -0.3 3.6 VDD + 0.3 0.8 V V V 22 22 -90 90 45 25 20 5 10 µA 33 IOZ -45 -25 -20 -5 -10 µA 33 VOH VOL 2.4 – – 0.4 II V V Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Table 12: IDD Specifications and Conditions – 128MB Notes: 1, 5, 6, 11, 13; notes appear on page 18; VDD, VDDQ = +3.3V ±0.3V; SDRAM component values only MAX PARAMETER/CONDITION SYMBOL IDD1 -13E -133 -10E UNITS NOTES 1,125 1,035 855 mA 3, 18, 19, 30 OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; t RC = tRC (MIN) STANDBY CURRENT: Power-Down Mode; All device banks idle; CKE = LOW STANDBY CURRENT: Active Mode;CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device banks active tRFC = tRFC (MIN) AUTO REFRESH CURRENT IDD4 IDD5 CKE = HIGH; CS# = HIGH IDD6 27 27 IDD7 18 9 18 9 SELF REFRESH CURRENT: CKE ≤ 0.2V t RFC = 15.625µs Standard Low Power IDD2 18 18 18 mA 30 IDD3 405 405 315 mA 3, 12, 19, 30 1,350 1,260 1,080 mA 3, 18, 19, 30 2,070 1,890 1,710 mA 3, 12 27 mA 18, 19, 30, 31 18 9 mA mA 4 4 Table 13: IDD Specifications and Conditions – 256MB Notes: 1, 5, 6, 11, 13; notes appear on page 18; VDD, VDDQ = +3.3V ±0.3V; SDRAM component values only MAX PARAMETER/CONDITION SYMBOL IDD1a -13E -133 IDD4a IDD5b CKE = HIGH; CS# = HIGH IDD6b 54 54 IDD7b 36 27 36 27 SELF REFRESH CURRENT: CKE ≤ 0.2V tRFC = 15.625µs Standard Low Power -10E 1,458 1,368 1,278 OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) STANDBY CURRENT: Power-Down Mode; All device banks idle; CKE = LOW STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device banks active tRFC = tRFC (MIN) AUTO REFRESH CURRENT UNITS NOTES mA 3, 18, 19, 30 IDD2b 36 36 36 mA 30 IDD3a 468 468 378 mA 3, 12, 19, 30 1,503 1,368 1,278 mA 3, 18, 19, 30 5,940 5,580 4,860 mA 3, 12 54 mA 18, 19, 30, 31 36 27 mA mA 4 4 NOTE: a - Value calculated as one module rank in this condition, and all other module ranks in Power-Down Mode (IDD2). b - Value calculated reflects all module ranks in this condition. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM . 14: Capacitance – 128MB Table Note 2; notes appear on page 18 PARAMETER Input Capacitance: Address and Command Input Capacitance: CK0 Input Capacitance: CK2 Input Capacitance: S0# Input Capacitance: S2# Input Capacitance: CKE Input Capacitance: DQMB0, 2–4, 6, 7 Input Capacitance: DQMB1 Input/Output Capacitance: DQ, CB SYMBOL MIN MAX UNITS CI1 CI2 CI2 CI3 CI3 CI4 CI5 CI6 CIO 22.5 12.5 13.3 12.5 10 22.5 2.5 5 4 34.2 17.5 17.3 19 15.2 34.2 3.8 7.6 6 pF pF pF pF pF pF pF pF pF SYMBOL MIN MAX UNITS CI1 CI2 CI2 CI3 CI3 CI4 CI5 CI6 CIO 45 12.5 13.3 12.5 10 22.5 5 7.5 8 68.4 17.5 17.3 19 15.2 34.2 7.6 11.4 12 pF pF pF pF pF pF pF pF pF . Table 15: Capacitance – 256MB Note 2; notes appear on page 18 PARAMETER Input Capacitance: Address and Command Input Capacitance: CK0 Input Capacitance: CK2 Input Capacitance: S0# Input Capacitance: S2# Input Capacitance: CKE Input Capacitance: DQMB0, 2–4, 6, 7 Input Capacitance: DQMB1 Input/Output Capacitance: DQ, CB 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Table 16: Electrical Characteristics and Recommended AC Operating Conditions Notes: 5, 6, 8, 9, 11, 31; notes appear on page 18 Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters ACCHARACTERISTICS -13E PARAMETER SYMBOL Access timefrom CLK (pos.edge) CL= 3 t CL= 2 t MIN -133 MAX MIN -10E MAX UNITS NOTES AC(3) 5.4 MAX 5.4 MIN 6 ns 27 AC(2) 5.4 6 6 ns AH 0.8 0.8 1 ns Address setup time t 1.5 1.5 2 ns CLK high-level width t CH 2.5 2.5 3 ns CLK low-level width tCL 2.5 2.5 3 ns CL= 3 tCK(3) 7 7.5 8 ns 23 CL = 2 t CK(2) 7.5 10 10 ns 23 tCKH 0.8 0.8 1 ns tCKS 1.5 1.5 2 ns CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 0.8 1 ns CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 1.5 2 ns Data-in hold time tDH 0.8 0.8 1 ns Data-in setup time tDS 1.5 1.5 2 ns t Address hold time Clock cycle time CKE holdt ime CKE setup time Data-out high-impedance time AS CL = 3 tHZ(3) 5.4 5.4 6 ns 10 CL = 2 tHZ(2) 5.4 6 6 ns 10 Data-out low-impedance time tLZ 1 1 1 ns Data-out hold time (load) tOH 3 3 3 ns Data-out hold time (noload) tOH 1.8 1.8 1.8 ns 28 ACTIVE to PRECHARGE command tRAS 37 ns 32 tRC 60 ACTIVE to READ or WRITE delay tRCD 15 Refresh period (4,096 rows) tREF AUTOREFRESH period tRFC 66 66 70 ns tRP 15 20 20 ns ACTIVE bank a to ACTIVE bank b command Transition time tRRD 14 15 20 ns tT 0.3 WRITE recovery time t WR Exit SELF REFRESH to ACTIVE command tXSR 1 CLK + 7ns 14 67 ACTIVE to ACTIVE command period PRECHARGE command period N 120,000 44 120,000 66 0.3 1 CLK + 7.5ns 15 75 ns 20 64 1.2 120,000 70 20 64 50 1.2 ns 64 0.3 1 CLK + 7ns 15 80 1.2 ms ns 7 ns 24 ns ns 25 20 . 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Table 17: AC Functional Characteristics Notes: 5, 6, 7, 8, 9, 11, 31; notes appear on page 18 PARAMETER SYMBOL -13E -133 -10E CCD 1 1 1 t CK 17 tCKED 1 1 1 tCK 14 t READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode UNITS NOTES CKE to clock enable or power-down exit setup mode t PED 1 1 1 t 14 DQM to input data delay t DQD 0 0 0 t 17 DQM to data mask during WRITEs t DQM 0 0 0 t 17 DQM to data high-impedance during READs t DQZ 2 2 2 t CK 17 WRITE command to input data delay tDWD 0 0 0 tCK 17 Data-in to ACTIVE command tDAL 4 5 4 tCK 15, 21 Data-in to PRECHARGE command tDPL 2 2 2 tCK 16, 21 Last data-in to burst STOP command tBDL 1 1 1 tCK 17 Last data-in to new READ/WRITE command tCDL 1 1 1 tCK 17 Last data-in to PRECHARGE command tRDL 2 2 2 tCK 16, 21 LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 2 tCK 26 CL = 3 tROH(3) 3 3 3 tCK 17 CL = 2 tROH(2) 2 2 2 tCK 17 Data-out to high-impedance from PRECHARGE command 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 17 CK CK CK Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Notes 1. All voltages referenced to VSS. 2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz; TA = 25°C; pin under test biased at 1.4V. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (0°C ≤ TA ≤ +70°C for Commercial, -40°C ≤ TA ≤ +85°C for Industrial). 6. An initial pause of 100µs is required after powerup, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 10ns for -10E; tCK = 7.5ns for -133 and -13E. 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for -13E; 7.5ns for -133; and 7ns for -10E after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 25. Precharge mode only. 26. JEDEC and PC100 specify three clocks. 27. tAC for -133/-13E at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. For -13E, CL = 2 and tCK = 7.5ns; for -133, CL = 3 and tCK = 7.5ns; for -10E, CL=2 and tCK = 10ns 30. CKE is HIGH during refresh command period t RFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 31. Refer to device data sheet for timing waveforms. 32. The value of tRAS used in -13E speed grade modules is calculated from tRC - tRP. 33. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. Q 50pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet t OH before going High-Z. 11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the ISV crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7, Data Validity, and Figure 8, Definition of Start and Stop). Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Figure 9, Acknowledge Response From Receiver). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure 7: Data Validity Figure 8: Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT STOP BIT Figure 9: Acknowledge Response From Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Table 18: EEPROM Device Select Code The most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER SELECT CODE CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW Memory Area Select Code (two arrays) Protection Register Select Code Table 19: EEPROM Operating Modes MODE RW BIT WC BYTES Current Address Read 1 VIH or VIL 1 Start, Device Select, RW = 1 INITIAL SEQUENCE RandomAddressRead 0 VIH or VIL 1 Start, Device Select, RW= 0, Address 1 VIH or VIL Sequential Read 1 VIH or VIL ≥1 Similar to Current or Random Address Read Byte Write Page Write 0 0 VIL VIL 1 ≤ 16 START, Device Select, RW = 0 START, Device Select, RW = 0 RESTART, Device Select, RW= 1 Figure 10: SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Table 20: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD POWER SUPPLY CURRENT: SYMBOL MIN MAX UNITS VDD VIH VIL VOL ILI ILO ICCS 3 VDD x 0.7 -1 – -10 -10 – 3.6 VDD + 0.5 VDD x 0.3 0.4 10 10 30 V V V V µA µA µA ICC Write ICC Read – – 3 1 mA Table 21: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +3.3V ±0.3V PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL MIN MAX UNITS NOTES tAA 0.2 1.3 200 0.9 µs µs ns ns µs µs µs ns µs µs KHz ns µs µs ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH 300 0 0.6 0.6 tI tLOW 50 1.3 tR 0.3 400 fSCL tSU:DAT tSU:STA t SU:STO tWRC 100 0.6 0.6 10 2 2 3 4 NOTE: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Table 22: Serial Presence-Detect Matrix “1”/”0”: Serial data, “driven to HIGH”/”driven to LOW”; VDD = +3.3V ±0.3V BYTE DESCRIPTION ENTRY (VERSION) 0 1 2 3 4 5 6 7 8 9 Number of Bytes Used by Micron Total Number of SPD Memory Bytes Memory Type Number of Row Addresses Number of Column Addresses Number of Module Ranks Module Data Width Module Data Width (Continued) Module Voltage Interface Levels 10 SDRAM Access From CLK, tAC (CAS Latency = 3) Module Configuration Type Refresh Rate/Type SDRAM Width (Primary SDRAM) Error-checking SDRAM Data Width Minimum Clock Delay from Back-to-Back Random Column Addresses,tCCD Burst Lengths Supported Number of Banks on SDRAM Device CAS Latencies Supported CS Latency WE Latency SDRAM Module Attributes SDRAM Device Attributes: General MT9LSDT1672A MT18LSDT3272A 128 256 SDRAM 12 10 1 or 2 72 0 LVTTL 7ns (-13E) 7.5ns (-133 8ns (-10E) 5.4ns (-13E/-133) 6ns (-10E) 80 08 04 0C 0A 01 48 00 01 70 75 80 54 60 80 08 04 0C 0A 02 48 00 01 75 75 80 54 60 ECC 15.625µs/SELF 8 8 1 02 80 08 08 01 02 80 08 08 01 SDRAM Cycle Time , tCK (CAS Latency = 2) 1, 2, 4, 8, PAGE 4 2, 3 0 0 UNBUFFERED 0E 7.5ns (13E) 10ns (-133/-10E) 8F 04 06 01 01 00 0E 75 A0 8F 04 06 01 01 00 0E 75 A0 24 SDRAM Access from CLK, tAC (CAS Latency = 2) 5.4ns (-13E) 6ns (-133/-10E) 54 60 54 60 25 SDRAM Cycle Time, tCK (CAS Latency = 1) 00 00 11 12 13 14 15 16 17 18 19 20 21 22 23 26 SDRAM Cycle Time, tCK (CAS Latency = 3) SDRAM Access from CLK, tAC (CAS Latency = 1) 27 Minimum Row Precharge Time, 28 Minimum Row Active to Row Active, tRRD 29 Minimum RAS# to CAS# Delay, tRCD 30 Minimum RAS# Pulse Width, tRAS (See note 1) 31 Module Rank Density 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 15ns (-13E) 20ns (-133/-10E) 14ns (-13E) 15ns (-133) 20ns (-10E) 15ns (-13E) 20ns (-133/-10E) 45ns (-13E) 44ns (-133) 50ns (-10E) 128MB tRP 22 00 00 0F 14 0E 0F 14 0F 14 2D 2C 32 20 oF 14 0E 0F 14 0F 14 2D 2C 32 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Table 22: Serial Presence-Detect Matrix (Continued) “1”/”0”: Serial data, “driven to HIGH”/”driven to LOW”; VDD = +3.3V ±0.3V BYTE DESCRIPTION 32 Command and Address Setup Time, tAS, tCMS 33 Command and Address Hold Time, tAH, tCMH 34 Data Signal Input Setup Time, tDS 35 Data Signal Input Hold Time, tDH 36-40 41 Reserved 42-61 62 63 Reserved SPD Revision Checksum For Bytes 0-62 64 65-71 72 73-90 91 92 93 94 95-98 99-125 126 Manufacturer’s JEDEC ID Code Manufacturer’s JEDEC ID Code(Cont.) Manufacturing Location Module Part Number (ASCII) PCB Identification Code Identification Code (Cont.) Year of Manufacture in BCD Week of Manufacture in BCD Module Serial Number Manufacturer-Specific Data (RSVD) System Frequency 127 ENTRY (VERSION) 1.5ns (-13E/-133) 2ns (-10E) 0.8ns (-13E/-133) 1ns (-10E) 1.5ns (-13E/-133) 2ns (-10E) 0.8ns (-13E/-133 1ns (-10E)) 60ns (-13E) 66ns (-133) 70ns (10E) Device Minimum Active/Auto-Refresh Time, tRC REV. 2.0 (-13E) (-133) (-10E) MICRON 1–12 1–9 0 100 MHz (-13E/-133/10E) SDRAM Component & Clock Detail MT9LSDT1672A MT18LSDT3272A 15 20 08 10 15 20 08 10 00 3C 42 46 00 02 A6 F2 3E 2C FF 01–0C Variable Data 01–09 00 Variable Data Variable Data Variable Data 15 20 08 10 15 20 08 10 00 3C 42 46 00 02 A7 F3 3F 2C FF 01–0C Variable Data 01–09 00 Variable Data Variable Data Variable Data 64 64 AF FF NOTE: 1. The value of tRAS used for -13E modules is calculated from tRC - tRP. Actual device specification value is 37ns. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Figure 11: 168-Pin DIMM Dimensions – Single Rank STANDARD PCB FRONT VIEW 0.125 (3.18) MAX 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (2X) U1 U2 U4 U3 U5 U6 U7 U8 U9 0.118 (3.00) (2X) 1.380 (35.05) 1.370 (34.80) 0.700 (17.78) TYP U10 0.118 (3.00) TYP 0.250 (6.35) TYP 0.118 (3.00) TYP 1.661 (42.18) 0.039 (1.00)R (2X) 2.625 (66.68) 0.128 (3.25) (2X) 0.118 (3.00) 1.039 (1.00) TYP 0.050 (1.27) TYP 0.054 (1.37) 0.046 (1.17) PIN 84 (PIN 168 ON BACKSIDE) PIN 1 (PIN 85 ON BACKSIDE) 4.550 (115.57) LOW PROFILE PCB 0.125 (3.18) MAX FRONT VIEW 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (2X) U10 U1 U2 U4 U3 U5 U6 U7 U8 U9 1.131 (28.73) 0.700 (17.78) 1.119 (28.42) TYP 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.250 (6.35) TYP 0.118 (3.00) TYP 1.661 (42.18) 0.039 (1.00)R (2X) 2.625 (66.68) 0.128 (3.25) (2X) 0.118 (3.00) 0.039 (1.00) TYP PIN 1 (PIN 85 ON BACKSIDE) 0.050 (1.27) TYP 0.054 (1.37) 0.046 (1.17) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) NOTE: MAX All dimensions in inches (millimeters); MIN or typical where noted. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Figure 12: 168-Pin DIMM Dimensions – Low-Profile PCB STANDARD PCB 0.157 (3.99) MAX FRONT VIEW 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (2X) U4 U3 U2 U1 U5 U7 U6 U8 U9 0.118 (3.00) (2X) 1.380 (35.05) 1.370 (34.80) 0.700 (17.78) TYP U10 0.118 (3.00) TYP 0.250 (6.35) TYP 0.118 (3.00) TYP 1.661 (42.18) 0.039 (1.00)R (2X) 2.625 (66.68) 0.128 (3.25) (2X) 0.118 (3.00) 0.039 (1.00) TYP 0.050 (1.27) TYP 0.054 (1.37) 0.046 (1.17) PIN 84 PIN 1 4.550 (115.57) BACK VIEW U12 U11 U14 U13 U15 U16 U17 U18 U19 PIN 168 PIN 85 0.157 (3.99) MAX LOW PROFILE PCB FRONT VIEW 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (2X) U10 U1 U4 U3 U2 U5 U6 U7 U8 U9 1.131 (28.73) 0.700 (17.78) 1.119 (28.42) TYP 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.250 (6.35) TYP 0.118 (3.00) TYP 1.661 (42.18) 0.039 (1.00)R (2X) 2.625 (66.68) 0.128 (3.25) (2X) 0.118 (3.00) 0.039 (1.00) TYP 0.050 (1.27) TYP 0.054 (1.37) 0.046 (1.17) PIN 84 PIN 1 4.550 (115.57) BACK VIEW U11 U12 U13 U14 U15 U16 U17 PIN 168 U18 U19 PIN 85 NOTE: MAX All dimensions in inches (millimeters); MIN or typical where noted. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) 168-PIN SDRAM UDIMM Data Sheet Designation Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice.. ©2004 Micron Technology, Inc