Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPL5110 SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 TPL5110 Nano-power System Timer for Power Gating 1 Features 3 Description • • • • • • • The TPL5110 Nano Timer is a low power timer with an integrated MOSFET driver ideal for power gating in duty cycled or battery powered applications. Consuming only 35nA, the TPL5110 can enable the power supply line and drastically reduce the overall system stand by current during the sleep time. Such power savings enable the use of significantly smaller batteries making it well suited for energy harvesting or wireless sensor applications. The TPL5110 provides selectable timing intervals from 100ms to 7200s and is designed for power gating applications. In addition, the TPL5110 has a unique One-shot feature where the timer will only power the MOSFET for one cycle. The TPL5110 is available in a 6-pin SOT23 package. 1 Supply Voltage from 1.8V to 5.5V Current Consumption at 2.5V 35nA (typ) Selectable Time Intervals 100ms to 7200s Timer Accuracy 1% (typ) Resistor Selectable Time Interval Manual MOSFET Power On One-shot Feature 2 Applications • • • • • • • • • Battery Powered Systems Internet of Things (IoT) Intruder Detection Tamper Detection Home Automation Sensors Thermostats Consumer Electronics Remote Sensor White Goods Device Information(1) PART NUMBER TPL5110 PACKAGE SOT23 (6) BODY SIZE (NOM) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Simplified Application Schematic µC VOUT TPL5110 VIN VDD EN/ ONE_SHOT GND DRV + Battery VDD POWER MANAGEMENT - DELAY/ M_DRV GND REXT DONE GPIO GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPL5110 SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Application Schematic ........................ Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 4 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Ratings ........................... Thermal Information ................................................. Electrical Characteristics........................................... Timing Requirements ............................................... Typical Characteristics .............................................. 8.2 8.3 8.4 8.5 9 Functional Block Diagram ......................................... 8 Feature Description................................................... 8 Device Functional Modes.......................................... 9 Programming .......................................................... 10 Application and Implementation ........................ 16 9.1 Application Information............................................ 16 9.2 Typical Application ................................................. 16 10 Power Supply Recommendations ..................... 17 11 Layout................................................................... 17 11.1 Layout Guidelines ................................................. 17 11.2 Layout Example .................................................... 18 12 Device and Documentation Support ................. 19 12.1 Trademarks ........................................................... 19 12.2 Electrostatic Discharge Caution ............................ 19 12.3 Glossary ................................................................ 19 Detailed Description .............................................. 8 13 Mechanical, Packaging, and Orderable Information ........................................................... 19 8.1 Overview ................................................................... 8 5 Revision History 2 DATE REVISION NOTES January 2015 * Initial release. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 TPL5110 www.ti.com SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 6 Pin Configuration and Functions 6-Lead SOT-23 Top View TPL5110 1 VDD EN/ ONE_ SHOT 6 2 GND DRV 5 3 DELAY/ M_DRV DONE 4 Pin Functions PIN NO. (1) NAME TYPE (1) DESCRIPTION APPLICATION INFORMATION 1 VDD P Supply voltage 2 GND G Ground 3 DELAY/ M_DRV I Time interval set and manual MOSFET Power ON Resistance between this pin and GND is used to select the time interval. The manual MOSFET power ON switch is also connected to this pin. 4 DONE I Logic Input for watchdog functionality Digital signal driven by the µC to indicate successful processing. 5 DRV O Power Gating output signal generated every tIP The Gate of the MOSFET is connected to this pin. When DRV = LOW, the MOSFET is ON. 6 EN/ ONE_SHOT I Selector of mode of operation When EN/ONE_SHOT = HIGH, the TPL5110 works as a TIMER. When EN/ONE_SHOT = LOW, the TPL5110 turns on the MOSFET one time for the programmed time interval. The next power on of the MOSFET is enabled by the manual power ON. G= Ground, P= Power, O= Output, I= Input. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 3 TPL5110 SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) MIN MAX UNIT Supply Voltage (VDD-GND) -0.3 6.0 V Input Voltage at any pin (2) -0.3 VDD + 0.3 V Input Current on any pin -5 +5 mA Storage Temperature, Tstg -65 150 °C 150 °C Junction Temperature, TJ (3) (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The voltage between any two pins should not exceed 6V. The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human Body Model, per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22-101 (2) ±250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Ratings MIN MAX Supply Voltage (VDD-GND) 1.8 5.5 UNIT V Temperature Range -40 105 °C 7.4 Thermal Information TPL5110 THERMAL METRIC (1) SOT23 UNIT 6 PINS RθJA Junction-to-ambient thermal resistance 163 RθJC(top) Junction-to-case (top) thermal resistance 26 RθJB Junction-to-board thermal resistance 57 ψJT Junction-to-top characterization parameter 7.5 ψJB Junction-to-board characterization parameter 57 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A (1) 4 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 TPL5110 www.ti.com SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 7.5 Electrical Characteristics (1) Specifications are for TA= 25°C, VDD-GND=2.5 V, unless otherwise stated. PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT POWER SUPPLY IDD Supply current (4) Operation mode 35 50 nA Digital conversion of external resistance (Rext) 200 400 µA TIMER tIP tOSC Time interval Period 1650 selectable Time intervals Min time interval 100 Max time interval 7200 Time interval Setting Accuracy (5) Excluding the precision of Rext Time interval Setting Accuracy over supply voltage 1.8V ≤ VDD ≤ 5.5V Oscillator Accuracy ±25 -0.5% ±100 Oscillator Accuracy over supply voltage 1.8V ≤ VDD ≤ 5.5V ±0.4 Oscillator Accuracy over life time (7) tDRV DRV Pulse width t_Rext ppm/V 0.5% -40°C ≤ TA≤ 105°C DONE Pulse width s ±0.6% Oscillator Accuracy over temperature (6) tDONE ms ±400 ppm/°C %/V ±0.24% (6) 100 DONE signal not received ns tIP50ms Time to convert Rext 100 120 ms DIGITAL LOGIC LEVELS VIH Logic High Threshold DONE pin VIL Logic Low Threshold DONE pin VOH VOL VIHM_DRV (1) (2) (3) (4) (5) (6) (7) Logic output High Level DRV pin Logic output Low Level DRV pin 0.7xVDD V 0.3xVDD Iout = 100 µA VDD-0.3 Iout = 1 mA VDD-0.7 V V V Iout = -100 µA 0.3 V Iout = -1 mA 0.7 V Logic High Threshold DELAY/M_DRV pin 1.5 V Electrical Characteristics Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. The supply current excludes load and pull-up resistor current. Input pins are at GND or VDD. The accuracy for time interval settings below 1second is ±100ms. This parameter is specified by design and/or characterization and is not tested in production. Operational life time test procedure equivalent to10 years. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 5 TPL5110 SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 www.ti.com 7.6 Timing Requirements MIN (1) trDRV Rise Time DRV tfDRV Fall Time DRV (3) tDDONE DONE to DRV delay tM_DRV Valid manual MOSFET Power ON tDB (1) (2) (3) (4) (3) NOM (2) MAX (1) UNIT Capacitive load 50 pF 50 ns Capacitive load 50 pF 50 ns Min delay (4) 100 ns Max delay (4) tDRV Observation time 30ms 20 De-bounce manual MOSFET Power ON ms 20 ms Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. This parameter is specified by design and/or characterization and is not tested in production. from DRV falling edge. VDD EN/ ONE_SHOT ttDDONEt tDONE DONE t tDRVt trDRV t tDRV + tDBt t tIPt DRV tfDRV t tIPt tR_EXT DELAY/ M_DRV ttM_DRV Figure 1. TPL5110 Timing 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 TPL5110 www.ti.com SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 7.7 Typical Characteristics 80 80 TA= -40°C TA= 25°C TA= 70°C TA= 105°C 70 Supply current (nA) Supply current (nA) 70 VDD= 1.8V VDD= 2.5V VDD= 3.3V VDD= 5.5V 60 50 40 60 50 40 30 30 20 1.5 1.9 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 20 -40 5.5 -25 -10 5 Figure 2. IDD vs. VDD 35 50 65 80 95 110 95 110 Figure 3. IDD vs. Temperature 2 2 TA= -40°C TA= 25°C TA= 70°C TA= 105°C VDD= 1.8V VDD= 2.5V VDD= 3.3V VDD= 5.5V 1.5 Oscillator accuracy (%) 1.5 Oscillator accuracy (%) 20 Temperature (°C) Supply Voltage (V) 1 0.5 0 1 0.5 0 -0.5 -0.5 -1 1.5 1.9 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 -1 -40 5.5 -25 -10 5 20 35 50 65 80 Temperature (°C) Supply Voltage (V) Figure 4. Oscillator Accuracy vs. VDD Figure 5. Oscillator Accuracy vs. Temperature 1000 40% POR REXT READING 35% 30% 10 Frequency Supply current (PA) 100 1 TIMER MODE 0.1 25% 20% 15% 10% 5% 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Time (s) 0.8 0.9 1 0 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 Accuracy (%) number of observations >20000 1s < tIP ≤ 7200s Figure 7. Time interval Setting Accuracy Figure 6. IDD vs. Time Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 7 TPL5110 SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 www.ti.com 8 Detailed Description 8.1 Overview The TPL5110 is a timer with power gating feature. It is ideal for use in power-cycled applications and provides selectable timing from 100ms to 7200s. Once configured in timer mode (EN/ONE_SHOT= HIGH) the TPL5110 periodically sends out a DRV signal to a MOSFET to turn on the µC. If the µC replies with a DONE signal within the programmed time interval (tDRV) the TPL5110 turns off the µC, otherwise the TPL5110 keeps the µC in the on state for a time equal to tDRV. The TPL5110 can work also in a one shot mode (EN/ONE_SHOT= LOW). In this mode the DRV signal is sent out just one time at the power on of the TPL5110 to turn on the µC. If the µC replies with a DONE signal within the programmed time interval (tDRV) the TPL5110 turns off the µC, otherwise the TPL5110 keeps the µC in the on state for a time equal to tDRV. 8.2 Functional Block Diagram VDD EN/ ONE_SHOT LOW FREQUENCY OSCILLATOR FREQUENCY DIVIDER LOGIC CONTROL DRV DONE DELAY/ M_DRV DECODER & MANUAL RESET DETECTOR GND 8.3 Feature Description The TPL5110 implements a periodical power gating feature or one shot power gating according to the EN/ONE_SHOT voltage. A manual MOSFET Power ON function is realized by momentarily pulling the DELAY/M_DRV pin to VDD. 8.3.1 DRV The gate of the MOSFET is connected to the DRV pin. When DRV= LOW, the MOSFET is turned ON. The pulse generated at DRV is equal to the selected time interval period, minus 50ms. It is shorter in the case of a DONE signal received from the µC. If the DONE signal is not received within the programmed time interval (minus 50ms), the DRV signal will be high for the last 50ms of the time interval in order to turn off the MOSFET before the next cycle starts. The default value (after resistance reading) is HIGH. The signal is sent out from the TPL5110 when the programmed time interval starts. When the DRV is LOW, the manual power ON signal is ignored. 8.3.2 DONE The DONE pin is driven by a µC to signal that the µC is working properly. The TPL5110 recognizes a valid DONE signal as a low to high transition; if two or more DONE signals are received within the time interval, only the first DONE signal is processed. The minimum DONE signal pulse length is 100ns. When the TPL5110 receives the DONE signal it asserts DRV logic HIGH. 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 TPL5110 www.ti.com SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 8.4 Device Functional Modes 8.4.1 Startup During startup, after POR, the TPL5110 executes a one-time measurement of the resistance attached to the DELAY/M_DRV pin in order to determine the desired time interval for DRV. This measurement interval is tR_EXT. During this measurement a constant current is temporarily flowing into REXT. Once the reading of the external resistance is completed the TPL5110 enters automatically in one of the 2 modes according to the EN/ONE_SHOT value.The EN/ONE_SHOT pin needs to be hard wired to GND or VDD according to the required mode of operation. ttIPt ttIPt ttDRVt DRV FORCED DRV RISING MISSED DONE DONE EN/ ONE_SHOT DELAY/ M_DRV POR RESISTANCE READING Figure 8. Startup - Timer mode 8.4.2 Timer Mode During timer mode (EN/ONE_SHOT = HIGH), the TPL5110 asserts periodic DRV pulses according to the programmed time interval. The length of the DRV pulses is set by the receiving of a DONE pulse from the uC. See Figure 8. 8.4.3 One Shot Mode During One shot mode (EN/ONE_SHOT = LOW), the TPL5110 generates just one pulse at the DRV pin which lasts according to the programmed time interval. In one-shot mode, other DRV pulses can be triggered using the DELAY/M_DRV pin. If a valid manual power ON occurs when EN/ONE_SHOT is LOW, the TPL5110 generates just one pulse at the DRV pin. The duration of the pulse is set by the programmed time interval. Also in this case, if a DONE signal is received within the programmed time interval (minus 50ms), the MOSFET connected to the DRV pin is turned off. See Figure 9 and Figure 10. ttIPt DRV DONE EN/ ONE_SHOT DELAY/ M_DRV POR RESISTANCE READING Figure 9. Startup One Shot Mode, (DONE received within tIP) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 9 TPL5110 SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 www.ti.com Device Functional Modes (continued) ttIPt ttDRVt DRV FORCED DRV RISING MISSED DONE DONE EN/ ONE_SHOT DELAY/ M_DRV POR RESISTANCE READING Figure 10. Startup One Shot Mode, (no DONE received within tIP) 8.5 Programming 8.5.1 Configuring the Time Interval with the DELAY/M_DRV Pin The time interval between 2 adjacent DRV pulses (falling edges, in timer mode) is selectable through an external resistance (REXT) between the DELAY/M_DRV pin and ground. The resistance (REXT) must be in the range between 500Ω and 170kΩ. At least a 1% precision resistance is recommended. See section Selection of the External Resistance on how to set the time interval using REXT. 8.5.2 Manual MOSFET Power ON Applied to the DELAY/M_DRV Pin If VDD is connected to the DELAY/M_DRV pin, the TPL5110 recognizes this as a manual MOSFET Power ON condition. In this case the time interval is not set. If the manual MOSFET Power ON is asserted during the POR or during the reading procedure, the reading procedure is aborted and is re-started as soon as the manual MOSFET Power ON switch is released. A pulse on the DELAY/M_DRV pin is recognized as a valid manual MOSFET Power ON only if it lasts at least 20ms (observation time is 30ms). The manual MOSFET Power ON may be implemented using a switch (momentary mechanical action). If the DRV is already LOW (MOSFET ON) the manual MOSFET Power ON is ignored. ttIPt ttIPt DRV DONE EN/ ONE_SHOT ttM_DRVt ttDBt ttM_DRVt ttM_DRVt DELAY/ M_DRV VALID M_DRV NOT VALID M_DRV IGNORED M_DRV DRV ALREADY LOW Figure 11. Manual MOSFET Power ON in Timer Mode 10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 TPL5110 www.ti.com SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 Programming (continued) ttIPt DRV DONE EN/ ONE_SHOT ttM_DRVt ttDBt ttM_DRVt DELAY/ M_DRV VALID M_DRV NOT VALID M_DRV Figure 12. Manual MOSFET Power ON in One Shot Mode 8.5.2.1 DELAY/M_DRV A resistance in the range between 500Ω and 170kΩ must to be connected to the DELAY/M_DRV pin in order to select a valid time interval. At the POR and during the reading of the resistance, the DELAY/M_DRV is connected to an analog signal chain through a mux. After the reading of the resistance, the analog circuit is switched off and the DELAY/M_DRV is connected to a digital circuit. In this state, a logic HIGH applied to the DELAY/M_DRV pin is interpreted by the TPL5110 as a manual power ON. The manual power ON detection is provided with a de-bounce feature (on both edges) which makes the TPL5110 insensitive to the glitches on the DELAY/M_DRV. The M_DRV must stay high for at least 20ms to be valid. Once a valid signal at DELAY/M_DRV is understood as a manual power on, the DRV signal will be asserted in the next 10ms. Its duration will be according to the programmed time interval (minus 50ms), or less if the DONE is received. A manual power ON signal resets all the counters. The counters will restart as soon as a valid manual power ON signal is recognized and the signal at DELAY/M_DRV pin is asserted LOW. Due to the asynchronous nature of the manual power ON signal and its arbitrary duration, the LOW status of the DRV signal may be affected by an uncertainty of about ±5ms. An extended assertion of a logic HIGH at the DELAY/M_DRV pin will turn on the MOSFET for a time longer than the programmed time interval. DONE signals received while the DELAY/M_DRV is HIGH are ignored. If the DRV is already LOW (MOSFET ON) the manual power ON is ignored. 8.5.2.2 Circuitry The manual Power ON may be implemented using a switch (momentary mechanical action). The TPL5110 offers 2 possible approaches according to the power consumption constraints of the application. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 11 TPL5110 SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 www.ti.com Programming (continued) µC VOUT TPL5110 VIN VDD EN/ ONE_SHOT GND DRV + Battery VDD POWER MANAGEMENT - DELAY/ M_DRV DONE GPIO REXT GND GND Figure 13. Manual MOSFET Power ON with SPST Switch For use cases that do not require the lowest power consumption, using a single pole single throw switch may offer a lower cost solution. The DELAY/M_DRV pin may be directly connected to VDD with REXT in the circuit. The current drawn from the supply voltage during the manual power ON is given by VDD/REXT. µC VOUT TPL5110 VIN VDD EN/ ONE_SHOT GND DRV + Battery VDD POWER MANAGEMENT - DELAY/ M_DRV DONE GPIO REXT GND GND Figure 14. Manual MOSFET Power ON with SPDT Switch The manual MOSFET Power ON function may also be asserted by switching DELAY/M_DRV from REXT to VDD using a single pole double throw switch, which will provide a lower power solution for the manual power ON, because no current flows. 8.5.3 Selection of the External Resistance In order to set the time interval, the external resistance REXT is selected according the following formula: R EXT § b 100 ¨ ¨ © b 2 4 a c 100 T 2a ·¸ ¸ ¹ (1) Where: • • • 12 T is the desired time interval in seconds. REXT is the resistance value to use in Ω. a,b,c are coefficients depending on the range of the time interval. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 TPL5110 www.ti.com SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 Programming (continued) Table 1. Coefficients for Equation 1 SET Time Interval Range (s) a b c 1 1 <T≤ 5 0.2253 -20.7654 570.5679 2 5 <T≤ 10 -0.1284 46.9861 -2651.8889 3 10 <T≤ 100 0.1972 -19.3450 692.1201 4 100 <T≤ 1000 0.2617 -56.2407 5957.7934 5 T> 1000 0.3177 -136.2571 34522.4680 EXAMPLE Required time interval: 8s The coefficient set to be selected is the number 2. The formula becomes § 46.9861 46.98612 4*0.12842561.8889100*8 · ¸ REXT 100¨ ¨ ¸ 2*0.1284 © ¹ (2) The resistance value is 10.18 kΩ. The following Look-Up-Tables contain example values of tIP and their corresponding value of REXT. Table 2. First 9 Time Intervals tIP (ms) Resistance (Ω) Closest real value (Ω) Parallel of two 1% tolerance resistors, (kΩ) 1.0 // 1.0 100 500 500 200 1000 1000 - 300 1500 1500 2.43 // 3.92 400 2000 2000 - 500 2500 2500 4.42 // 5.76 600 3000 3000 5.36 // 6.81 700 3500 3500 4.75 // 13.5 800 4000 4000 6.19 // 11.3 900 4500 4501 6.19 // 16.5 Table 3. Most Common Time Intervals Between 1s to 2h tIP Calculated Resistance (kΩ) Closest Real Value (kΩ) Parallel of Two 1% Tolerance Resistors,(kΩ) 1s 5.20 5.202 7.15 // 19.1 2s 6.79 6.788 12.4 // 15.0 3s 7.64 7.628 12.7// 19.1 4s 8.30 8.306 14.7 // 19.1 5s 8.85 8.852 16.5 // 19.1 6s 9.27 9.223 18.2 // 18.7 7s 9.71 9.673 19.1 // 19.6 8s 10.18 10.180 11.5 // 8.87 9s 10.68 10.68 17.8 // 26.7 10s 11.20 11.199 15.0 // 44.2 20s 14.41 14.405 16.9 // 97.6 30s 16.78 16.778 32.4 // 34.8 40s 18.75 18.748 22.6 // 110.0 50s 20.047 20.047 28.7 // 66.5 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 13 TPL5110 SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 www.ti.com Table 3. Most Common Time Intervals Between 1s to 2h (continued) tIP Calculated Resistance (kΩ) Closest Real Value (kΩ) Parallel of Two 1% Tolerance Resistors,(kΩ) 1min 22.02 22.021 40.2 // 48.7 2min 29.35 29.349 35.7 // 165.0 3min 34.73 34.729 63.4 // 76.8 4min 39.11 39.097 63.4 // 102.0 5min 42.90 42.887 54.9 // 196.0 6min 46.29 46.301 75.0 // 121.0 7min 49.38 49.392 97.6 // 100.0 8min 52.24 52.224 88.7 // 127.0 9min 54.92 54.902 86.6 // 150.0 10min 57.44 57.437 107.0 // 124.0 20min 77.57 77.579 140.0 // 174.0 30min 92.43 92.233 182.0 // 187.0 40min 104.67 104.625 130.0 // 536.00 50min 115.33 115.331 150.0 // 499.00 1h 124.91 124.856 221.0 // 287.00 1h30min 149.39 149.398 165.0 // 1580.0 2h 170.00 170.00 340.0 // 340.0 8.5.4 Quantization Error The TPL5110 can generate 1650 discrete timer intervals in the range of 100ms to 7200s. The first 9 intervals are multiples of 100ms. The remaining 1641 intervals cover the range between 1s to 7200s. Because they are discrete intervals, there is a quantization error associated with each value. The quantization error can be evaluated according to the following formula: Err 100 TDESIRED TADC TDESIRED (3) Where: T ADC ª 1 INT « ¬ 100 § ·º R D2 RD ¨¨ a b c ¸¸ » 2 100 100 © ¹¼ RD º ªR INT « EXT » ¬ 100 ¼ (4) (5) REXT is the resistance calculated with Equation 1 and a,b,c are the coefficients of the equation listed in Table 1. 8.5.5 Error Due to Real External Resistance REXT is a theoretical value and may not be available in standard commercial resistor values. It is possible to closely approach the theoretical REXT using two or more standard values in parallel. However, standard values are characterized by a certain tolerance. This tolerance will affect the accuracy of the time interval. The accuracy can be evaluated using the following procedure: 1. Evaluate the min and max values of REXT (REXT_MIN, REXT_MAX with Equation 1 using the selected commercial resistance values and their tolerances. 2. Evaluate the time intervals (TADC_MIN[REXT_MIN], TADC_MAX[REXT_MAX]) with Equation 4. 3. Find the errors using Equation 3 with TADC_MIN, TADC_MAX. The results of the formula indicate the accuracy of the time interval. The example below illustrates the procedure. • Desired time interval , T_desired = 600s, 14 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 TPL5110 www.ti.com • SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 Required REXT, from Equation 1, REXT= 57.44kΩ. From Table 3 REXT can be built with a parallel combination of two commercial values with 1% tolerance: R1=107kΩ, R2=124kΩ. The uncertainty of the equivalent parallel resistance can be found using: 2 §u · §u · uR// R// ¨ R1 ¸ ¨ R 2 ¸ © R1 ¹ © R2 ¹ 2 (6) Where uRn (n=1,2) represent the uncertainty of a resistance, u R n Rn Tolerance 3 (7) The uncertainty of the parallel resistance is 0.82%, meaning the value of REXT may range between REXT_MIN = 56.96 kΩ and REXT_MAX = 57.90 kΩ. Using these value of REXT, the digitized timer intervals calculated with Equation 4 are respectively TADC_MIN = 586.85 s and TADC_MAX = 611.3 s, giving an error range of -1.88% / +2.19%. The asymmetry of the error range is due to the quadratic transfer function of the resistance digitizer. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 15 TPL5110 SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information In battery powered applications one design constraint is the need for low current consumption. The TPL5110 is suitable in applications where there is a need to monitor environmental conditions at a fixed time interval. Often in these applications a watchdog or other internal timer in a µC is used to implement a wakeup function. Typically, the power consumption of these functions is not optimized. Using the TPL5110 to implement a periodical power gating of the µC or of the entire system the current consumption will be only tens of nA. 9.2 Typical Application The TPL5110 can be used in environment sensor nodes such as humidity and temperature sensor node. The sensor node has to measure the humidity and the temperature and transmit the data through a low power RF micro such as the CC2531. Since the temperature and the humidity in home application do not change so fast, the measurement and the transmission of the data can be done at very low rate, such as every 30 seconds. The RF micro should spend most of the time in counting the elapsed time, but using the TPL5110 it is possible to complete turn off the RF micro and extend the battery life. The TPL5110 will turn on the RF micro when the programmed time interval elapses or for debug purpose with the manual MOSFET Power ON switch. VIN DC-DC BOOST VOUT ENB TPL5110 + Lithium ion battery VDD EN/ ONE_SHOT GND DRV DELAY/ M_DRV CC2531 GND Rp 100k RF VDD DONE GPIO - Rp 100k HDC1000 VDD SCL SCL SDA SDA GND GND Figure 15. Sensor Node 9.2.1 Design Requirements The Design is driven by the low current consumption constraint. The data are usually acquired on a rate which is in the range between 30s and 60s. The highest necessity is the maximization of the battery life. The TPL5110 helps achieve this goal because it allows turning off the RF micro. 9.2.2 Detailed Design Procedure When the focal constraint is the battery life, the selection of a low power voltage regulator and low leakage MOSFET to power gate the µC is mandatory. The first step in the design is the calculation of the power consumption of each device in the different mode of operations. An example is the HDC1000, in measurement mode the RF micro is in normal operation and transmission. The different modes offer the possibility to select the appropriate time interval which respect the application constraint and maximize the life of the battery. 16 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 TPL5110 www.ti.com SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 Typical Application (continued) 9.2.3 Application Curves Current consumption Without TPL5110 With TPL5110 Time Figure 16. Effect of TPL5110 on Current Consumption 10 Power Supply Recommendations The TPL5110 requires a voltage supply within 1.8 V and 5.5 V. A multilayer ceramic bypass X7R capacitor of 0.1μF between VDD and GND pin is recommended. 11 Layout 11.1 Layout Guidelines The DELAY/M_DRV pin is sensitive to parasitic capacitance. It is suggested that the traces connecting the resistance on this pin to GROUND be kept as short as possible to minimize parasitic capacitance. This capacitance can affect the initial set up of the time interval. Signal integrity on the DRV pin is also improved by keeping the trace length between the TPL5110 and the gate of the MOSFET short to reduce the parasitic capacitance. The EN/ONE_SHOT needs to be tied to GND or VDD with short traces. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 17 TPL5110 SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 www.ti.com 11.2 Layout Example Figure 17. Layout 18 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 TPL5110 www.ti.com SNAS650 – JANUARY 2015 – REVISED JANUARY 2015 12 Device and Documentation Support 12.1 Trademarks All trademarks are the property of their respective owners. 12.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5110 19 PACKAGE OPTION ADDENDUM www.ti.com 16-Jan-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TPL5110DDCR ACTIVE SOT DDC 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 ZALX TPL5110DDCT ACTIVE SOT DDC 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 ZALX (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 16-Jan-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jan-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPL5110DDCR SOT DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPL5110DDCT SOT DDC 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jan-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPL5110DDCR SOT DDC 6 3000 210.0 185.0 35.0 TPL5110DDCT SOT DDC 6 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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