L6585DE Combo IC for PFC and ballast control Features ■ ■ PFC section – transition mode PFC with over-current protection – over-voltage protection – feedback disconnection – under-voltage lockout – PFC choke saturation detection – THD optimizer SO-20 – programmable and precise end-of-life protection compliant with all ballast configurations – smart hard switching detection – fast ignition voltage control with choke saturation detection – half-bridge over-current control Half-bridge section – preheating and ignition phases independently programmable – 3 % oscillator precision – 1.2 µs dead time Figure 1. April 2009 Block diagram Rev 2 1/33 www.st.com 33 Contents L6585DE Contents 1 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 2/33 5.1 VCC section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 PFC section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.1 TM PFC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.2 Leading edge blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.3 THD optimizer feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.4 Over-voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.5 Disabling the L6585DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.6 Feedback disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.7 PFC over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Ballast section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Half-bridge drivers and integrated bootstrap diode . . . . . . . . . . . . . . . . . 18 6.2 Normal start-up description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 Startup sequence with old or damaged lamps . . . . . . . . . . . . . . . . . . . . . 21 6.4 Old lamp management during run mode . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.5 Rectifying effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.6 Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.7 Hard switching protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 L6585DE Contents 6.8 Choke saturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3/33 Pin settings L6585DE 1 Pin settings 1.1 Connection Figure 2. 1.2 Functions Table 1. Pin functions Pin n. Name Function 1 OSC An external capacitor to ground fixes the half-bridge switching frequency with a ± 3 % precision. RF Voltage reference capable of sourcing up to 240 µA. The current sunk from this pin fixes the switching frequency of the half-bridge for each operating state. A resistor (RRUN) connected to ground sets the half-bridge operating frequency combined with the capacitor connected to the pin OSC. A resistor connected to EOI (RPRE) sets the maximum half-bridge switching frequency during preheating combined with RRUN and COSC. EOI Connected to ground by a capacitor that, combined with RPRE, determines the ignition time. Preheating: low impedance to set high switching frequency Ignition and run mode: high impedance with controlled current sink in case of HBCS threshold triggering. 2 3 4/33 Pin connection (top view) L6585DE Pin settings Table 1. Pin n. 4 Pin functions (continued) Name Function Tch Pin for setting the preheating time and protection intervention. Connect an RC parallel network (Rd and Cd) to ground. Preheating: the Cd is charged by an internal current generator. When the pin voltage reaches 4.63 V the generator is disabled and the capacitor discharges because of Rd. Once the voltage drops below 1.5 V, the preheating finishes, the ignition phase starts and the RdCd is pulled to ground. Ignition and Run mode: During proper behavior of the IC, this pin is low impedance. During a fault (either over-current or EOL) the internal generator charges the Cd to 4.63 V and then another current generator discharges the same capacitor. In this way, Cd sets the fault timing (shorter than preheating time). EOLP Pin to program the EOL comparator. It is possible to select both the EOL sensing method (fixed reference or reference in tracking with CTR) and the window comparator amplitude by connecting a resistor (REOLP) to ground. EOL Input for the window comparator. It can be used to detect lamp ageing for either “lamp to ground” or “block capacitor to ground” configurations. This function is blanked during the ignition phase. 7 CTR Input pin for: - PFC over-voltage detection: the PFC driver is stopped until the voltage returns in the proper operating range - Feedback disconnection detection - Reference for EOL comparator (in case tracking reference) - The pin can be used also for shutdown 8 MULT Multiplier external input. This pin is connected to the rectified mains voltage via a voltage divider and provides the sinusoidal reference to the PFC current loop. 9 Output of the error amplifier. A compensation network is placed between this pin COMP and INV to achieve stability of the PFC voltage control loop and ensure high power factor and low THD. 5 6 10 11 12 INV Inverting input of the error amplifier. Output voltage of the PFC pre-regulator is fed to the pin through a voltage divider. ZCD Boost inductor demagnetization sensing input for PFC transition-mode operation. A negative-going edge triggers PFC MOSFET turn-on. During startup or when the voltage is not high enough to arm the internal comparator, the PFC driver is triggered by means of an internal starter. Input to the PFC PWM comparator. The current flowing through the PFC MOSFET is sensed through a resistor. The resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the PFCCS multiplier, to determine the PFC MOSFET’ s turnoff. A second comparison level detects abnormal currents (due to boost inductor saturation, for example) and, on this occurrence, shuts down the PFC gate. An internal LEB prevents undesired function triggering. 5/33 Pin settings L6585DE Table 1. Pin n. Name Function 13 PFG PFC gate driver output. The totem pole output stage is able to drive power MOSFETs with a peak current of 300 mA source and 600 mA sink (typ. values). 14 3-level half-bridge current monitor for current control. The current flowing through the HB MOSFET is sensed through a resistor. The resulting voltage is applied to this pin. First level threshold (1.05 V, active during run mode): in case of threshold crossing the IC reacts with frequency increase in order to limit the half-bridge (and lamp) current. Second level threshold (1.6 V, active during ignition and run mode): - Ignition: in case of threshold crossing during the frequency shift, the IC reacts with frequency increase in order to limit the lamp voltage and preventing operation below resonance. HBCS - Run mode: in case of threshold crossing because of current spikes (due, for example, to capacitive mode / cross-conduction) longer than 200 ns the L6585DE is latched in low consumption mode to avoid damage to the MOSFETs. Third level threshold (2.75 V, active during ignition and run mode): - Ignition: in case of threshold crossing during frequency shift (e.g. caused by choke saturation), the IC latches to avoid damage to the MOSFETs. - Run mode: in case of threshold crossing by a hard switching event (spike duration equal to around 40 ns) an internal counter is increased. After around 350 (typ.) subsequent hard switching events the IC is latched in low consumption mode. 15 GND Ground. 16 LSD Low side driver output: the output stage can deliver 290 mA source and 480 mA sink (typ. values). 17 VCC Supply voltage of both the signal part of the IC and the gate driver. Clamped with a Zener inside. 18 OUT High-side driver floating reference. This pin must be connected close to the source of the high side power MOSFET. 19 HSD High-side driver output: the output stage can deliver 290 mA source and 480 mA sink (typ. values). 20 6/33 Pin functions (continued) Bootstrapped supply voltage. Bootstrap capacitor must be connected between this pin and OUT pin. BOOT Patented, integrated circuitry replaces the external bootstrap diode by means of a high voltage DMOS, synchronously driven with the low side power MOSFET. L6585DE Electrical data 2 Electrical data 2.1 Maximum ratings Table 2. Absolute maximum ratings Symbol Pin VBOOT 20 VOUT dVOUT /dt VCC Value Unit Floating supply voltage -1 to 618 V 18 Floating ground voltage -3 to VBOOT – 18 V 18 Floating ground max. slew rate 50 V/ns Self-limited V -0.3 to 5 V -0.3 to 2.7 V 17 1, 3, 4, 8, 10, 12 Parameter (1) IC supply voltage (ICC = 20 mA) Analog input and outputs 2, 5 VEOL 6 Maximum EOL voltage -0.3 to VCC V VCTR 7 Maximum CTR voltage -0.3 to 7 V VHBCS 14 Maximum half-bridge current sense voltage -5 to 5 V 9, 11 Self-limited IRF 2 Current capability 240 μA IEOLP 5 Current capability 100 μA FOSC(MAX) Maximum operating frequency 250 kHz PTOT Power dissipation @TA = 70 °C 0.83 W 1. The device has an internal clamping Zener between GND and the VCC pin. It must not be supplied by a low impedance voltage source. Note: ESD immunity for pins 18, 19 and 20 is guaranteed up to 900 V (human body model) 2.2 Thermal data Table 3. Thermal data Symbol RthJA TJ TSTG Description Value Unit 120 °C/W Junction operating temperature range -40 to 150 °C Storage temperature -55 to 150 °C Max. thermal resistance junction to ambient 7/33 Electrical characteristics 3 L6585DE Electrical characteristics VCC = 15 V, TA = 25 °C, CL = 1 nF, COSC = 470 pF, RRUN = 47 kΩ, unless otherwise specified Table 4. Electrical characteristics Symbol Pin Parameter Test condition Min. Typ. Max. Unit 16 V Supply voltage Vcc VCC(on) VCC(OFF) VCC VCC VCC Operating range After turn-on Turn-on threshold (1) 13.6 14.3 15 V Turn-off threshold (1) 9.6 10.3 11 V 16.7 17.1 17.5 V 16 17.1 18 V 250 370 µA Icc = 20 mA, TA = 25 °C VZ VCC Zener voltage Icc = 20 mA, full temperature range IST-UP VCC Start-up current Before turn-on @ 13 V ICC VCC Operating supply current Fpfc = 50 kHz Iq VCC Residual current 11 Supply current 7 IC latched mA 350 µA -1 µA PFC section – multiplier input IMULT MULT Input bias current VMULT = 0 V VMULT MULT Linear operation range VCOMP = 3 V MULT Output max. slope VMULT = 0 to 1 V, VCOMP = Upper clamp 0.75 V/V MULT Gain VMULT = 1 V, VCOMP= 3 V 0.52 1/V ΔVCS ΔVMULT KM 0 to 3 V PFC section – error amplifier VINV IINV Gv INV Voltage feedback input threshold INV Line regulation INV Input bias current INV 2.52 VCC = 10.3 V to 16 V Voltage gain Open loop Gain-bandwidth product (2) Source current (2) V 50 mV -1 µA dB 1 MHz VCOMP = 4V, VINV = 2.4 V -2.6 mA Sink current VCOMP = 4V, VINV = 2.6 V 4 mA Upper clamp voltage ISOURCE = 0.5 mA 4.2 V Lower clamp voltage ISINK = 0.5 mA 2.25 V CTR > 3.4 V 1.2 V INV ICOMP COMP VCOMP COMP VDIS INV Open loop detection threshold COMP Static OVP threshold 60 2.57 80 GB 8/33 2.47 2.1 2.25 2.4 V L6585DE Table 4. Symbol Electrical characteristics Electrical characteristics (continued) Pin Parameter Test condition Min. Typ. Max. Unit CTR pin DIS CTR PFOV CTR Shutdown threshold Falling edge 0.75 V 120 mV 3.4 V 140 mV Lower threshold (falling) 1.7 V Hysteresis 120 mV Higher threshold (rising) 3.4 V Hysteresis 140 mV Hysteresis Dynamic PFC overvoltage Rising edge Hysteresis CTR Available range as tracking reference PFC section – current sense comparator ICS PFCS Input bias current VCS = 0 V 100 1.65 tLEB PFCS Leading edge blanking (2) VCSstop PFCS PFC stop threshold VCTR td(H-L) PFCS Delay to output VCSclamp PFCS Current sense reference clamp -1 µA 200 300 ns 1.75 1.85 V 120 VCOMP = Upper clamp 1 1.08 ns 1.16 V PFC section – zero current detector VZCDH ZCD Upper clamp voltage IZCD = 2.5 mA 5 VZCDL ZCD Lower clamp voltage IZCD = -2.5 mA -0.3 VZCDA ZCD Arming voltage (positive-going edge) (2) 1.4 V VZCDT ZCD Triggering voltage (negative-going edge) (2) 0.7 V IZCDb ZCD Input bias current VZCD = 1 to 4.5 V IZCDsrc ZCD Source current capability -4 mA IZCDsnk ZCD Sink current capability 4 mA V 0 0.3 1 V µA PFC section – gate driver ISINK = 10 mA 0.2 V PFG Output high/low tf PFG Fall time 40 90 ns tr PFG Rise time 90 140 ns ISINK PFG Peak sink current 475 600 mA ISOURCE PFG Peak source current 200 300 mA PFG Pull-down resistor 10 kΩ ISOURCE = 10 mA 14.5 V 9/33 Electrical characteristics Table 4. Symbol L6585DE Electrical characteristics (continued) Pin Parameter Test condition Min. Typ. Max. Unit Half bridge section – timing and oscillator ICH TCH Charge current VTCH = 2.2 V VCHP TCH Charge threshold (positive going-edge) (1) VCHN TCH Discharge threshold (negative going edge) (1) TCH Leakage current 1.5 V < VTCH < 4.5 V, falling ICHsnk TCH Discharge current During protection: reduced timing VTCH = 3 V 26 RTCH TCH Internal impedance Run mode 100 EOI Open state current VEOI = 2 V EOI EOI impedance During preheating REOI IEOI EOI EOI current generator during ignition and run mode 31 4.53 EOI 4.73 1.50 Tspike = 200 ns (3) 20 Tspike = 400 ns (3) 100 Tspike = 600 ns (3) 200 V V 0.1 Tspike = 1 µs (3) VEOI 4.63 µA µA µA 200 Ω 0.15 µA 150 Ω µA 270 EOI threshold (1) 1.83 1.9 1.98 V (1) 1.92 2 2.08 V VREF RF Reference voltage IRF RF Max current capability IOSCratio OSC 240 µA IOSC/IRF VOSC = 3 V Rising threshold (1) 3.7 V OSC Falling threshold (1) 0.9 V D OSC Output duty cycle TDEAD OSC FRUN FPRE OSC 4 48 50 52 % Dead time 0.96 1.2 1.44 µs OSC Half-bridge oscillation frequency (run mode) 58.4 60.2 62 KHz OSC Half-bridge oscillation frequency (preheating) 113.2 116.7 120.2 KHz RPRE = 50 kΩ Half bridge section – end-of-life function IEOLP EOLP Current capability 100 VEOLP EOLP Reference voltage 1.92 EOL VS 10/33 EOL Operating range Window comparator reference EOLP = 27 kΩ µA 2 0.95 2.08 V 4.15 V 220 kΩ < REOLP < 270 kΩ or 22 kΩ < REOLP < 27 kΩ tracking with CTR REOLP > 620KΩ or 75 kΩ < REOLP < 91 kΩ 2.5 V L6585DE Table 4. Symbol Electrical characteristics Electrical characteristics (continued) Pin Parameter Test condition Min. EOL EOL Half window amplitude Max. Unit +250 220 kΩ < REOLP < 270 kΩ VW Typ. -240 +160 22 kΩ < REOLP < 27 kΩ mV -150 REOLP > 620 kΩ 720 75 kΩ < REOLP < 91 kΩ 240 Sink/source capability 5.5 µA Half bridge section – Half-bridge current sense HBCSH HBCS Frequency increase VEOI < 1.9 V (ignition) 1.53 1.6 1.66 V HBCSL HBCS Threshold VEOI > 1.9 V (run mode) 0.98 1.05 1.12 V HBCSH,test HBCS VEOI < 1.9 V (ignition) 1.05 V HBCSL,test HBCS Shut down threshold during first low side on time after Tch cycle VEOI > 1.9 V (run mode) 0.82 V HBCSAS HBCS Anti saturation threshold Ignition 2.75 V tLEB,HBCS HBCS Leading edge blanking Ignition 270 ns HBCSCM HBCS Capacitive mode threshold Run mode, Tpulse > 200 ns HBCSHS HBCS Hard switching detector Run mode, Tpulse > 40 ns 1.53 Hysteresis Hard switching events before shutdown NHS Run mode 1.6 1.66 V 2.75 V 450 mV 350 Half bridge section – Low side gate driver LSD Output low voltage ISINK = 10 mA 0.3 LSD Output high voltage ISOURCE = 10 mA LSD Peak source current 200 290 mA LSD Peak sink current 400 480 mA TRISE LSD Rise time 120 ns TFALL LSD Fall time 80 ns LSD Pull-down resistor 45 kΩ 14.5 V V Half bridge section – High side gate driver (voltages referred to OUT) VOUT + 0.3 HSD Output low voltage ISINK = 10 mA HSD Output high voltage ISOURCE = 10 mA HSD Peak source current 200 290 mA HSD Peak sink current 400 480 mA VBOOT – 0.5 V V 11/33 Electrical characteristics Table 4. L6585DE Electrical characteristics (continued) Symbol Pin Parameter Test condition Min. Typ. Max. Unit TRISE HSD Rise time 120 ns TFALL HSD Fall time 80 ns HSD HSD-OUT pull-down 50 kΩ High-side floating gate-drive supply BOOT OUT Leakage current VBOOT = 600 V (2) Leakage current VOUT = 600 V Synchronous bootstrap diode on-resistance VLSD = HIGH (2) 5 µA 5 µA 250 Ω 1. Parameter in tracking 2. Specification over the -40 °C to 125 °C junction temperature range are ensured by design, characterization and statistical correlation 3. A pulse train has been sent to the HBCS pin with f = 6 kHz; the pulse duration is the one indicated in the notes as "TON" 12/33 L6585DE 4 Device description Device description The L6585DE embeds a high performance PFC controller, a ballast controller and all the relevant drivers necessary to build an electronic ballast. The PFC section achieves current mode control operating in transition mode, offering a highly linear multiplier including a THD optimizer that allows for an extremely low THD, even over a large range of input voltages and loading conditions. The PFC output voltage is controlled by means of a voltage-mode error amplifier and a precise internal voltage reference. The ballast controller offers the designer a very precise oscillator, a logic that manages all the operating steps and a full set of protection features: ● Programmable end-of-life detection, compliant with both lamp-to-ground and capacitorto-ground configurations ● Over-current protection with either current limiting or choke saturation protection ● Hard switching events detection High current capability drivers for both the PFC (300 mA source and 600 mA sink) and the half-bridge (290 mA source and 480 mA sink) also allow ballast designs for very high output power (up to 160 W). 13/33 Application information 5 Application information Figure 3. 5.1 L6585DE Typical application VCC section The L6585DE is supplied by applying voltage between the VCC pin and GND pin. An undervoltage lockout (UVLO) prevents the IC from operating with supply voltages too low to guarantee the correct behavior of the internal structures. An internal voltage clamp limits the voltage to around 17 V and can deliver up to 20 mA. For this reason it cannot be used directly as a clamp for the charge pump (current peaks usually reach several hundreds of mA), but can be easily used during startup in order to charge the VCC capacitor or during save mode in order to keep the IC alive, for example, connecting VCC to input voltage through a resistor. In addition to the bulk capacitor (>1 µF)it is suggested to place a 100 nF ceramic capacitor close to VCC pin. 14/33 L6585DE Application information 5.2 PFC section 5.2.1 TM PFC operation The PFC stage contains all the features needed to implement a transition mode PFC controller. Figure 4. PFC section The control loop can be implemented thanks to the high performance error amplifier and the very precise internal voltage reference that fixes the non-inverting input of the E/A to 2.52 V ± 2 %. The control loop reacts in order to bring the inverting input to the same voltage. Connecting the high voltage rail to INV pin, by means of a voltage divider, the output voltage will be easily set. The output of the E/A can be used in order to compensate the control loop with an RC network or, more often, with a simple capacitor connected between INV and COMP pin. The output voltage of the E/A is also fed to the multiplier. This block multiplies the waveform present at the MULT pin by the output of the E/A. The resulting voltage will be used as the threshold for the current sense input. An internal clamp limits the threshold to a maximum value equal to 1 V. In Figure 5 the characteristic curves of the multiplier are reported. Figure 5. Multiplier 15/33 Application information L6585DE The ZCD input can be connected directly to an auxiliary winding of the PFC choke in order to turn on the MOSFET when the choke current reaches zero. This pin has internal clamps and high current capability that makes it compliant with a very wide range of input voltage. At startup, when PFC choke is not yet energized, an internal starter gives ZCD pulses to the PFC gate driver with a repetition rate of approximately 15 kHz. By turning off the MOSFET when the current reaches the threshold and turning on the MOSFET when the choke current reaches zero, a triangular input current whose peaks are modulated by the MULT voltage is obtained. By feeding the MULT pin with the mains waveform, a power factor correction and THD reduction is achieved. 5.2.2 Leading edge blanking Usually current sense voltage is filtered by means of an RC network in order to avoid false turning off of the MOSFET because of the discharge current related to parasitic drain capacitance present at the beginning of the on time of the MOSFET. This filtering generates a delay between the actual threshold crossing and the input triggering. During this time the PFC inductor current increases and the choke may saturate. A leading edge blanking structure makes the PFCCS input active only after 200 ns (typ.) after the PFG turn on. This allows the use of inductors with lower saturation current. However, if saturation occurs, a choke saturation protection turns off the PFC gate as soon as the voltage at pin PFCCS is above 1.7 V. Figure 6. 5.2.3 PFCCS waveforms THD optimizer feature When the input voltage passes through zero, the PFC choke cannot store energy because of the very low voltage across it. This may cause heavy crossover distortion and subsequent THD degradation. A small offset voltage superimposed over the MULT voltage can reduce this issue. The internal THD optimizer increases the performance when the mains voltage reaches zero; this reduces crossover distortion and avoids offset introduction. 16/33 L6585DE 5.2.4 Application information Over-voltage protection Two different over-voltage protections can be detected: dynamic over-voltage, usually due to fast load transition and static over-voltage, due to an excessive input voltage. 5.2.5 ● Dynamic OVP The CTR pin is connected to high voltage rail through a voltage divider. If the voltage at this pin is above 3.4 V, the PFC gate driver is stopped until the voltage returns below the threshold. This limits the risk of choke saturation and MOSFET's damage. ● Static OVP A steady over-voltage may cause abnormal behavior in both the PFC (e.g. because input voltage is higher than PFC output voltage) and the ballast (e.g. overheating, lamp over-current, capacitive mode operating point). A steady over-voltage causes a slow transition of the COMP pin towards the low saturation (around 2.25 V). This fact is considered by the L6585DE as a static over-voltage event and a Tch cycle is started. After this cycle, if the COMP pin is saturated low the IC is latched in low consumption mode. Disabling the L6585DE the CTR pin can be used to shut down the IC without mains disconnection. When CTR is pulled below 0.75 V, the IC is stopped and the internal logic is reset. When CTR is released, the IC starts with a new preheating sequence. This function is available only if the IC is not latched due to a fault protection intervention. 5.2.6 Feedback disconnection protection Very fast output voltage surges may damage the upper resistors of the voltage divider feeding the INV pin, causing a feedback disconnection. In this case, the E/A saturates high and the PFC gate drive turns on the MOSFET for a long time (the current sense threshold assumes its maximum value equal to 1 V) and the choke may saturate, destroying the MOSFET. The output voltage increases very fast and may reach very high value even if OVP is triggered. Feedback disconnection protection is then activated if VINV < 1.2 V and dynamic overvoltage protection is triggered. 5.2.7 PFC over-current protection The PFC MOSFET over-current can occur in cases of PFC choke saturation or in cases of surge from the input, due to the breakdown of the MOSFET body diode. The latter case is observed together with an over-voltage of the PFC output. In both cases, the PFC stage is stopped, whereas the HB stage continues switching. The protection is not latched: once the PFCCS falls below 1.7 V, the PFC driver restarts. 17/33 Ballast section L6585DE 6 Ballast section 6.1 Half-bridge drivers and integrated bootstrap diode The half-bridge drivers are capable of 290 mA source and 480 mA sink current. This makes them able to effectively drive also big MOSFETs Cg up to 2.2 nF. The high-side MOSFET is driven by means of a bootstrapped structure reducing the number of external components. 6.2 Normal start-up description Referring to Figure 7, normal startup proceeds as follows: Figure 7. 18/33 Normal start-up procedure 1. Startup: As soon as Vcc reaches the startup threshold voltage references are built up, the RF and EOLP pin are biased, the EOI pin is pulled down and the TCH pin starts sourcing 31 µA. The frequency of the half-bridge is generated by an internal CCO, connected to COSC and using the RF current as the control signal. With the EOI pin pulled down, the startup frequency will be due to the current flowing in parallel with RPRE and RRUN (see typical application diagram). 2. Preheating: the TCH pin continues to source 31 µA until its voltage reaches 4.63 V, therefore it is left in a high impedance status. As this pin loaded with an RC parallel network, the voltage across this pin decreases exponentially. When it reaches 1.5 V the TCH pin is pulled down and the preheating time ends. During this sequence the EOI pin is pulled down and the half-bridge frequency is the startup frequency. A leading L6585DE Ballast section edge blanking is active during this time in order to avoid any detection of hard switching events, very common during this phase. 3. Ignition: At the end of the TCH cycle, the EOI pin is left free in high impedance mode. Therefore, the capacitor connected between EOI and ground is charged by RF through RPRE. The current sunk from the RF pin decreases exponentially, and the frequency along with it. An exponential decrease in switching frequency causes a linear increase of the lamp voltage. When the lamp voltage reaches the strike value, the lamp ignites. Ignition time is set by the value of RPRE and CIGN. During ignition current control protection, anti-ballast choke saturation protection and leading edge blanking are all active. Figure 8. 4. Half-bridge protection thresholds during ignition Run mode: When the EOI voltage reaches 1.9 V, the IC enters run mode and the switching frequency is set only by RRUN. Current control protection and anti-ballast choke saturation are now active with a lower threshold, leading edge blanking is not active and a fast hard switching detector is activated. Figure 9. Half-bridge protection thresholds during run mode 19/33 Ballast section L6585DE The oscillator characteristic curves represent the half bridge frequency versus the resistance R placed between RF pin and ground. During preheating R is equal to RRUN in parallel with RPRE whereas during Run mode R is equal to RRUN. Each curve is related to a value of the COSC capacitor and are depicted in Figure 10. The value of COSC is measured between pin 1 (OSC) and 15 (GND); for other capacitor values please refer to AN2870. The right value of R during preheating and run mode can be found graphically considering the curve related with the chosen capacitor and respectively FPRE and FRUN“ Figure 10. Oscillator characteristics Some useful equations are given: TPRE = TTch = 4.63 ⎛ 4.63 ⎞ C d + R dC d ⋅ ln⎜ ⎟ ICH ⎝ 1 .5 ⎠ TIGN ≅ 3 ⋅ RPRE ⋅ CIGN 20/33 L6585DE 6.3 Ballast section Startup sequence with old or damaged lamps When an old lamp is connected to the ballast the strike voltage is higher than the nominal voltage and may also be higher than the safety threshold. In this case the lamp can ignite in a time longer than ignition time or may not ignite. In both cases, during ignition time, because of the frequency decrease, the voltage at the output of the ballast can easily reach dangerous values. The same occurs if the lamp tube is broken: the lamp cannot ignite and the lamp voltage must be limited. During ignition time, the L6585DE senses the current flowing into the lamp through a sense resistor connected to the HBCS pin. If the HBCS pin voltage reaches 1.6 V, a small amount of current is sunk from the EOI pin causing a small frequency increase. This frequency modification results, macroscopically, in a frequency regulation and therefore a current regulation and a lamp voltage limiting. As soon as the HBCS pin voltage reaches 1.6 V, the TCH pin starts to charge Cd: when the TCH voltage reaches 4.63 V, the TCH pin is no longer left free (as during preheating), but it sinks 26 uA, causing a faster discharge of Cd. When the TCH voltage reaches 1.5 V, the pin is pulled down and HBCS voltage is checked. If it is above 1.05 V the IC is stopped. If the lamp ignites during this reduced TCH cycle, the EOI pin stops sinking current and if it reaches 1.9 V, the IC enters run mode and TCH pin is immediately pulled down. Figure 11. Startup procedures with old or damaged lamps It can be noted that the reduced TCH cycle time depends only on the value of Cd. It is suggested to start from the choice of Cd in order to obtain the protection time, and then can proceed to the choice of Rd to obtain the desired TPRE. ⎛ 4.63 4.63 − 1.5 ⎞⎟ TTch,reduced = C d ⎜ ≅ C d ⋅ 0.26974 ⋅ 10 6 + ⎟ ⎜I I Tch, snk ⎠ ⎝ Tch, source 21/33 Ballast section 6.4 L6585DE Old lamp management during run mode During run mode, an old lamp can exhibit three different abnormal behaviors: ● Rectifying effect 6.5 ● Over-current ● Hard switching event Rectifying effect The rectifying effect is related to a differential increase of the ohmic resistance of the two cathodes. The lamp equivalent resistance is therefore higher when the lamp current flows in one direction than in the other. The current waveform is distorted and the mean value of the lamp current is no longer zero. The EOL pin is the input of an internal window comparator that can be triggered by a voltage variation due to rectifying effect. The reference of this comparator and the amplitude of the window can be set by connecting a suitable resistor to EOLP pin as indicated in following table: Table 5. EOL window comparator configuration table EOLP resistor range Reference Window amplitude (Wv) 22 k ÷ 27 k VCTR +160 mV / -150 mV 75 k ÷ 91 k 2.5 V 240 mV 220 k ÷ 270 k VCTR + 250 mV / -240 mV > 680 k 2.5 V 720 mV The reference of this comparator can be set at a fixed voltage or at the same voltage as the CTR pin. The fixed reference configuration (see Figure 12) can be used when the lamp is connected to ground, and requires two Zener diodes in order to shift the mean value of the lamp voltage to 2.5 V. The values of the two Zeners affect the symmetry of the intervention of the protection: the best symmetry is obtained choosing two values whose difference is equal to twice the reference voltage: ● VUP = VREF + VZ2 + VF1 + W/2 ● VDOWN = VREF – (VZ1 + VF2) – W/2 ● VUP = - VDOWN ● 2 VREF = VZ1 − VZ2 Where VUP and VDOWN are the maximum allowed values of VK The tracking configuration (see Figure 13) is useful when the lamp is connected between choke and blocking capacitor in the block capacitor-to-ground configuration. In this configuration the voltage across the blocking capacitor is affected by the voltage ripple superimposed on the PFC output. Using a reference affected by the same ripple helps to reject it and avoid premature triggering of the comparator. As soon as the comparator is triggered, a Tch cycle starts in order to improve the noise immunity. 22/33 L6585DE Ballast section Figure 12. End-of-life protection in lamp-to-ground configuration 23/33 Ballast section L6585DE Figure 13. End-of-life protection in blocking capacitor-to-ground configuration 24/33 L6585DE 6.6 Ballast section Over-current protection The appearance of over-current and hard switching events are related to a symmetrical increase of the ohmic resistance of the two cathodes. The overall effect results in an increased equivalent resistance of the lamp and a subsequent modification of the resonance curve of the resonance network (see Figure 14). Figure 14. Resonance curve modification due to lamp ageing Old lamp frun New lamp The increasing of the resonant peak causes over-current that is managed by the L6585DE in the same way as in ignition mode, but the limiting threshold and checking threshold are respectively 1.05 V and 0.82 V. 6.7 Hard switching protection When FRUN is equal to the peak of the resonance curve, the load seen by the half-bridge is purely resistive. In this case, zero voltage switching is no longer present and the MOSFET experiences high current spikes at turn on. The voltage at HBCS pin shows these peaks whose voltage value can be greater than 3 V with a duration that depends on how close the resonant frequency and the operating frequency are. Typical values go from 40 ns to around 200 ns. These spikes may overheat the MOSFETs but, if correctly detected, can prevent the risk of working below the resonance frequency (capacitive mode). The L6585DE can detect these spikes by means of a 2.75 V threshold on HBCS pin, and a counter that shuts down the IC if 350 (typ.) subsequent spikes are detected. This protection is blanked both during preheating and ignition. 6.8 Choke saturation protection Ballast choke saturation implies that very high currents flow into resonance network and an almost instant modification of the resonance curve occurs in a way that the operating point lies immediately in capacitive mode. Steady operation in capacitive mode heavily damages the ballast. 25/33 Ballast section L6585DE Figure 15. Example of capacitive mode operation due to ballast choke saturation OUT pin HBCS Good working Saturating slightly Capacitive mode Therefore, in ignition and run mode a comparator, connected to the HBCS pin, is active with a threshold respectively equal to 2.75 V and 1.6 V. It senses very high currents flowing in the ballast sense resistor and immediately latches the IC in low consumption mode. The width of the triggering spike is above 200 ns. This guarantees that, during run mode, hard switching events (typical duration between 40 ns and 100 ns) cannot trigger the comparator. However, hard switching protection and anti-saturation protection are not perfectly independent. Regarding the pulse width we can indicate four different regions: 26/33 a) Spikes with a duration less than 40 ns: (noise region) no protection can be triggered. b) Spikes with a duration between 40 ns and 100 ns: (HSw region) only hard switching protection will be activated after around 420 events. c) Spikes with a duration between 100 ns and 200 ns: (uncertainty region) hard switching protection is activated, but also anti-saturation protection can be activated, which may result in a sort of early activation of hard switching protection or retarded activation of anti-saturation protection (in this case the saturation of the choke won’t be deep). d) Spikes with a duration longer than 200 ns: (ASP region) anti-saturation protection will certainly be activated at the first event. L6585DE Ballast section Figure 16. Half-bridge current sense pulse detection areas 27/33 Ballast section Table 6. L6585DE Table of faults Active during Fault Condition PH Ign IC behavior Required action Run Fault with immediate activation of latched operating mode Shutdown PFC feedback disconnection 9 9 9 9 9 9 VCTR < 0.75 V - Drivers stopped - IC low consumption (Vcc clamped) VCTR > 0.75 V (IC restarts with PH sequence) VCTR > 3.4 V and VINV < 1.2 V - Drivers stopped - IC low consumption (Vcc clamped) Board failure - Drivers stopped - IC low consumption Vcc clamped) Turn off – turn on sequence Ignition: VHBCS > 2.75 V Half bridge antisaturation protection 9 9 Run mode: VHBCS > 1.6 V Fault with immediate activation of a non latched operating mode PFC dynamic over-voltage 9 9 9 VCTR > 3.4 V - PFC driver stopped Wait for output voltage reduction PFC protection over-current 9 9 9 VPFCCS > 1.7 V - PFC driver stopped Wait for next starter event Fault with timed activation of latched operating mode PFC static OVP 9 9 Lamp end-of-life 9 9 VCOMP < 2.25 V - PFC driver stopped - Tch cycle starts - At the end of cycle, if VCOMP < 2.25 V IC is latched Check the mains voltage VEOL outside allowed range (set by REOLP) - Tch cycle starts - At the end of the cycle if VEOL is out of range the IC is latched Replace the lamp with a new one - Frequency control activated and Reduced Tch Cycle (RTC) starts - At the end of RTC the threshold is reduced (1.05 V during ignition and 0.82 V during run mode) - If VHBCS>reduced threshold IC is stopped Replace the lamp with a new one - After 350 subsequent hard switching events IC is stopped Replace the lamp with a new one Ignition: VHBCS > 1.6 V Lamp over-current 9 9 Run mode: VHBCS > 1.05 V Lamp ageing causing hard switching 28/33 9 VHBCS > 2.75 V L6585DE 7 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 29/33 Package mechanical data Table 7. L6585DE SO-20 mechanical data mm. inch Dim. Min. Typ. A a1 Max. Typ. 2.65 0.1 Max. 0.104 0.2 a2 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45° (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 M S Figure 17. Package dimensions 30/33 Min. 0.75 0.029 8° (max.) L6585DE 8 Ordering information Ordering information Table 8. Order codes Order codes Package Packaging L6585DE SO-20 Tube L6585DETR SO-20 Tape and reel 31/33 Revision history 9 L6585DE Revision history Table 9. 32/33 Document revision history Date Revision Changes 27-Nov-2008 1 Initial release 10-Apr-2009 2 Updated Table 1,Table 2, Table 3, Figure 4 L6585DE Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 33/33