Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN74LVC1G3157 SCES424I – JANUARY 2003 – REVISED JUNE 2015 SN74LVC1G3157 Single-Pole Double-Throw Analog Switch 1 Features 3 Description • • • • • • • This single-pole double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCC operation. 1 • • • 1.65-V to 5.5-V VCC Operation Useful for Both Analog and Digital Applications Specified Break-Before-Make Switching Rail-to-Rail Signal Handling Operating Frequency Up to 300 MHz High Degree of Linearity High Speed, Typically 0.5 ns (VCC = 3 V, CL = 50 pF) Low ON-State Resistance, Typically ≉6 Ω (VCC = 4.5 V) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. Device Information(1) PART NUMBER SN74LVC1G3157 PACKAGE BODY SIZE (NOM) SOT-23 (6) 2.90 mm × 1.60 mm SC70 (6) 2.00 mm × 1.25 mm SOT (6) 1.60 mm × 1.20 mm SON (6) 1.45 mm × 1.00 mm DSBGA (6) 1.41 mm × 0.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • The SN74LVC1G3157 device can handle both analog and digital signals. The SN74LVC1G3157 device permits signals with amplitudes of up to VCC (peak) to be transmitted in either direction. Wearables Portable Computing Internet of Things Audio Signal Processing Simplified Schematic 1 B2 6 S B1 4 A 3 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC1G3157 SCES424I – JANUARY 2003 – REVISED JUNE 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 4 4 4 5 5 6 6 7 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics........................................... Analog Switch Characteristics ................................. Switching Characteristics ......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 8 Detailed Description ............................................ 13 8.1 Overview ................................................................. 13 8.2 Functional Block Diagram ....................................... 13 8.3 Feature Description................................................. 13 8.4 Device Functional Modes........................................ 13 9 Application and Implementation ........................ 14 9.1 Application Information............................................ 14 9.2 Typical Application ................................................. 14 10 Power Supply Recommendations ..................... 16 11 Layout................................................................... 16 11.1 Layout Guidelines ................................................. 16 11.2 Layout Example .................................................... 16 12 Device and Documentation Support ................. 17 12.1 12.2 12.3 12.4 12.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 17 17 17 17 17 13 Mechanical, Packaging, and Orderable Information ........................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (May 2012) to Revision I Page • Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................ 1 • Updated document to new TI data sheet format. ................................................................................................................... 1 • Updated Features. .................................................................................................................................................................. 1 Changes from Revision G (September 2011) to Revision H Page • Changed YZP with correct pin labels. ................................................................................................................................... 3 • Added Thermal Information table. .......................................................................................................................................... 5 • Changed to correct Pin Label "S" ........................................................................................................................................... 5 2 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 SN74LVC1G3157 www.ti.com SCES424I – JANUARY 2003 – REVISED JUNE 2015 5 Pin Configuration and Functions DBV Package 6-Pin SOT-23 Top View DCK Package 6-Pin SC70 Top View B2 1 6 S GND 2 5 VCC B1 3 4 A B2 1 6 S GND 2 5 VCC B1 3 4 A DSF Package 6-Pin SON Top View 1 6 2 5 3 4 1 6 S GND 2 5 VCC B1 3 4 A DRL Package 6-Pin SOT Top View DRY Package 6-Pin SON Top View B2 GND B1 B2 B2 1 6 S GND 2 5 VCC B1 3 4 A YZP Package 6-Pin DSBGA Bottom View S VCC A B1 C1 3 4 C2 GND B1 2 5 B2 B2 A1 1 6 A2 A VCC S Pin Functions PIN SOT-23, SC70, SON, or SOT DSBGA B2 1 A1 I/O Switch I/O. Set S high to enable. GND 2 B1 — Ground B1 3 C1 I/O Switch I/O. Set S low to enable. A 4 C2 I/O Common terminal VCC 5 B2 — Power supply S 6 A2 I NAME I/O DESCRIPTION Select Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 3 SN74LVC1G3157 SCES424I – JANUARY 2003 – REVISED JUNE 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltage (2) VCC (2) (3) MIN MAX UNIT –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 V –50 mA VIN Control input voltage VI/O Switch I/O voltage (2) (3) (4) (5) IIK Control input clamp current VIN < 0 II/O I/O port diode current VI/O < 0 or VI/O > VCC ±50 mA II/O On-state switch current (6) VI/O = 0 to VCC ±128 mA ±100 mA Continuous current through VCC or GND (1) (2) (3) (4) (5) (6) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground unless otherwise specified. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 5.5 V maximum. VI, VO, VA, and VBn are used to denote specific conditions for VI/O. II, IO, IA, and IBn are used to denote specific conditions for II/O. 6.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN MAX 1.65 5.5 V Switch input/output voltage 0 VCC V Control input voltage 0 5.5 V VCC Supply voltage VI/O VIN VIH High-level input voltage, control input VIL Low-level input voltage, control input Δt/Δv TA (1) 4 Input transition rise or fall rate VCC = 1.65 V to 1.95 V VCC = 2.3 V to 5.5 V VCC × 0.75 V VCC × 0.7 VCC = 1.65 V to 1.95 V VCC × 0.25 VCC = 2.3 V to 5.5 V VCC × 0.3 VCC = 1.65 V to 1.95 V 20 VCC = 2.3 V to 2.7 V 20 VCC = 3 V to 3.6 V 10 VCC = 4.5 V to 5.5 V 10 Operating free-air temperature –40 UNIT 85 V ns/V °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 SN74LVC1G3157 www.ti.com SCES424I – JANUARY 2003 – REVISED JUNE 2015 6.4 Thermal Information SN74LVC1G3157 THERMAL METRIC RθJA (1) (1) DBV (SOT-23) DCK (SC70) DRL (SOT) DRY (SON) YZP (DSBGA) 6 PINS 6 PINS 6 PINS 6 PINS 6 PINS 165 259 142 234 123 Junction-to-ambient thermal resistance UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS ON-state switch resistance (2) ron rrange ON-state switch resistance over signal range (2) (3) Difference of ON-state resistance between switches (2) (4) (5) Δron ron(flat) See Figure 1 and Figure 2 ON resistance flatness (2) (4) (6) VI = 0 V IO = 4 mA VI = 1.65 V IO = –4 mA VI = 0 V IO = 8 mA VI = 2.3 V IO = –8 mA VI = 0 V IO = 24 mA VI = 3 V IO = –24 mA VI = 0 V IO = 30 mA VI = 2.4 V IO = –30 mA VI = 4.5 V IO = –30 mA 0 ≤ VBn ≤ VCC (see Figure 1 and Figure 2) See Figure 2 VCC MIN 1.65 V 2.3 V 3V 4.5 V 15 50 8 12 11 30 7 9 9 20 6 7 7 12 7 15 1.65 V 140 2.3 V 45 IA = –24 mA 3V 18 IA = –30 mA 4.5 V VBn = 1.15 V IA = –4 mA 1.65 V 0.5 VBn = 1.6 V IA = –8 mA 2.3 V 0.1 VBn = 2.1 V IA = –24 mA 3V 0.1 VBn = 3.15 V IA = –30 mA 4.5 V 0.1 IA = –4 mA 1.65 V 110 IA = –8 mA 2.3 V 26 IA = –24 mA 3V 9 IA = –30 mA 4.5 V 4 0 ≤ VBn ≤ VCC 0 ≤ VI, VO ≤ VCC (see Figure 3 ) IS(on) ON-state switch leakage current VI = VCC or GND, VO = Open (see Figure 4) IIN Control input current 0 ≤ VIN ≤ VCC ICC Supply current S = VCC or GND 5.5 V ΔICC Supply-current change S = VCC – 0.6 V 5.5 V Ci Control input capacitance (7) 20 IA = –8 mA OFF-state switch leakage current (3) (4) (5) (6) MAX 11 IA = –4 mA Ioff (7) (1) (2) TYP (1) S 1.65 V to 5.5 V 5V Ω Ω 10 Ω Ω ±1 ±0.05 ±1 (1) ±1 5.5 V 0 V to 5.5 V UNIT ±0.1 (1) ±1 ±0.05 1 ±1 (1) µA µA µA 10 µA 500 µA 2.7 pF TA = 25°C Measured by the voltage drop between I/O pins at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages on the two (A or B) ports. Specified by design Δron = ron(max) – ron(min) measured at identical VCC, temperature, and voltage levels This parameter is characterized, but not production tested. Flatness is defined as the difference between the maximum and minimum values of on-state resistance over the specified range of conditions. Ioff is the same as IS(off) (off-state switch leakage current). Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 5 SN74LVC1G3157 SCES424I – JANUARY 2003 – REVISED JUNE 2015 www.ti.com Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Cio(off) Switch input/output capacitance Cio(on) Switch input/output capacitance VCC Bn MIN TYP (1) 5V Bn 5.2 UNIT pF 17.3 5V A MAX pF 17.3 6.6 Analog Switch Characteristics TA = 25°C PARAMETER Frequency response (1) (switch on) FROM (INPUT) A or Bn TO (OUTPUT) Bn or A (2) Crosstalk (between switches) Feed through attenuation (2) (switch off) B1 or B2 A or Bn Charge injection (3) Total harmonic distortion (1) (2) (3) S A or Bn B2 or B1 Bn or A A Bn or A TEST CONDITIONS RL = 50 Ω, fin = sine wave (see Figure 6) RL = 50 Ω, fin = 10 MHz (sine wave) (see Figure 7) CL = 5 pF, RL = 50 Ω, fin = 10 MHz (sine wave) (see Figure 8) CL = 0.1 nF, RL = 1 MΩ (see Figure 9) VI = 0.5 Vp-p, RL = 600 Ω, fin = 600 Hz to 20 kHz (sine wave) (see Figure 10) VCC TYP 1.65 V 300 2.3 V 300 3V 300 4.5 V 300 1.65 V –54 2.3 V –54 3V –54 4.5 V –54 1.65 V –57 2.3 V –57 3V –57 4.5 V –57 3.3 V 3 5V 7 1.65 V 0.1% 2.3 V 0.025% 3V 0.015% 4.5 V 0.01% UNIT MHz dB dB pC Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB. Adjust fin voltage to obtain 0 dBm at input. Specified by design 6.7 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5 and Figure 11) PARAMETER tpd (1) ten FROM (INPUT) TO (OUTPUT) A or Bn Bn or A S Bn (2) tdis (3) tB-M (4) (1) (2) (3) (4) 6 VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V MAX MIN 2 MAX VCC = 3.3 V ± 0.3 V MIN 1.2 MAX VCC = 5 V ± 0.5 V MIN 0.8 0.3 7 24 3.5 14 2.5 7.6 1.7 5.7 3 13 2 7.5 1.5 5.3 0.8 3.8 0.5 0.5 0.5 0.5 UNIT MAX ns ns ns tpd is the slower of tPLH or tPHL. The propagation delay is calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance). ten is the slower of tPZL or tPZH. tdis is the slower of tPLZ or tPHZ. Specified by design. Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 SN74LVC1G3157 www.ti.com SCES424I – JANUARY 2003 – REVISED JUNE 2015 6.8 Typical Characteristics 120 VCC = 1.65 V 100 ron 80 60 40 VCC = 2.3 V 20 VCC = 3 V VCC = 4.5 V 0 0 1 2 3 4 5 VI - V Figure 1. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 7 SN74LVC1G3157 SCES424I – JANUARY 2003 – REVISED JUNE 2015 www.ti.com 7 Parameter Measurement Information ron = VI – V O Ω IO Figure 2. ON-State Resistance Test Circuit Figure 3. OFF-State Switch Leakage-Current Test Circuit VCC VIL or VIH S VCC B1 B2 A S 1 VIL 2 VIH 1 SW VI SW 2 VO VO = Open A GND VI = VCC or GND Figure 4. ON-State Switch Leakage-Current Test Circuit 8 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 SN74LVC1G3157 www.ti.com SCES424I – JANUARY 2003 – REVISED JUNE 2015 Parameter Measurement Information (continued) VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC VCC VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 VCC/2 VCC/2 2 × VCC 2 × VCC 2 × VCC 2 × VCC 50 pF 50 pF 50 pF 50 pF 500 W 500 W 500 W 500 W 0.3 V 0.3 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 5. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 9 SN74LVC1G3157 SCES424I – JANUARY 2003 – REVISED JUNE 2015 www.ti.com Parameter Measurement Information (continued) 50 Ω RL = 50 Ω Figure 6. Frequency Response (Switch On) S VCC VIL or VIH TEST CONDITION VIL 20log10(VO2/VI) VIH 20log10(VO1/VI) VCC S B1 VB1 fin VB2 A Analyzer B2 GND 50 Ω RL RL = 50 Ω Figure 7. Crosstalk (Between Switches) 10 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 SN74LVC1G3157 www.ti.com SCES424I – JANUARY 2003 – REVISED JUNE 2015 Parameter Measurement Information (continued) 50 Ω RL = 50 Ω Figure 8. Feed Through VCC VCC S B1 LOGIC INPUT 1 SW B2 VOUT 2 RGEN VGE A GND RL CL RL/CL = 1 MΩ/100 pF LOGIC INPUT OFF VOUT ON OFF ∆VOUT Q = (∆VOUT) (CL) Figure 9. Charge-Injection Test Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 11 SN74LVC1G3157 SCES424I – JANUARY 2003 – REVISED JUNE 2015 www.ti.com Parameter Measurement Information (continued) 10 kΩ 600 Ω Figure 10. Total Harmonic Distortion VCC VCC S B1 VI = VCC/2 B2 VO A GND VS RL CL RL/CL = 50 Ω/35 pF VO 0.9 x VO tD Figure 11. Break-Before-Make Internal Timing 12 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 SN74LVC1G3157 www.ti.com SCES424I – JANUARY 2003 – REVISED JUNE 2015 8 Detailed Description 8.1 Overview The SN74LVC1G3157 device is a single-pole double-throw (SPDT) analog switch designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G3157 device can handle analog and digital signals. The device permits signals with amplitudes of up to VCC (peak) to be transmitted in either direction. 8.2 Functional Block Diagram B2 S B1 1 6 4 A 3 Figure 12. Logic Diagram (Positive Logic) 8.3 Feature Description The 1.65-V to 5.5-V supply operation allows the device to function in many different systems comprised of different logic levels, allowing rail-to-rail signal switching. Either the B1 channel or the B2 channel is activated depending upon the control input. If the control input is low, B1 channel is selected. If the control input is high, B2 channel is selected. 8.4 Device Functional Modes Table 1 lists the ON channel when one of the control inputs is selected. Table 1. Function Table CONTROL INPUTS ON CHANNEL L B1 H B2 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 13 SN74LVC1G3157 SCES424I – JANUARY 2003 – REVISED JUNE 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN74LVC1G3157 SPDT analog switch is flexible enough for use in a variety of circuits such as analog audio routing, power-up monitor, memory sharing, and so on. For details on the applications, see SCYB014. 9.2 Typical Application Figure 13. Typical Application Schematic 9.2.1 Design Requirements The inputs can be analog or digital, but TI recommends waiting until VCC has ramped to a level in Recommended Operating Conditions before applying any signals. Appropriate termination resistors should be used depending on the type of signal and specification. The Select pin should not be left floating; either pull up or pull down with a resistor that can be overdriven by a GPIO. 14 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 SN74LVC1G3157 www.ti.com SCES424I – JANUARY 2003 – REVISED JUNE 2015 Typical Application (continued) 9.2.2 Detailed Design Procedure Using this circuit idea, a system designer can ensure a component or subsystem power has ramped up before allowing signals to be applied to its input. This is useful for integrated circuits that do not have overvoltage tolerant inputs. The basic idea uses a resistor divider on the VCC1 power rail, which is ramping up. The RC time constant of the resistor divider further delays the voltage ramp on the select pin of the SPDT bus switch. By carefully selecting values for R1, R2, and C, it is possible to ensure that VCC1 will reach its nominal value before the path from A to B2 is established, thus preventing a signal being present on an I/O before the device/system is powered up. To ensure the minimum desired delay is achieved, the designer should use Equation 1 to calculate the time required from a transition from ground (0 V) to half the supply voltage (VCC1/2). R2 Set × VCC1 > VIH of the select pin R1 R2 (1) ( ) Choose Rs and C to achieve the desired delay. When VS goes high, the signal will be passed. 9.2.3 Application Curve Figure 14. VS Voltage Ramp Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 15 SN74LVC1G3157 SCES424I – JANUARY 2003 – REVISED JUNE 2015 www.ti.com 10 Power Supply Recommendations Most systems have a common 3.3-V or 5-V rail that can supply the VCC pin of this device. If this is not available, a Switch-Mode-Power-Supply (SMPS) or a Linear Dropout Regulator (LDO) can be used to provide supply to this device from another voltage rail. 11 Layout 11.1 Layout Guidelines TI recommends keeping signal lines as short as possible. TI also recommends incorporating microstrip or stripline techniques when signal lines are greater than 1 inch in length. These traces must be designed with a characteristic impedance of either 50 Ω or 75 Ω, as required by the application. Do not place this device too close to high-voltage switching components, as they may interfere with the device. 11.2 Layout Example Figure 15. Recommended Layout Example 16 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 SN74LVC1G3157 www.ti.com SCES424I – JANUARY 2003 – REVISED JUNE 2015 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • Implications of Slow or Floating CMOS Inputs, SCBA004. • SN74LVC1G3157 and SN74LVC2G53 SPDT Analog Switches, SCYB014 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G3157 17 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 74LVC1G3157DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CC5F 74LVC1G3157DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CC5F 74LVC1G3157DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C55 ~ C5F ~ C5K ~ C5R) 74LVC1G3157DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C55 ~ C5F ~ C5K ~ C5R) 74LVC1G3157DRLRG4 ACTIVE SOT DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C57 ~ C5R) 74LVC1G3157DRYRG4 ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 C5 SN74LVC1G3157DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (CC55 ~ CC5F ~ CC5K ~ CC5R) SN74LVC1G3157DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C55 ~ C5F ~ C5K ~ C5R) SN74LVC1G3157DRLR ACTIVE SOT DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C57 ~ C5R) SN74LVC1G3157DRY2 ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 C5 SN74LVC1G3157DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 C5 SN74LVC1G3157DSFR ACTIVE SON DSF 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 C5 SN74LVC1G3157YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 (C57 ~ C5N) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2015 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. 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OTHER QUALIFIED VERSIONS OF SN74LVC1G3157 : • Automotive: SN74LVC1G3157-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 18-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) 74LVC1G3157DBVRG4 SOT-23 DBV 6 3000 178.0 9.0 3.17 1.37 4.0 8.0 Q3 SN74LVC1G3157DBVR SOT-23 DBV 6 3000 178.0 9.2 SN74LVC1G3157DBVR SOT-23 DBV 6 3000 180.0 9.2 3.3 3.2 1.55 4.0 8.0 Q3 3.17 3.23 1.37 4.0 8.0 SN74LVC1G3157DBVR SOT-23 DBV 6 3000 178.0 9.0 Q3 3.23 3.17 1.37 4.0 8.0 SN74LVC1G3157DCKR SC70 DCK 6 3000 178.0 Q3 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1G3157DRLR SOT DRL 6 4000 SN74LVC1G3157DRLR SOT DRL 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 180.0 9.5 1.78 1.78 0.69 4.0 8.0 SN74LVC1G3157DRY2 SON DRY 6 Q3 5000 180.0 8.4 1.65 1.2 0.7 4.0 8.0 Q3 3.23 W Pin1 (mm) Quadrant SN74LVC1G3157DRY2 SON DRY 6 5000 180.0 9.5 1.6 1.15 0.75 4.0 8.0 Q3 SN74LVC1G3157DRYR SON DRY 6 5000 179.0 8.4 1.2 1.65 0.7 4.0 8.0 Q1 SN74LVC1G3157DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 SN74LVC1G3157YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74LVC1G3157DBVRG4 SOT-23 DBV 6 3000 180.0 180.0 18.0 SN74LVC1G3157DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 SN74LVC1G3157DBVR SOT-23 DBV 6 3000 205.0 200.0 33.0 SN74LVC1G3157DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 SN74LVC1G3157DCKR SC70 DCK 6 3000 180.0 180.0 18.0 SN74LVC1G3157DRLR SOT DRL 6 4000 202.0 201.0 28.0 SN74LVC1G3157DRLR SOT DRL 6 4000 184.0 184.0 19.0 SN74LVC1G3157DRY2 SON DRY 6 5000 202.0 201.0 28.0 SN74LVC1G3157DRY2 SON DRY 6 5000 184.0 184.0 19.0 SN74LVC1G3157DRYR SON DRY 6 5000 203.0 203.0 35.0 SN74LVC1G3157DSFR SON DSF 6 5000 184.0 184.0 19.0 SN74LVC1G3157YZPR DSBGA YZP 6 3000 220.0 220.0 35.0 Pack Materials-Page 2 MECHANICAL DATA PLASTIC SMALL OUTLINE NO-LEAD DSF (S-PX2SON-N6) 1.05 0.95 A B PIN 1 INDEX AREA 1.05 0.95 0.4 MAX C SEATING PLANE 0.05 C (0.11) TYP SYMM 0.05 0.00 3 2X 0.7 4 SYMM 4X 0.35 6 1 (0.1) PIN 1 ID 6X 6X 0.45 0.35 0.22 0.12 0.07 0.05 C A C B 4208186/F 10/2014 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MO-287, variation X2AAF. www.ti.com PACKAGE OUTLINE YZP0006 DSBGA - 0.5 mm max height SCALE 9.000 DIE SIZE BALL GRID ARRAY B A E BALL A1 CORNER D C 0.5 MAX SEATING PLANE 0.19 0.15 BALL TYP 0.05 C 0.5 TYP C SYMM 1 TYP B 0.5 TYP D: Max = 1.418 mm, Min =1.357 mm E: Max = 0.918 mm, Min =0.857 mm A 6X 0.015 0.25 0.21 C A B 1 2 SYMM 4219524/A 06/2014 NanoFree Is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. TM 3. NanoFree package configuration. www.ti.com EXAMPLE BOARD LAYOUT YZP0006 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 6X ( 0.225) 1 2 A (0.5) TYP SYMM B C SYMM LAND PATTERN EXAMPLE SCALE:40X ( 0.225) METAL 0.05 MAX METAL UNDER MASK 0.05 MIN ( 0.225) SOLDER MASK OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4219524/A 06/2014 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017). www.ti.com EXAMPLE STENCIL DESIGN YZP0006 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 6X ( 0.25) (R0.05) TYP 2 1 A (0.5) TYP SYMM B METAL TYP C SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4219524/A 06/2014 NOTES: (continued) 5. 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