LMZ14202H www.ti.com SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 LMZ14202H 2A, SIMPLE SWITCHER® Power Module for High Output Voltage Check for Samples: LMZ14202H FEATURES 1 • • • 23 • • • • • • • Integrated Shielded Inductor Simple PCB Layout Flexible Startup Sequencing Using External Soft-start and Precision Enable Protection Against Inrush Currents Input UVLO and Output Short Circuit Protection – 40°C to 125°C Junction Temperature Range Single Exposed Pad and Standard Pinout for Easy Mounting and Manufacturing Low Output Voltage Ripple Pin-to-pin Compatible Family: – LMZ14203H/2H/1H (42V Max 3A, 2A, 1A) – LMZ14203/2/1 (42V Max 3A, 2A, 1A) – LMZ12003/2/1 (20V Max 3A, 2A, 1A) Fully Enabled for Webench® Power Designer APPLICATIONS • • • • Intermediate Bus Conversions to 12V and 24V Rail Time Critical Projects Space Constrained / High Thermal Requirement Applications Negative Output Voltage Applications Figure 1. Easy to use 7 pin package PFM 7 Pin Package 10.16 x 13.77 x 4.57 mm (0.4 x 0.542 x 0.18 in) θJA = 16°C/W, θJC = 1.9°C/W RoHS Compliant ELECTRICAL SPECIFICATIONS • • • • Up to 2A Output Current Input Voltage Range 6V to 42V Output Voltage as Low as 5V Efficiency up to 97% PERFORMANCE BENEFITS • • • • High Efficiency Reduces System Heat Generation Low Radiated EMI(EN 55022 Class B Compliant) (1) No Compensation Required Low Package Thermal Resistance DESCRIPTION The LMZ14202H SIMPLE SWITCHER power module is an easy-to-use step-down DC-DC solution capable of driving up to 2A load with exceptional power conversion efficiency, line and load regulation, and output accuracy. The LMZ14202H is available in an innovative package that enhances thermal performance and allows for hand or machine soldering. The LMZ14202H can accept an input voltage rail between 6V and 42V and deliver an adjustable and highly accurate output voltage as low as 5V. The LMZ14202H only requires three external resistors and four external capacitors to complete the power solution. The LMZ14202H is a reliable and robust design with the following protection features: thermal shutdown, input under-voltage lockout, output overvoltage protection, short-circuit protection, output current limit, and allows startup into a pre-biased output. A single resistor adjusts the switching frequency up to 1 MHz. (1) EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SIMPLE SWITCHER is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated LMZ14202H SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 www.ti.com System Performance Efficiency VOUT = 12V 100 EFFICIENCY (%) 95 90 85 80 VIN = 15V VIN = 24V VIN = 30V VIN = 36V VIN = 42V 75 70 0.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Thermal Derating VOUT = 12V, θJA = 16°C/W OUTPUT CURRENT (A) 2.5 2.0 1.5 1.0 0.5 VIN = 15V VIN = 24V VIN = 42V 0.0 -20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (°C) Radiated Emissions (EN 55022 Class B) RADIATED EMISSIONS (dB V/m) 80 Emissions (Evaluation Board) EN 55022 Limit (Class B) 70 60 50 40 30 20 10 0 0 2 200 400 600 800 FREQUENCY (MHz) 1000 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H LMZ14202H www.ti.com SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 Simplified Application Schematic VOUT FB SS EN GND VIN VIN RON LMZ14202H VOUT 30V 24V 18V 15V 12V 5V RFBT 34 k: 34 k: 34 k: 34 k: 34 k: 34 k: RFBB 931: 1.18 k: 1.58 k: 1.91 k: 2.43 k: 6.49 k: RON COUT 619 k: 33 PF 499 k: 33 PF 374 k: 33 PF 287 k: 47 PF 249 k: 47 PF 100 k: 100 PF COUT-ESR 1-75 m: 1-60 m: 1-60 m: 1-65 m: 1-75 m: 1-145 m: VIN 34 - 42V 28 - 42V 22 - 42V 18 - 42V 15 - 42V 8 - 42V VOUT CFF RON 0.022 PF VIN CIN 10 PF * RENT RFBT CSS 4700 pF * RENB COUT RFBB * See equation 1 to calculate values Connection Diagram Exposed Pad Connect to GND 7 6 5 4 3 2 1 VOUT FB SS GND EN RON VIN Figure 2. Top View 7-Lead PFM PIN DESCRIPTIONS Pin Name Description 1 VIN Supply input — Additional external input capacitance is required between this pin and the exposed pad (EP). 2 RON On time resistor — An external resistor from VIN to this pin sets the on-time and frequency of the application. Typical values range from 100k to 700k ohms. 3 EN 4 GND 5 SS Soft-Start — An internal 8 µA current source charges an external capacitor to produce the soft-start function. 6 FB Feedback — Internally connected to the regulation, over-voltage, and short-circuit comparators. The regulation reference point is 0.8V at this input pin. Connect the feedback resistor divider between the output and ground to set the output voltage. 7 VOUT EP EP Enable — Input to the precision enable comparator. Rising threshold is 1.18V. Ground — Reference point for all stated voltages. Must be externally connected to EP. Output Voltage — Output from the internal inductor. Connect the output capacitor between this pin and the EP. Exposed Pad — Internally connected to pin 4. Used to dissipate heat from the package during operation. Must be electrically connected to pin 4 external to the package. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H 3 LMZ14202H SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 Absolute Maximum Ratings www.ti.com (1) (2) VIN, RON to GND -0.3V to 43.5V EN, FB, SS to GND -0.3V to 7V Junction Temperature 150°C Storage Temperature Range -65°C to 150°C ESD Susceptibility (3) ± 2 kV Peak Reflow Case Temperature (30 sec) 245°C For soldering specifications, refer to the following document: www.ti.com/lit/snoa549c (1) (2) (3) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD-22-114. Operating Ratings (1) VIN 6V to 42V EN 0V to 6.5V −40°C to 125°C Operation Junction Temperature (1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 24V, VOUT = 12V, RON = 249kΩ Symbol Parameter Conditions Min Typ Max 1.10 1.18 1.25 (1) (2) (1) Units SYSTEM PARAMETERS Enable Control VEN VEN-HYS EN threshold trip point VEN rising EN threshold hysteresis 90 V mV Soft-Start ISS ISS-DIS SS source current VSS = 0V 8 SS discharge current 10 15 -200 µA µA Current Limit ICL Current limit threshold DC average 2.4 3.2 3.95 A VINUVLO Input UVLO EN pin floating VIN rising 3.75 V VINUVLO-HYST Hysteresis EN pin floating VIN falling 130 mV ON timer minimum pulse width 150 ns OFF timer pulse width 260 ns VIN UVLO ON/OFF Timer tON-MIN tOFF Regulation and Over-Voltage Comparator (1) (2) 4 Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Typical numbers are at 25°C and represent the most likely parametric norm. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H LMZ14202H www.ti.com SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 24V, VOUT = 12V, RON = 249kΩ Symbol VFB VFB VFB-OVP Min Typ Max (1) Units VIN = 24V, VOUT = 12V VSS >+ 0.8V TJ = -40°C to 125°C IOUT = 10mA to 2A 0.782 0.803 0.822 V VIN = 24V, VOUT = 12V VSS >+ 0.8V TJ = 25°C IOUT = 10mA to 2A 0.786 0.803 0.818 V VIN = 36V, VOUT = 24V VSS >+ 0.8V TJ = -40°C to 125°C IOUT = 10mA to 2A 0.780 0.803 0.824 V VIN = 36V, VOUT = 24V VSS >+ 0.8V TJ = 25°C IOUT = 10mA to 2A 0.787 0.803 0.819 V Parameter Conditions In-regulation feedback voltage In-regulation feedback voltage Feedback over-voltage protection threshold (1) (2) 0.92 V IFB Feedback input bias current 5 nA IQ Non Switching Input Current VFB= 0.86V 1 mA ISD Shut Down Quiescent Current VEN= 0V 25 μA Rising 165 °C 15 °C 4 layer Printed Circuit Board, 7.62cm x 7.62cm (3in x 3in) area, 1 oz Copper, No air flow 16 °C/W 4 layer Printed Circuit Board, 6.35cm x 6.35cm (2.5in x 2.5in) area, 1 oz Copper, No air flow 18.4 °C/W No air flow 1.9 °C/W Thermal Characteristics TSD TSD-HYST θJA θJC Thermal Shutdown Thermal Shutdown Hysteresis Junction to Ambient Junction to Case PERFORMANCE PARAMETERS ΔVOUT Output Voltage Ripple VOUT = 5V, CO = 100µF 6.3V X7R ΔVOUT/ΔVIN Line Regulation VIN = 16V to 42V, IOUT= 3A .01 8 % ΔVOUT/ΔIOUT Load Regulation VIN = 24V, IOUT = 0A to 2A 1.5 mV/A η Efficiency VIN = 24V VOUT = 12V IOUT = 1A 93 % η Efficiency VIN = 24V VOUT = 12V IOUT = 2A 92 % Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H mV PP 5 LMZ14202H SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics Unless otherwise specified, the following conditions apply: VIN = 24V; Cin = 10uF X7R Ceramic; CO = 47uF; TAMB = 25°C. 95 2.5 90 85 80 VIN = 8V VIN = 12V VIN = 24V VIN = 36V VIN = 42V 70 0.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 1.5 1.0 0.5 0.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 3. Figure 4. Efficiency VOUT = 12V TAMB = 25°C Power Dissipation VOUT = 12V TAMB = 25°C 100 3.0 95 2.5 90 85 80 VIN = 15V VIN = 24V VIN = 30V VIN = 36V VIN = 42V 75 70 0.0 0.5 1.0 1.5 OUTPUT CURRENT (A) VIN = 15V VIN = 24V VIN = 30V VIN = 36V VIN = 42V 2.0 1.5 1.0 0.5 0.0 0.0 2.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 5. Figure 6. Efficiency VOUT = 15V TAMB = 25°C Power Dissipation VOUT = 15V TAMB = 25°C 100 3.0 95 2.5 90 85 80 75 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 0.0 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 2.0 1.5 1.0 0.5 0.0 70 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 7. 6 VIN = 8V VIN = 12V VIN = 24V VIN = 36V VIN = 42V 0.0 2.0 POWER DISSIPATION (W) EFFICIENCY (%) POWER DISSIPATION (W) 3.0 75 EFFICIENCY (%) Power Dissipation VOUT = 5.0V TAMB = 25°C POWER DISSIPATION (W) EFFICIENCY (%) Efficiency VOUT = 5.0V TAMB = 25°C 100 0.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 8. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H LMZ14202H www.ti.com SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 24V; Cin = 10uF X7R Ceramic; CO = 47uF; TAMB = 25°C. Power Dissipation VOUT = 18V TAMB = 25°C 3.0 95 2.5 POWER DISSIPATION (W) EFFICIENCY (%) Efficiency VOUT = 18V TAMB = 25°C 100 90 85 80 75 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 0.5 1.0 1.5 OUTPUT CURRENT (A) 1.0 0.5 0.0 2.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 10. Efficiency VOUT = 24V TAMB = 25°C Power Dissipation VOUT = 24V TAMB = 25°C 100 3.0 95 2.5 POWER DISSIPATION (W) EFFICIENCY (%) 1.5 Figure 9. 90 85 80 75 VIN = 28V VIN = 30V VIN = 36V VIN = 42V 0.0 VIN = 28V VIN = 30V VIN = 36V VIN = 42V 2.0 1.5 1.0 0.5 0.0 70 0.5 1.0 1.5 OUTPUT CURRENT (A) 0.0 2.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 11. Figure 12. Efficiency VOUT = 30V TAMB = 25°C Power Dissipation VOUT = 30V TAMB = 25°C 100 3.0 95 2.5 POWER DISSIPATION (W) EFFICIENCY (%) 2.0 0.0 70 0.0 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 90 85 80 75 70 0.0 VIN = 34V VIN = 36V VIN = 42V 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 1.5 1.0 0.5 VIN = 34V VIN = 36V VIN = 42V 0.0 2.0 Figure 13. 0.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 14. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H 7 LMZ14202H SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 24V; Cin = 10uF X7R Ceramic; CO = 47uF; TAMB = 25°C. 95 2.5 90 85 80 70 0.0 VIN = 8V VIN = 12V VIN = 24V VIN = 36V VIN = 42V 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 1.5 1.0 0.5 0.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 15. Figure 16. Efficiency VOUT = 12V TAMB = 85°C Power Dissipation VOUT = 12V TAMB = 85°C 100 3.0 95 2.5 90 85 80 VIN = 15V VIN = 24V VIN = 30V VIN = 36V VIN = 42V 75 70 0.0 0.5 1.0 1.5 OUTPUT CURRENT (A) VIN = 15V VIN = 24V VIN = 30V VIN = 36V VIN = 42V 2.0 1.5 1.0 0.5 0.0 0.0 2.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 17. Figure 18. Efficiency VOUT = 15V TAMB = 85°C Power Dissipation VOUT = 15V TAMB = 85°C 100 3.0 95 2.5 90 85 80 75 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 0.0 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 2.0 1.5 1.0 0.5 0.0 70 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 19. 8 VIN = 8V VIN = 12V VIN = 24V VIN = 36V VIN = 42V 0.0 2.0 POWER DISSIPATION (W) EFFICIENCY (%) POWER DISSIPATION (W) 3.0 75 EFFICIENCY (%) Power Dissipation VOUT = 5.0V TAMB = 85°C POWER DISSIPATION (W) EFFICIENCY (%) Efficiency VOUT = 5.0V TAMB = 85°C 100 0.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 20. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H LMZ14202H www.ti.com SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 24V; Cin = 10uF X7R Ceramic; CO = 47uF; TAMB = 25°C. Power Dissipation VOUT = 18V TAMB = 85°C 3.0 95 2.5 POWER DISSIPATION (W) EFFICIENCY (%) Efficiency VOUT = 18V TAMB = 85°C 100 90 85 80 75 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 0.5 1.0 1.5 OUTPUT CURRENT (A) 1.0 0.5 0.0 2.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 22. Efficiency VOUT = 24V TAMB = 85°C Power Dissipation VOUT = 24V TAMB = 85°C 100 3.0 95 2.5 POWER DISSIPATION (W) EFFICIENCY (%) 1.5 Figure 21. 90 85 80 75 VIN = 28V VIN = 30V VIN = 36V VIN = 42V 0.0 VIN = 28V VIN = 30V VIN = 36V VIN = 42V 2.0 1.5 1.0 0.5 0.0 70 0.5 1.0 1.5 OUTPUT CURRENT (A) 0.0 2.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 23. Figure 24. Efficiency VOUT = 30V TAMB = 85°C Power Dissipation VOUT = 30V TAMB = 85°C 100 3.0 95 2.5 POWER DISSIPATION (W) EFFICIENCY (%) 2.0 0.0 70 0.0 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 90 85 80 75 70 0.0 VIN = 34V VIN = 36V VIN = 42V 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 1.5 1.0 0.5 VIN = 34V VIN = 36V VIN = 42V 0.0 2.0 Figure 25. 0.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 26. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H 9 LMZ14202H SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 24V; Cin = 10uF X7R Ceramic; CO = 47uF; TAMB = 25°C. Thermal Derating VOUT = 12V, θJA = 16°C/W 2.0 1.5 1.0 0.5 0.0 -20 Thermal Derating VOUT = 12V, θJA = 20°C/W 2.5 OUTPUT CURRENT (A) OUTPUT CURRENT (A) 2.5 VIN = 15V VIN = 24V VIN = 42V 2.0 1.5 1.0 0.5 0.0 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (°C) -20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (°C) Figure 27. Figure 28. Thermal Derating VOUT = 24V, θJA = 16°C/W Thermal Derating VOUT = 24V, θJA = 20°C/W 2.0 1.5 1.0 0.5 0.0 -20 2.5 OUTPUT CURRENT (A) OUTPUT CURRENT (A) 2.5 VIN = 30V VIN = 36V VIN = 42V VIN = 30V VIN = 36V VIN = 42V 2.0 1.5 1.0 0.5 0.0 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (°C) -20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (°C) Figure 29. Figure 30. Thermal Derating VOUT = 30V, θJA = 16°C/W Thermal Derating VOUT = 30V, θJA = 20°C/W 2.0 1.5 1.0 0.5 0.0 -20 2.5 OUTPUT CURRENT (A) OUTPUT CURRENT (A) 2.5 VIN = 34V VIN = 36V VIN = 42V VIN = 34V VIN = 36V VIN = 42V 2.0 1.5 1.0 0.5 0.0 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (°C) Figure 31. 10 VIN = 15V VIN = 24V VIN = 42V -20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (°C) Figure 32. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H LMZ14202H www.ti.com SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 24V; Cin = 10uF X7R Ceramic; CO = 47uF; TAMB = 25°C. Package Thermal Resistance θJA 4 Layer Printed Circuit Board with 1oz Copper 0LFM (0m/s) air 225LFM (1.14m/s) air 500LFM (2.54m/s) air Evaluation Board Area 35 30 25 20 15 10 5 0 0 10 20 30 40 2 BOARD AREA (cm ) 50 Line and Load Regulation TAMB = 25°C OUTPUT VOLTAGE REGULATION (%) THERMAL RESISTANCE JA(°C/W) 40 60 0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 VIN = 15V VIN = 24V VIN = 30V VIN = 36V VIN = 42V -0.20 0.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Figure 33. Figure 34. Output Ripple VIN = 12V, IOUT = 2A, Ceramic COUT, BW = 200 MHz Output Ripple VIN = 24V, IOUT = 2A, Polymer Electrolytic COUT, BW = 200 MHz VOUT=12V 1 µs/div 100 mV/div Figure 35. Figure 36. Load Transient Response VIN = 24V VOUT = 12V Load Step from 10% to 100% Load Transient Response VIN = 24V VOUT = 12V Load Step from 30% to 100% VOUT=12V 100 mV/Div 1.0 A/Div IOUT 1 ms/Div Figure 37. Figure 38. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H 11 LMZ14202H SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 24V; Cin = 10uF X7R Ceramic; CO = 47uF; TAMB = 25°C. Current Limit vs. Input Voltage VOUT = 5V TAMB = 25°C 3.5 POWER DISSIPATION (W) DC CURRENT LIMIT LEVEL (A) 4.5 4.0 3.5 3.0 Fsw = 250kHz Fsw = 400kHz Fsw = 600kHz 2.5 5 10 15 20 25 30 35 INPUT VOLTAGE (V) 40 2.0 1.5 1.0 0.5 300 400 500 600 700 SWITCHING FREQUENCY (kHz) Figure 39. Figure 40. Current Limit vs. Input Voltage VOUT = 12V TAMB = 25°C Switching Frequency vs. Power Dissipation VOUT = 12V TAMB = 25°C 3.5 POWER DISSIPATION (W) DC CURRENT LIMIT LEVEL (A) 2.5 200 45 4.5 4.0 3.5 3.0 Fsw = 250kHz Fsw = 400kHz Fsw = 600kHz 2.5 3.0 800 VIN = 15V VIN = 24V VIN = 36V VIN = 42V 2.5 2.0 1.5 1.0 0.5 0.0 2.0 5 10 15 20 25 30 35 INPUT VOLTAGE (V) 40 200 45 Figure 42. Current Limit vs. Input Voltage VOUT = 24V TAMB = 25°C Switching Frequency vs. Power Dissipation VOUT = 24V TAMB = 25°C 3.5 POWER DISSIPATION (W) 4.0 3.5 3.0 Fsw = 250kHz Fsw = 400kHz Fsw = 600kHz 2.5 300 400 500 600 700 SWITCHING FREQUENCY (kHz) Figure 41. 4.5 DC CURRENT LIMIT LEVEL (A) VIN = 12V VIN = 24V VIN = 36V VIN = 42V 0.0 2.0 800 3.0 2.5 2.0 1.5 VIN = 30V VIN = 36V VIN = 42V 1.0 0.5 0.0 2.0 30 33 36 39 42 INPUT VOLTAGE (V) 45 Figure 43. 12 3.0 Switching Frequency vs. Power Dissipation VOUT = 5V TAMB = 25°C 200 300 400 500 600 700 SWITCHING FREQUENCY (kHz) 800 Figure 44. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H LMZ14202H www.ti.com SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 24V; Cin = 10uF X7R Ceramic; CO = 47uF; TAMB = 25°C. Startup VIN = 24V IOUT = 2A Radiated EMI of Evaluation Board, VOUT = 12V RADIATED EMISSIONS (dB V/m) 80 VOUT ENABLE Emissions (Evaluation Board) EN 55022 Limit (Class B) 70 60 50 40 30 20 10 0 0 1 ms/Div 5V/Div 200 400 600 800 FREQUENCY (MHz) Figure 45. 1000 Figure 46. Conducted EMI, VOUT = 12V Evaluation Board BOM and 3.3µH 2x10µF LC line filter CONDUCTED EMISSIONS (dB V) 80 70 Emissions CISPR 22 Quasi Peak CISPR 22 Average 60 50 40 30 20 10 0 0.1 1 10 FREQUENCY (MHz) 100 Figure 47. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H 13 LMZ14202H SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 www.ti.com APPLICATION BLOCK DIAGRAM Vin RENT 3 VIN 1 EN Linear reg RENB Cvcc 5 SS CBST Css RON 2 VOUT 7 Timer 15 PH VO Co FB RFBT RFBB 0.47 PF RON CFF 6 CIN Regulator IC Internal Passives GND 4 14 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H LMZ14202H www.ti.com SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 COT CONTROL CIRCUIT OVERVIEW Constant On Time control is based on a comparator and an on-time one shot, with the output voltage feedback compared to an internal 0.8V reference. If the feedback voltage is below the reference, the high-side MOSFET is turned on for a fixed on-time determined by a programming resistor RON. RON is connected to VIN such that ontime is reduced with increasing input supply voltage. Following this on-time, the high-side MOSFET remains off for a minimum of 260 ns. If the voltage on the feedback pin falls below the reference level again the on-time cycle is repeated. Regulation is achieved in this manner. Design Steps for the LMZ14202H Application The LMZ14202H is fully supported by Webench® which offers the following: • • • • Component selection Electrical simulation Thermal simulation Build-it prototype board for a reduction in design time The following list of steps can be used to manually design the LMZ14202H application. • • • • • • • • Select minimum operating VIN with enable divider resistors Program VO with divider resistor selection Program turn-on time with soft-start capacitor selection Select CO Select CIN Set operating frequency with RON Determine module dissipation Layout PCB for required thermal performance ENABLE DIVIDER, RENT AND RENB SELECTION The enable input provides a precise 1.18V reference threshold to allow direct logic drive or connection to a voltage divider from a higher enable voltage such as VIN. The enable input also incorporates 90 mV (typ) of hysteresis resulting in a falling threshold of 1.09V. The maximum recommended voltage into the EN pin is 6.5V. For applications where the midpoint of the enable divider exceeds 6.5V, a small zener can be added to limit this voltage. The function of the RENT and RENB divider shown in the Application Block Diagram is to allow the designer to choose an input voltage below which the circuit will be disabled. This implements the feature of programmable under voltage lockout. This is often used in battery powered systems to prevent deep discharge of the system battery. It is also useful in system designs for sequencing of output rails or to prevent early turn-on of the supply as the main input voltage rail rises at power-up. Applying the enable divider to the main input rail is often done in the case of higher input voltage systems such as 24V AC/DC systems where a lower boundary of operation should be established. In the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the LMZ14202H output rail. The two resistors should be chosen based on the following ratio: RENT / RENB = (VIN-ENABLE/ 1.18V) – 1 (1) The EN pin is internally pulled up to VIN and can be left floating for always-on operation. However, it is good practice to use the enable divider and turn on the regulator when VIN is close to reaching its nominal value. This will guarantee smooth startup and will prevent overloading the input supply. OUTPUT VOLTAGE SELECTION Output voltage is determined by a divider of two resistors connected between VO and ground. The midpoint of the divider is connected to the FB input. The voltage at FB is compared to a 0.8V internal reference. In normal operation an on-time cycle is initiated when the voltage on the FB pin falls below 0.8V. The high-side MOSFET on-time cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8V. As long as the voltage at FB is above 0.8V, on-time cycles will not occur. The regulated output voltage determined by the external divider resistors RFBT and RFBB is: Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H 15 LMZ14202H SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 www.ti.com VO = 0.8V x (1 + RFBT / RFBB) (2) Rearranging terms; the ratio of the feedback resistors for a desired output voltage is: RFBT / RFBB = (VO / 0.8V) - 1 (3) These resistors should be chosen from values in the range of 1 kΩ to 50 kΩ. A feed-forward capacitor is placed in parallel with RFBT to improve load step transient response. Its value is usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for best transient response and minimum output ripple. A table of values for RFBT , RFBB , and RON is included in the simplified applications schematic. SOFT-START CAPACITOR, CSS, SELECTION Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to prevent overshoot. Upon turn-on, after all UVLO conditions have been passed, an internal 8uA current source begins charging the external soft-start capacitor. The soft-start time duration to reach steady state operation is given by the formula: tSS = VREF x CSS / Iss = 0.8V x CSS / 8uA (4) This equation can be rearranged as follows: CSS = tSS x 8 μA / 0.8V (5) Use of a 4700pF capacitor results in 0.5ms soft-start duration. This is a recommended value. Note that high values of CSS capacitance will cause more output voltage droop when a load transient goes across the DCMCCM boundary. Use Equation 18 below to find the DCM-CCM boundary load current for the specific operating condition. If a fast load transient response is desired for steps between DCM and CCM mode the softstart capacitor value should be less than 0.018µF. As the soft-start input exceeds 0.8V the output of the power stage will be in regulation. Note that the following conditions will reset the soft-start capacitor by discharging the SS input to ground with an internal 200 μA current sink: • • • • The enable input being “pulled low” Thermal shutdown condition Over-current fault Internal VINUVLO OUTPUT CAPACITOR, CO, SELECTION None of the required output capacitance is contained within the module. At a minimum, the output capacitor must meet the worst case RMS current rating of 0.5 x ILR P-P, as calculated in Equation 19. Beyond that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum value of 10 μF is generally required. Experimentation will be required if attempting to operate with a minimum value. Low ESR capacitors, such as ceramic and polymer electrolytic capacitors are recommended. CAPACITANCE: Equation 6 provides a good first pass approximation of CO for load transient requirements: CO≥ISTEP x VFB x L x VIN/ (4 x VO x (VIN — VO) x VOUT-TRAN) (6) As an example, for 2A load step, VIN = 24V, VOUT = 12V, VOUT-TRAN = 50mV: CO≥ 2A x 0.8V x 15μH x 24V / (4 x 12V x ( 24V — 12V) x 50mV) CO≥ 20μF ESR: 16 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H LMZ14202H www.ti.com SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 The ESR of the output capacitor affects the output voltage ripple. High ESR will result in larger VOUT peak-topeak ripple voltage. Furthermore, high output voltage ripple caused by excessive ESR can trigger the overvoltage protection monitored at the FB pin. The ESR should be chosen to satisfy the maximum desired VOUT peak-to-peak ripple voltage and to avoid over-voltage protection during normal operation. The following equations can be used: ESRMAX-RIPPLE ≤ VOUT-RIPPLE / ILR P-P where • ILR P-P is calculated using Equation 19 below ESRMAX-OVP < (VFB-OVP - VFB) / (ILR P-P x AFB ) (7) where • AFB is the gain of the feedback network from VOUT to VFB at the switching frequency. (8) As worst case, assume the gain of AFB with the CFF capacitor at the switching frequency is 1. The selected capacitor should have sufficient voltage and RMS current rating. The RMS current through the output capacitor is: I(COUT(RMS)) = ILR P-P / √12 (9) INPUT CAPACITOR, CIN, SELECTION The LMZ14202H module contains an internal 0.47 µF input ceramic capacitor. Additional input capacitance is required external to the module to handle the input ripple current of the application. This input capacitance should be located as close as possible to the module. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. Worst case input ripple current rating is dictated by Equation 10: I(CIN(RMS)) ≊ 1 / 2 x IO x √ (D / 1-D) where • D ≊ VO / VIN (10) (As a point of reference, the worst case ripple current will occur when the module is presented with full load current and when VIN = 2 x VO). Recommended minimum input capacitance is 10uF X7R ceramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. It is also recommended that attention be paid to the voltage and temperature deratings of the capacitor selected. It should be noted that ripple current rating of ceramic capacitors may be missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this rating. If the system design requires a certain maximum value of input ripple voltage ΔVIN to be maintained then Equation 11 may be used. CIN ≥ IO x D x (1–D) / fSW-CCM x ΔVIN (11) If ΔVIN is 1% of VIN for a 24V input to 12V output application this equals 240 mV and fSW = 400 kHz. CIN≥ 2A x 12V/24V x (1– 12V/24V) / (400000 x 0.240 V) CIN≥ 5.2μF Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines. ON TIME, RON, RESISTOR SELECTION Many designs will begin with a desired switching frequency in mind. As seen in the Typical Performance Characteristics section, the best efficiency is achieved in the 300kHz-400kHz switching frequency range. Equation 12 can be used to calculate the RON value. fSW(CCM) ≊ VO / (1.3 x 10-10 x RON) (12) This can be rearranged as RON ≊ VO / (1.3 x 10 -10 x fSW(CCM) (13) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H 17 LMZ14202H SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 www.ti.com The selection of RON and fSW(CCM) must be confined by limitations in the on-time and off-time for the COT Control Circuit Overview section. The on-time of the LMZ14202H timer is determined by the resistor RON and the input voltage VIN. It is calculated as follows: tON = (1.3 x 10-10 x RON) / VIN (14) The inverse relationship of tON and VIN gives a nearly constant switching frequency as VIN is varied. RON should be selected such that the on-time at maximum VIN is greater than 150 ns. The on-timer has a limiter to ensure a minimum of 150 ns for tON. This limits the maximum operating frequency, which is governed by Equation 15: fSW(MAX) = VO / (VIN(MAX) x 150 nsec) (15) This equation can be used to select RON if a certain operating frequency is desired so long as the minimum ontime of 150 ns is observed. The limit for RON can be calculated as follows: RON ≥ VIN(MAX) x 150 nsec / (1.3 x 10 -10) (16) If RON calculated in Equation 13 is less than the minimum value determined in Equation 16 a lower frequency should be selected. Alternatively, VIN(MAX) can also be limited in order to keep the frequency unchanged. Additionally, the minimum off-time of 260 ns (typ) limits the maximum duty ratio. Larger RON (lower FSW) should be selected in any application requiring large duty ratio. Discontinuous Conduction and Continuous Conduction Modes At light load the regulator will operate in discontinuous conduction mode (DCM). With load currents above the critical conduction point, it will operate in continuous conduction mode (CCM). When operating in DCM the switching cycle begins at zero amps inductor current; increases up to a peak value, and then recedes back to zero before the end of the off-time. Note that during the period of time that inductor current is zero, all load current is supplied by the output capacitor. The next on-time period starts when the voltage on the FB pin falls below the internal reference. The switching frequency is lower in DCM and varies more with load current as compared to CCM. Conversion efficiency in DCM is maintained since conduction and switching losses are reduced with the smaller load and lower switching frequency. Operating frequency in DCM can be calculated as follows: fSW(DCM)≊VO x (VIN-1) x 15μH x 1.18 x 1020 x IO / (VIN–VO) x RON2 (17) In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the off-time. The switching frequency remains relatively constant with load current and line voltage variations. The CCM operating frequency can be calculated using Equation 12 above. The approximate formula for determining the DCM/CCM boundary is as follows: IDCB≊VOx (VIN–VO) / ( 2 x 15μH x fSW(CCM) x VIN) (18) The inductor internal to the module is 15μH. This value was chosen as a good balance between low and high input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple current (ILR). ILR can be calculated with: ILR P-P=VO x (VIN- VO) / (15µH x fSW x VIN) where • VIN is the maximum input voltage and fSW is determined from Equation 12. (19) If the output current IO is determined by assuming that IO = IL, the higher and lower peak of ILR can be determined. Be aware that the lower peak of ILR must be positive if CCM operation is required. POWER DISSIPATION AND BOARD THERMAL REQUIREMENTS For a design case of VIN = 24V, VOUT = 12V, IOUT = 2A, TAMB (MAX) = 85°C , and TJUNCTION = 125°C, the device must see a maximum junction-to-ambient thermal resistance of: θJA-MAX < (TJ-MAX - TAMB(MAX)) / PD This θJA-MAX will ensure that the junction temperature of the regulator does not exceed TJ-MAX in the particular application ambient temperature. 18 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H LMZ14202H www.ti.com SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 To calculate the required θJA-MAX we need to get an estimate for the power losses in the IC. The following graph is taken form the Typical Performance Characteristics section and shows the power dissipation of the LMZ14202H for VOUT = 12V at 85°C TAMB. Figure 48. Power Dissipation VOUT = 12V TAMB = 85°C POWER DISSIPATION (W) 3.0 VIN = 15V VIN = 24V VIN = 30V VIN = 36V VIN = 42V 2.5 2.0 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 OUTPUT CURRENT (A) 2.0 Using the 85°C TAMB power dissipation data PD for VIN = 24V and VOUT = 12V is estimated to be 1.8W. The necessary θJA-MAX can now be calculated. θJA-MAX < (125°C - 85°C) / 1.8W θJA-MAX < 22.2°C/W To achieve this thermal resistance the PCB is required to dissipate the heat effectively. The area of the PCB will have a direct effect on the overall junction-to-ambient thermal resistance. In order to estimate the necessary copper area we can refer to the following Package Thermal Resistance graph. This graph is taken from the Typical Performance Characteristics section and shows how the θJA varies with the PCB area. Figure 49. Package Thermal Resistance θJA 4 Layer Printed Circuit Board with 1oz Copper THERMAL RESISTANCE JA(°C/W) 40 0LFM (0m/s) air 225LFM (1.14m/s) air 500LFM (2.54m/s) air Evaluation Board Area 35 30 25 20 15 10 5 0 0 10 20 30 40 2 BOARD AREA (cm ) 50 60 For θJA-MAX< 22.2°C/W and only natural convection (i.e. no air flow), the PCB area will have to be at least 30cm2. This corresponds to a square board with approximately 5.5cm x 5.5cm (2.17in x 2.17in) copper area, 4 layers, and 1oz copper thickness. Higher copper thickness will further improve the overall thermal performance. Note that thermal vias should be placed under the IC package to easily transfer heat from the top layer of the PCB to the inner layers and the bottom layer. For more guidelines and insight on PCB copper area, thermal vias placement, and general thermal design practices please refer to Application Note AN-2020 (http://www.ti.com/lit/an/snva419b/snva419b.pdf). PC BOARD LAYOUT GUIDELINES PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H 19 LMZ14202H SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 www.ti.com VIN LMZ14202H VIN VO VOUT High di/dt Cin1 CO1 GND Loop 2 Loop 1 1. Minimize area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PC board layout. The high current loops that do not overlap have high di/dt content that will cause observable high frequency noise on the output pin if the input capacitor (Cin1) is placed at a distance away from the LMZ14202H. Therefore place CIN1 as close as possible to the LMZ14202H VIN and GND exposed pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor should consist of a localized top side plane that connects to the GND exposed pad (EP). 2. Have a single point ground. The ground connections for the feedback, soft-start, and enable components should be routed to the GND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to EP. 3. Minimize trace length to the FB pin. Both feedback resistors, RFBT and RFBB, and the feed forward capacitor CFF, should be located close to the FB pin. Since the FB node is high impedance, maintain the copper area as small as possible. The traces from RFBT, RFBB, and CFF should be routed away from the body of the LMZ14202H to minimize noise pickup. 4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and provide optimum output accuracy. 5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 x 6 via array with minimum via diameter of 10mils (254 μm) thermal vias spaced 59mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C. Additional Features OUTPUT OVER-VOLTAGE COMPARATOR The voltage at FB is compared to a 0.92V internal reference. If FB rises above 0.92V the on-time is immediately terminated. This condition is known as over-voltage protection (OVP). It can occur if the input voltage is increased very suddenly or if the output load is decreased very suddenly. Once OVP is activated, the top MOSFET on-times will be inhibited until the condition clears. Additionally, the synchronous MOSFET will remain on until inductor current falls to zero. 20 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H LMZ14202H www.ti.com SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 CURRENT LIMIT Current limit detection is carried out during the off-time by monitoring the current in the synchronous MOSFET. Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds ICL the current limit comparator disables the start of the next on-time period. The next switching cycle will occur only if the FB input is less than 0.8V and the inductor current has decreased below ICL. Inductor current is monitored during the period of time the synchronous MOSFET is conducting. So long as inductor current exceeds ICL, further on-time intervals for the top MOSFET will not occur. Switching frequency is lower during current limit due to the longer off-time. It should also be noted that DC current limit varies with duty cycle, switching frequency, and temperature. THERMAL PROTECTION The junction temperature of the LMZ14202H should not be allowed to exceed its maximum ratings. Thermal protection is implemented by an internal Thermal Shutdown circuit which activates at 165 °C (typ) causing the device to enter a low power standby state. In this state the main MOSFET remains off causing VO to fall, and additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for accidental device overheating. When the junction temperature falls back below 145 °C (typ Hyst = 20 °C) the SS pin is released, VO rises smoothly, and normal operation resumes. ZERO COIL CURRENT DETECTION The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which inhibits the synchronous MOSFET when its current reaches zero until the next on-time. This circuit enables the DCM operating mode, which improves efficiency at light loads. PRE-BIASED STARTUP The LMZ14202H will properly start up into a pre-biased output. This is startup situation is common in multiple rail logic applications where current paths may exist between different power rails during the startup sequence. The pre-bias level of the output voltage must be less than the input UVLO set point. This will prevent the output prebias from enabling the regulator through the high side MOSFET body diode. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H 21 LMZ14202H SNVS691D – JANUARY 2011 – REVISED FEBRUARY 2013 www.ti.com REVISION HISTORY Changes from Revision C (February 2013) to Revision D • 22 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 21 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ14202H PACKAGE OPTION ADDENDUM www.ti.com 29-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) LMZ14202HTZ/NOPB ACTIVE PFM NDW 7 250 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 125 LMZ14202 HTZ LMZ14202HTZE/NOPB ACTIVE PFM NDW 7 45 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 125 LMZ14202 HTZ LMZ14202HTZX/NOPB ACTIVE PFM NDW 7 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 125 LMZ14202 HTZ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMZ14202HTZ/NOPB PFM NDW 7 250 330.0 24.4 10.6 14.22 5.0 16.0 24.0 Q2 LMZ14202HTZX/NOPB PFM NDW 7 500 330.0 24.4 10.6 14.22 5.0 16.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMZ14202HTZ/NOPB PFM NDW 7 250 367.0 367.0 45.0 LMZ14202HTZX/NOPB PFM NDW 7 500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA NDW0007A BOTTOM SIDE OF PACKAGE TOP SIDE OF PACKAGE TZA07A (Rev D) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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