Application Report
SNAA058B – July 2008 – Revised May 2013
AN-1850 LME49830TB Ultra-High Fidelity High Power
Amplifier Reference Design
.....................................................................................................................................................
ABSTRACT
This application report discusses the design and use of the LME ultra-high fidelity power amplifier input
stage ICs (drivers).
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Contents
Introduction .................................................................................................................. 3
Overview ..................................................................................................................... 3
Operational Details ......................................................................................................... 4
3.1
Output Stage Power Dissipation ................................................................................. 6
PCB Connections ........................................................................................................... 8
4.1
Input Connections .................................................................................................. 8
4.2
Output Connections ................................................................................................ 8
4.3
Power Supply Connections ....................................................................................... 9
4.4
GND Connection Optimization ................................................................................... 9
4.5
Mute Function ..................................................................................................... 10
4.6
Gain and Frequency Response ................................................................................ 10
Output Stage Biasing ..................................................................................................... 11
5.1
VBE Multiplier ....................................................................................................... 12
5.2
Bias Stability ...................................................................................................... 17
5.3
Biasing Procedure ................................................................................................ 19
Compensation .............................................................................................................. 19
6.1
Single-Pole Compensation ...................................................................................... 19
6.2
Two-Pole Compensation ........................................................................................ 21
Performance Graphs (±60V) ............................................................................................. 22
Board Layer Views ........................................................................................................ 23
Bill of Materials ............................................................................................................. 26
List of Figures
1
Simple Power Amplifier Schematic ....................................................................................... 3
2
Source-Follower Output Stage ............................................................................................ 4
3
LME49830 EF125WT1 FET PCB Amplifier Schematic ................................................................ 5
4
Amplifier Module Test Setup GND Connections ........................................................................ 9
5
Mute Circuit Reference Voltage ......................................................................................... 10
6
Gain And Low Frequency Response
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11
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13
...................................................................................
Output Stage DC Biasing VBE Multiplier Circuit ........................................................................
THD+N Versus Frequency Versus Bias Current ......................................................................
100mA Bias Current Distortion Residual ...............................................................................
100mA Bias Current Output FFT ........................................................................................
250mA Bias Current Distortion Residual ...............................................................................
250mA Bias Current Output FFT ........................................................................................
1A Bias Current Distortion Residual ....................................................................................
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14
1A Bias Current Output FFT ............................................................................................. 17
15
Bias Current Vs. Time
16
Bias Current Vs. Heat Sink Temperature
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24
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Bias Current Change Percent Vs. Heat Sink Temperature ..........................................................
Single-Pole Compensation Slew Rate ..................................................................................
Single-Pole Compensation Power Bandwidth vs Frequency ........................................................
Two-Pole Compensation Connections..................................................................................
PCB Composite View From Top ........................................................................................
PCB Top Silk Screen View ...............................................................................................
PCB Top Layer View ......................................................................................................
PCB Bottom Layer View .................................................................................................
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List of Tables
2
1
Output Power Levels ....................................................................................................... 5
2
Output Stage Maximum Power Dissipation.............................................................................. 6
3
LME49830 Power Dissipation & Heat Sink Information
4
Recommended MOSFET Power Devices .............................................................................. 11
5
Bias Current And Measured THD+N .................................................................................... 13
6
Slew Rates For 100kHz Power Bandwidth............................................................................. 20
7
LME49830 Slew Rate vs Compensation Capacitor ................................................................... 20
8
Compensation Capacitor Required Per Reference Design .......................................................... 20
...............................................................
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Introduction
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1
Introduction
The LME49830 EF125WT1 amplifier PCB module showcases the LME ultra-high fidelity power amplifier
input stage ICs (drivers). The LME49830 is a fully complementary bipolar 200V input stage IC with 56mA
(typical) of output current that has been optimized for audio applications. With 56mA of current drive, the
IC can drive numerous power transistors to achieve high levels of output power.
The LME49830’s ultra-low distortion and low-noise, combined with a user adjustable compensation
scheme results in a tightly controlled, but highly dynamic listening experience. User adjustable
compensation provides for high-frequency distortion minimization and for slew rate and power bandwidth
optimization. The IC’s high performance level, features and user customization make the driver a highly
reliable, unique input stage solution for high power amplifiers.
While the amplifier module provides a convenient way for performance measurement verification, it also
can be used to validate the solution’s sonic performance in the desired test environment. The solution
presented has undergone listening evaluations in a dedicated sound room for verification of sonic
performance.
2
Overview
The LME49830 IC in combination with a properly designed high-current output stage, with adequate
thermal management, can provide output power levels in excess of 1kW. Figure 1 represents a simple
schematic of a typical power amplifier utilizing the LME49830. The LME49830 simplifies power amplifier
design by providing a highly reliable, consistent performing low distortion input stage. With the addition of
an output stage and a simple DC biasing circuit, the end result is a very high fidelity power amplifier. The
LME49830 was designed for output stages using MOSFET devices but may be used with other output
device types as well. The LME49830 can be used with just about any MOSFET desired as a result of the
16V DC bias range for the output stage.
Figure 1. Simple Power Amplifier Schematic
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Operational Details
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With a 200V operating voltage range, an amplifier solution using the LME49830 is mainly limited by the
number of output power stage transistors in conjunction with adequate thermal management to keep the
power transistors operating within their safe operating area (SOA).
The LME49830 can be configured with a number of different output stage topologies, providing for endproduct differentiation and customization. Shown in Figure 2 is the common source-follower output stage
with three transistors paralleled per side.
Figure 2. Source-Follower Output Stage
3
Operational Details
The complete amplifier schematic for the EF125WT1 FET PCB is shown in Figure 3. Important aspects
and explanation of various sections of the circuit will be covered below. The amplifier module is a two
device per side MOSFET output stage driven directly from the LME49830. With only two devices per side
in the output stage there is no need for an additional current gain stage for higher output stage drive
current. The LME49830's drive current of 56mA (typical) provides plenty of drive current for high slew rate
and excellent THD. For higher device count output stages, the LME49830's drive current may not be
sufficient to meet design target specifications.
The LME49830 amplifier module when running on ±60V power supplies is capable providing the output
power levels shown in Table 1, with a 1kHz signal.
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Table 1. Output Power Levels
Load
0.1% THD+N
1% THD+N
10% THD+N
4Ω
335W
350W
430W
8Ω
175W
185W
230W
Figure 3. LME49830 EF125WT1 FET PCB Amplifier Schematic
It is important to note that the LME49830 EF125WT1 FET PCB amplifier module contains no output stage
protection mechanisms. A proper current limit set on the evaluation power supply is the minimum
precaution for safety.
The power supply voltage limitation for the EF125WT1 FET module is based on the Toshiba
2SK1530/2SJ201 MOSFET devices, which have a VDSS of 200V as well as the LME49830 which has an
absolute maximum supply voltage rating of ±100V (200V). Based on this, it is recommended that the
maximum power supply voltage applied to the amplifier module be less than ±80V. To allow for additional
safety margin it is recommended that the maximum power supply voltage is ±75V.
While power supply voltages up to ±75V can be applied to the amplifier module, it is recommended that
caution be applied when driving a load with an impedance less than 8Ω with continuous sinusoidal
signals. Only two output power transistors per side with limited power dissipation capabilities on the
provided heat sink does not allow for continuous total output stage power dissipation levels above 140W
with only convection cooling. The amplifier module’s limiting factor is the output stage power transistor
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Operational Details
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safe operating area (SOA) along with the power dissipation capabilities of the provided heat sink.
Continuous operation at both high supply voltages and into loads less than 8Ω, with sinusoidal signals will
require additional thermal capacity. Utilizing a high air velocity fan will aid in power dissipation, although
this method will still not guarantee SOA violations under high supply voltage and continuous signal driving
situations.
It is recommended that the PCB amplifier module be operated with ±60V, driving an 8Ω resistive load with
sinusoidal signals for standard performance characterization. When operating above ±60V supply rails or
into low impedance loads, care must be taken to keep from exceeding the output power transistor SOA. It
is highly recommended to minimize the time that continuous signals are applied to the amplifier under
extreme operating conditions. Standard audio performance measurements can be obtained at higher
supply voltages with time for the heat sink and devices to cool in between measurements.
The LME49830 EF125WT1 FET PCB amplifier module is intended to be used for performance verification
and critical listening evaluations. The PCB module indicates the high level of performance that can be
achieved from minimal external components, while still providing significant user design flexibility for endproduct differentiation. The PCB module is not intended to be used for long-term temperature and
reliability testing or significant high-power analysis due to limited thermal capabilities.
For continual high-power driving analysis, long-term temperature and reliability testing, it is recommended
that the amplifier be designed with adequate thermal management for the operating conditions.
3.1
Output Stage Power Dissipation
The output stage’s worst-case maximum power dissipation for purely resistive loads can be determined by
the following equation.
2&:#/2 ;I=T =
:8%% ;2
:9;
::2è;2 × 4. ;
where
•
VCC is the total supply voltage
(1)
For ±75V calculations VCC used in the equation would be 150V.
Table 2 represents the output stage’s maximum power dissipation for stated power supply voltages and
purely resistive loads.
Table 2. Output Stage Maximum Power Dissipation
Output Stage Maximum Power Dissipation
Load
VCC = ±60V
VCC = ±75V
RL = 8Ω
91W
142W
RL = 4Ω
182W
285W
With two power transistors per side on the LME49830 EF125WT1 FET PCB amplifier module, each
transistor will dissipate an average of 1/4th of the total output stage power dissipation. It is easy to see
that each power transistor would need to dissipate an average of 71W when driving a sine-wave
continuously into a 4Ω resistive load with a ±75V power supply. Each output device is rated for 150W of
power dissipation at a case temperature of 25°C. The power dissipation of each device must be de-rated
linearly based on case temperature. At a case temperature of 75°C the power dissipation rating for each
device is down to 90W, based on the device datasheets. Instantaneous power dissipation when driving
reactive loads will be even greater and may exceed the transistor’s safe operating area (SOA).
The heat sink used for the amplifier module is a 4 inch extrusion from Aavid Thermalloy, part number
65605 with a rating of 0.62°C/W. Adding a fan on the heat sink can greatly reduce the thermal resistance
depending on the air flow rate of the fan. More information and thermal modeling for the amplifier heat
sink can be found on Aavid Thermalloy's website.
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Determining the maximum power dissipation while de-rating the output devices base on case temperature
with the provided heat sink can be determined by mathematical derivation. The power dissipation of the
output devices are de-rated linearly with case temperature. The general formula for a line is y = mx + b.
For both output devices, 2SJ201 and 2SK1530, the thermal properties are the same. The power
dissipation de-rating graph end points are set by the power dissipation rating at a case temperature (TC) of
25°C and the maximum channel temperature, which is at 0W power dissipation. These specifications are
150W and 150°C respectively. Two points on the line are know allowing for the solution to the general
formula resulting in Equation 1.
PD(IC) = -1.2W/°C * TC + 180W
(W)
(2)
To determine the case temperature from the device power dissipation the equation is given in Equation 2.
TC = -0.83°C/W * PD(IC) + 150°C
(°C)
(3)
Inspection of the formula above reveals that the junction-to-case thermal resistance, θJC, of the device is
the absolute value of the slope of the curve in °C/W which is 0.83°C/W.
To determine the maximum device power dissipation while de-rating for increase device case temperature
with a given heat sink and ambient temperature a second equation for case temperature can be
determined resulting in:
Device Case Temperature (°C) = Heat Sink Temp (°C) + [Device Power Dissipation (W) * Case Thermal
Resistance (°C/W)]
TC (°C) = THS (°C) + [PD(IC) (W) * θCS (°C/W)]
(4)
The heat sink temperature is the total power dissipation multiplied by it's thermal resistance plus the
ambient temperature:
THS (°C) = [PD(TOTAL) (W) * θSA (°C/W)] + TA
(°C)
(5)
For any number of output devices, PD(TOTAL) = Number of Output Devices * PD(IC)
above gives Equation 3.
TC = (PD(TOTAL) * θSA) + TA + (PD(IC) * θCS)
(W). Combining the
(°C)
(6)
Setting Equation 2 equal to equation 3 gives:
-0.83°C/W * PD(IC) + 150°C = (PD(TOTAL) * θSA) + TA + (PD(IC) * θCS)
(7)
Solving for PD(IC) with four output devices results in Equation 4.
PD(IC) = (150°C - TA) / (4 * θSA + θCS + θJC)
(W)
(8)
Given:
TA = 25°C
θCS = 0.25°C/W, flat, thermal greased surface.
θSA = 0.62°C/W, rating of provided heat sink.
θJC = 0.83°C/W = (TJ(MAX) - TA) / (PD(MAX) at TA).
Results in PD(IC) = 35.1W maximum average power dissipation per device de-rating for case temperature
rise with the provided heat sink at an ambient temperature of 25°C. The total average output stage power
dissipation is 140.4W. Under these conditions each device's channel temperature will be 150°C, each
device case temperature will be 120.9°C, and the heat sink will be 112.1°C.
With some additional substitutions and inspection gives Equation 5 as the very general version of
Equation 4.
PD(IC) = (TJ(MAX) - TA) / {# of Devices * θSA + θCS + [(TJ(MAX) - TA) / (PD(MAX) at TA)]}
(W)
(9)
The above calculations are for continuous average power dissipation with sine waves. Music and other
program material will have average power dissipation levels lower than a sine wave reducing the heat sink
and device temperatures.
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PCB Connections
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LME49830 Power DIssipation
The LME49830 die is contained in a TO-247 package with a junction-to-ambient thermal resistance, θJA, of
73°C/W and a junction-to-case thermal resistance, θJC, of 4°C/W. The TO-247 package is an non-isolated
package and any attached heat sink will be at the same potential as the negative supply rail.
The LME49830 integrates a complete power amplifier input stage and has an output current drive
capability of 56mA. The LME49830 is intended to drive MOSFET transistors in the output stage providing
a high-impedance load to the LME49830.
Shown in Table 3 are maximum power dissipation levels and required minimum heat sink thermal
resistances for the stated power supply voltages to keep the LME49830 die temperature below 150°C.
The calculations use a 50°C ambient, a LME49830 θJC of 4°C/W, plus 0.5°C/W additional thermal
resistance from case-to-sink (θCS).
Table 3. LME49830 Power Dissipation & Heat Sink Information
LME49830
Power Dissipation & Heat Sink Thermal Resistances
LME49830
VCC = ±60V
ICCQ(max) = 25mA
3W
VCC = ±75V
3.75W
θSA
< 28.8°C/W
< 22°C/W
The heat sink used on the EF125WT1 FET amplifier module is from Aavid Thermalloy, part number
530101B00150, with a thermal resistance of 6.3°C/W. As shown in the equation below, even at ±100V
rails, the heat sink is sufficient.
θSA = [(TJ(MAX) - TA) - PD(MAX)(θJC - θCS)] / PD(MAX) = [(150°C - 50°C) - 5W(4°C/W + 0.5°C/W)] / 5W ≤ 15.5°C/W
(10)
This heat sink used for the LME49830 was selected intentionally for ease of IC mounting, thermal
robustness, and mechanical stability. It is recommended that a separate heat sink from the output stage
heat sink be used for the LME49830 to maintain a low operating die temperature and minimize thermal
interaction.
4
PCB Connections
4.1
Input Connections
An analog input signal is applied to the LME49830 EF125WT1 FET PCB through either the two pin
header, J2 or through the standard RCA input connector, J4. For optimum performance a shielded twisted
pair cable should be used between the signal source and PCB amplifier module with the shield terminated
only at the signal source.
The input is DC coupled, unbalanced and terminated in a 6.8kΩ resistor. The input termination, RT, and
the accompanying gain-setting feedback resistor, RF, can be changed to a higher value such as 10kΩ or
47kΩ, resulting in a slightly higher THD+N specification due to added resistor thermal noise. RIN and RI
should also be adjusted to maintain the same gain setting. An input high-frequency roll-off filter capacitor
limiting high-frequency amplification, CT, is in parallel with RT. The combination of these two values set the
pole location to 130kHz.
The input sensitivity for this amplifier is 1.37V, resulting in an output power of 175W at 0.1% THD+N into
8Ω running off of ±60V power supply rails.
4.2
Output Connections
The output is connected through the two pin header, J3. The intended impedance for this amplifier is 8Ω or
4Ω, running off of ±60V power supply rails. While the PCB amplifier module is capable of running off of
supply rails up to ±100V, the main limitation is the safe operating area of the output stage power
transistors. Please refer to the Operational Details section for limitations and recommendations.
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An RC output snubber network has been provided on the PCB acting as a high-frequency load. A 0.1µF
capacitor, CSN1 is in series with a 10Ω resistor, RSN1, which has a 3 watt rating at the output. The RC
snubber is not needed to provide any snubbing of high-frequency instabilities on the output waveform,
generally created in the quasi-saturation region when close to clipping. However, output snubbers are
commonly employed to provide a load impedance to the amplifier at high frequencies.
4.3
Power Supply Connections
The power supply to the amplifier module is applied to connector J1. This connector powers both the
output stage power transistors and the LME49830. Operating voltages from ±20V to ±100V may be
applied to the amplifier module. Please refer to the Operational Details section for limitations and
precautions when operating at elevated supply voltages.
The power supply cabling to the amplifier PCB should have sufficient current handling capability for the
desired amplifier output power. It is recommended that 18 gauge stranded wire be used to connect the
low-impedance power supply to the PCB, keeping connections as short as possible.
4.4
GND Connection Optimization
Shown in Figure 4, is a detailed diagram showing optimum ground connections with two options for the
clean signal GND connection. It is important to note that a separate ground connection must be made
from the signal generator GND to the power supply star GND, providing a reference between the input
and output. Only one option in Figure 4 should be used for the clean GND. This is because there is no
electrical ground connection between the input stage and the output stage power supply bypass
capacitors on the PCB amplifier module. This was done intentionally to eliminate any interaction of ground
currents between the input and output stages.
Figure 4. Amplifier Module Test Setup GND Connections
If the signal source is not grounded back to the power supply star point, the output will float up, drawing a
large amount of current from the positive power supply. Therefore, it is important that the PCB’s low-level
clean signal ground is referenced back to the star ground from either a connection at the Audio Precision
or from analog ground, J10 on the PCB, but only one connection typically gives the best THD+N
performance.
Also note that there is no output load ground return connection on the PCB. This was also done
intentionally to ensure that the high-current output ground return current is tied back at the star ground
point.
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In order to obtain the lowest level distortion measurements, it is important to make an oscilloscope chassis
ground connection to the power supply star ground point while NOT using the scope probe ground clip.
Connecting the scope probe ground clip to AGND, while probing the output stage, may significantly
increase distortion.
Due to the physical size limitation of providing large valued reservoir capacitors on the PCB, it is expected
that the user provide a low-inductance connection to either a low impedance power supply or bulk
capacitance.
In order to minimize amplifier distortion in a lab environment, it is recommended to provide high-valued
reservoir capacitors between the lab power supply and the PCB amplifier module. It is also recommended
to keep connections between the reservoir capacitors and the amplifier module as short as possible.
39,000µF of reservoir capacitance per supply rail was used for bench testing to obtain the performance
indicated in this document.
4.5
Mute Function
A reference voltage is used for the mute circuit in the EF125WT1 FET amplifier module, as shown in
Figure 5. This reference voltage allows varying power supply voltages to be applied to the LME49830
without continually adjusting the mute resistance. The mute current is set to 160μA using the on-board
(+12V) mute voltage. J11 and J12 allow for an external mute voltage of 2.6V to 5V to be used or the user
can adjust the value of the RM2 mute resistor for any desired voltage.
Figure 5. Mute Circuit Reference Voltage
Detailed design information for proper mute circuit operation and reference voltage set up can be found in
the LME49830 datasheet. Also shown in the datasheet is the excellent level of mute attenuation of -120dB
for audio signals. The LME49830 mute function has a smooth turn-on/off transition so that clicks and pops
are minimized. Adding a capacitor to the MUTE pin can totally eliminate any clicks and pops that may
occur with the trade-off being a delay when changing modes. A 47μF Mute capacitor is supplied on the
EF125WT1 FET PCB for a virtually silent mode change with minimal delay.
4.6
Gain and Frequency Response
The amplifier module is configured as non-inverting mode. The gain is set by:
AV = 1 + RF1 / RI
(V/V)
(11)
The gain is set to 28.3V/V (29dB) with RF1 set to 6.8kΩ and RI set to 249Ω. The low frequency response is
set by the combination of CI1 and RI by the equation:
B=
10
1
:*V;
:2è × %+1 × 4+ ;
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The low frequency -3dB roll-off point is 2.9Hz. Additionally, there are component footprints for additional
capacitors in parallel with CI1 (CI2) and RI (CI3) as shown in Figure 6.
Figure 6. Gain And Low Frequency Response
Experimentation with high quality film capacitors in these locations may result in additional sonic
improvements. Such investigation is not covered in this document.
5
Output Stage Biasing
The LME49830 is a robust, consistently high-performing amplifier input stage that eliminates numerous
discrete input stage design issues. Intricate inter-stage design dependencies that commonly affect
optimum distortion performance are no longer a problem for discrete designers, ensuring that new
amplifier designs get to market faster and more reliably.
One of the key benefits of designing with the LME49830 is the ability to select a preferred output stage
topology and power devices. This simple, yet flexible input stage solution makes it easy to combine a
preferred output topology and achieve ultra high-fidelity performance with an integrated form-factor.
System designers can continue to differentiate their power amplifier solutions from their competitors, by
utilizing their time-developed output stage intellectual property. The LME49830 also provides an
integration factor that increases the number of channels per chassis area, while maintaining an ultra highfidelity level never before obtained from an integrated circuit.
With the benefits and flexibility that this solution provides, there is a little complexity and some variability in
setting the output stage’s DC bias voltage. The DC bias voltage, or mode of operation - Class A, B, or
A/B, is set by the designer and is partially dependent upon the topology and the output power device
selected. Different MOSFET devices have significantly varying threshold voltages. There are other
topology configurations but other topologies are beyond the scope of this document.
Besides the DC voltage bias setting, there is a bias circuit difference depending upon whether BJTs or
MOSFETs are used as the power delivery device. BJTs are subject to thermal runaway and therefore
require a thermally compensated bias circuit. If MOSFETs are selected as the power device, there may
not be a need for a thermally compensated bias circuit depending on the specific MOSFET devices.
Shown below in Table 4 is a list of recommended MOSFETs that have been evaluated with the
LME49830. This list of parts was not meant to be an exhaustive list, but rather some of the more common
power devices that are currently used in audio power amplifiers. For more information regarding MOSFET
driving issues and recommendations, please refer to AN-1645 LM4702 Driving a MOSFET Output Stage
SNAA045.
Table 4. Recommended MOSFET Power Devices
(1)
Manufacturer
NFET
PFET
Toshiba
2SK1530
2SJ201
International Rectifier
IRFP240
IRFP9240
Renesas (1)
2SK1058
2SJ162
Renesas devices have a different pin out compared to the Toshiba and IR devices (Source and Drain pins reversed) requiring a
different PCB
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Output Stage Biasing
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The LME49830 has a maximum DC bias voltage of 16V for use with just about any MOSFET device. The
high output drive current from the LME49830 makes it ideal for very high power amplifier applications.
5.1
VBE Multiplier
The LME49830’s BIASP and BIASM pins are available to create the DC bias of the output stage.
Depending on the device characteristics and design goals, a thermally compensated circuit may be
needed in order to have stable bias at the desired current across temperature. A non-compensated bias
circuit would consist of a resistor or potentiometer and one or two capacitors between the BIAS pins of the
LME49830. The EF125WT1 FET PCB uses a thermally compensated VBE multiplier for the bias circuit with
the Toshiba 2SK1530/2SJ201 devices in the output stage.
The VBE multiplier’s transistor, which needs to be mounted directly next to one of the power transistors on
the heat sink, will sense the output device's temperature with some temperature gradient through the
common heat sink. With a correctly designed VBE multiplier circuit the bias current of the output stage will
remain relatively stable over the device temperature operating range.
The VBE multiplier circuit created by QVBE1 with associated resistors and capacitors is shown in Figure 7.
The output stage bias can initially be adjusted through potentiometer, RP1 in order to optimize for lowest
crossover distortion, desired sound quality or mode of operation – Class A, B, or AB.
Figure 7. Output Stage DC Biasing VBE Multiplier Circuit
The DC bias voltage can be measured by connecting a voltmeter between pins 1 and 2 of J9. The DC bias
voltage is measured from gate-to-gate of the output stage. When RP1 is set at its minimum, the total output
stage bias current will be approximately 500mA. When set at its maximum, the total output stage bias
current will be approximately 175mA. The bias current setting of the EF125WT1 FET module before
leaving the factory, and for all performance data, is approximately 225mA. This equates to approximately
112mA per power transistor of power stage quiescent current (~250mA from each supply rail at ±60V).
Changing the value of RB2 to 620Ω will change the bias range to approximately 115mA to 325mA.
It should be noted that the bias adjustment potentiometer, RP1, is available for your convenience in
analyzing the performance effects of output stage bias adjustment. The potentiometer can be replaced in
a final design with a simple resistor once the desired DC biasing voltage has been selected.
Please also note that the VBE Multiplier terminals are very sensitive to loading, so when obtaining any
performance measurements, be sure that the multi-meter or scope probe has been removed from DC Bias
Monitoring header, J9.
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The QVBE1 thermal properties are not an exact match to the MOSFET output device thermal properties. An
additional, temperature independent bias resistor, RB3, is used to adjust the bias voltage to more closely
match the output devices for stable bias current over temperature. This resistor changes the slope of the
bias voltage vs. temperature curve by reducing the effect of the VBE voltage of QVBE1.
Shown in the equation below is the relationship between the voltage setting resistors and the VBE
multiplier’s output voltage, VCE.
VBIAS = (RB3 * 2mA) + VBE [1 + RB2 / (RB1 + RP1)]
(13)
For a Class AB amplifier design, bias current is chosen such that crossover distortion is minimized while
also keeping quiescent power dissipation low. Higher bias current reduces harmonic distortion levels at
the cost of increased power dissipation. At some point there is little reduction with increased bias current
and resulting power dissipation. A tradeoff in the bias current level must be made between THD
performance and power dissipation.
MOSFET output stages typically need higher bias current than BJT output stages for good performance in
a Class AB amplifier design. What amount of bias current each solution’s output stage will require
depends completely on the user’s specific tastes and/or target specifications. Shown in Table 5 are
THD+N measurements with a 1kHz signal at 10W into 8Ω load with a 22kHz measurement bandwidth at
different total supply current settings. The LM49830 current is approximately 25mA so the output stage
bias current is equal to the total supply current minus 25mA.
Table 5. Bias Current And Measured THD+N
Supply Current per Supply
1kHz THD+N at 10W/8Ω, 22kHz BW
50mA
0.00364%
100mA
0.00176%
150mA
0.00120%
200mA
0.00089%
250mA
0.00078%
300mA
0.00070%
500mA
0.00067%
1A
0.00067%
Table 5 indicates that the a range of 200mA to 300mA of supply current per power supply produces low
magnitude harmonics and manageable power dissipation.
Different bias current levels are shown in the graphs and oscilloscope photos below. For each graph the
output power level is 10W into an 8Ω resistive load with 1kHz signal. Each oscilloscope photo shows the
input and output signal plus the time domain distortion residual. The measurement equipment is set to
notch out the fundamental frequency of the test signal. The fundamental is reduced by more than -110dB
relative to 0dB. 0dB is set equal to the voltage for 10W into 8Ω. The graphs show how an insufficient bias
current results in THD that is dominated by crossover distortion. Under bias is also indicated by the high
level and number of harmonics in the FFT graphs.
THD+N curves over frequency representing the level of crossover distortion associated with varying output
stage bias currents are shown in Figure 8. The output power level is 10W into an 8Ω load with an 80kHz
measurement bandwidth for all plots.
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Figure 8. THD+N Versus Frequency Versus Bias Current
Figure 9. 100mA Bias Current Distortion Residual
An under biased output stage is clearly exhibited by sharp, narrow glitches on the distortion residual at the
zero crossing point of the output voltage.
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Figure 10. 100mA Bias Current Output FFT
The under biased time domain distortion residual is represented above by an FFT that exhibits high odd
harmonic distortion over a large number of harmonics. The odd harmonics increase significantly from an
optimally biased FFT, while the even order harmonics remain relatively unchanged.
Figure 11. 250mA Bias Current Distortion Residual
A correctly biased output stage shows a very flat distortion residual except for the zero crossing point
where very small glitches can be observed.
Notice that while the distortion residual at the crossover region is quite small, the overall distortion of the
amplifier with this level of residual is 0.00078% THD+N.
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Figure 12. 250mA Bias Current Output FFT
A correctly biased time domain distortion residual is represented above by an FFT that exhibits fairly
evenly balanced amplitudes of even and odd harmonics as they decrease over frequency. Most of the
distortion products are below the fundamental or test signal of 1kHz.
Figure 13. 1A Bias Current Distortion Residual
A high bias (Class A) output stage shows no crossover distortion and a very flat time domain distortion
residual.
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Figure 14. 1A Bias Current Output FFT
A class A bias level shows very low harmonics in number and amplitude. The tradeoff is high power
dissipation and low efficiency.
5.2
Bias Stability
The Total Quiescent Current versus Time graph (Figure 15) was created by running the output stage at
40W into an 8Ω resistive load until steady state device case and heat sink temperature are reached. The
input signal is turned off (Time = 0) and the bias current recorded over time. It should be noted that the
graph units are not linear as indicated. Bias current is measured at 10 second intervals for the first two
minutes after the input signal was turned off then at 30 second intervals up to five minutes. One final
measurement is taken at 10 minutes. The time steps are one reason for the different slopes on the time
curve. There are two plots on the graph, one indicating the quiescent bias at a heat sink temperature of
35°C and the other indicating the bias over time after producing 40W of output power. There are several
factors that affect the data such as θJC of the package and heat sink size which contribute to thermal
delay.
Figure 15. Bias Current Vs. Time
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It is not possible to measure the exact instantaneous channel temperature of discrete devices. There is a
temperature gradient from the channel or junction of the output device to the heat sink. An additional
temperature gradient exist along the heat sink to the QVBE1 transistor and the thermal resistances of the
QVBE1 transistor case. When the output devices are producing power (and dissipating more power than
quiescent conditions) the temperature gradient from the channel of the output devices to the junction of
the QVBE1 transistor is greater than under quiescent conditions. The thermal resistance is relatively
constant but as the power dissipation increases the temperature gradient linearly increases. With the
channel temperature higher than the bias voltage setting, the output device current is higher. The current
will reduce down to quiescent levels as the channel cools and the temperature gradient from output device
channel to QVBE1 junction is equal to quiescent steady state conditions. The graph in Figure 15 shows the
phenomenon as the total current is higher when the input signal is first turned off and then returns down to
the steady state bias levels by 10 minutes. It should be noted that within 40 seconds the bias current has
returned to within ~4mA of the steady state bias current. With a different heat sink and device mounting
placement the response will be different.
Figure 16 shows the bias current as a function of heat sink temperature. The bias current is set when the
heat sink reaches 30°C and all the thermal gradients are established at a steady state mode. Using
different values for RB1 and RB3 with RB2 set to 750Ω shows how the thermal compensation can be
increased (over compensated) for reduced current at higher heat sink temperatures. The data for
Figure 16 Figure 17 are taken as the heat sink temperature increases under quiescent conditions (no
signal) up to 50°C. For the higher heat sink temperatures, the heat sink is heated to 87°C by driving a load
then the current recorded as the heat sink cools. Because of the larger temperature gradients when
driving a signal the data is collected starting at 70°C when the temperature gradients are near steady
state quiescent conditions. To remove differences in bias settings, the bias currents are normalized to
250mA.
Figure 16. Bias Current Vs. Heat Sink Temperature
Figure 17 shows how the bias current changes as a percent verses heat sink temperature. The percent
change uses the bias current at a heat sink temperature of 30°C for a baseline.
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Figure 17. Bias Current Change Percent Vs. Heat Sink Temperature
Based on the data above the bias resistors are set to RB1 = 392Ω, RB2 = 750Ω, and RB3 = 1.10kΩ.
5.3
Biasing Procedure
Where to set the bias current of the output stage is entirely up to the designer, essentially one of the
features of the solution. It is however, important to set up the biasing of the output stage after being
warmed up a while,
By allowing the amplifier to first warm up, the distortion is optimized at the temperature that the amplifier
will normally be operated. The amplifier will then be operating at its optimum bias point with reduced
distortion under normal operating temperature conditions.
Set the DC bias voltage to your preference of distortion level once the amplifier has warmed up to a
temperature indicative of normal operation. It is common to evaluate the distortion residual in the time
domain and/or the residual’s harmonics in the frequency domain when optimizing the DC bias.
Additionally, it is common to evaluate the DC bias setting for higher frequencies where crossover
distortion is easily recognized above the measurement unit’s noise floor. Frequencies of 3kHz and 5kHz
generally allow for significant harmonics to be present even when using a 30kHz measurement-unit lowpass filter.
The goal is to determine the desired potentiometer setting (or eventually a fixed resistance) that will be
required for the end-design. This is accomplished by optimizing the distortion residuals from a
measurement perspective or by optimizing the desired sound quality from a listening perspective.
Removing the amplifier’s input signal allows for measurement of the DC bias voltage and the quiescent
current running through each leg of power transistors. Simple DC voltage measurement across the source
degeneration resistors provides each leg’s quiescent current.
Please note that the VBE multiplier terminals are very sensitive to loading, so when obtaining any
performance measurements, be sure that the multi-meter or scope probe has been removed from DC Bias
Monitoring header, J9.
6
Compensation
6.1
Single-Pole Compensation
The slew rate specification of an amplifier defines its “speed” by establishing an upper limit of how fast its
output can respond to input signal transient changes. The amplifier’s slew rate is defined by the equation
below.
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Compensation
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One of the features of the LME49830 is the ability to set the amplifier’s slew rate and power bandwidth
through the selection of the external compensation capacitor value. Lowering the value of the
compensation capacitor increases the amplifier’s slew rate and hence its power bandwidth.
Slew Rate = ΔV/Δt = 2πfMAXVOpk
(14)
The amplifier’s power bandwidth is also determined through this equation and can be related to the
amplifier’s slew rate as shown below.
fPBW = Slew Rate/2πVOpk
(15)
The power bandwidth equation indicates that higher output power amplifiers will require larger slew rates
to maintain a constant power bandwidth. Shown in Table 6 are the required amplifier slew rates for a
100kHz power bandwidth for different output power levels.
Table 6. Slew Rates For 100kHz Power Bandwidth
Output Power (W)
(RL = 8Ω)
VO(PEAK) (V)
Slew Rate (μs)
(fBW = 100kHz)
125
44.7
28
250
63.2
40
500
89.4
56
The maximum slew rate for an amplifier will be dependent upon the value of the compensation capacitor,
in conjunction with the maximum tail current of the input differential transistor pair.
Slew Rate = dV/dt = IMAX / CCOMP
(16)
The LME49830 has a maximum input differential pair tail current of 550µA, so corresponding slew rates
for compensation capacitor values are shown in Table 7.
Table 7. LME49830 Slew Rate vs Compensation Capacitor
Compensation
Capacitor, CCOMP (pF)
Slew Rate
(V/µs)
5
110
10
55
12
46
15
37
18
31
20
27
25
22
30
19
60
9
100
5.5
Since slew rate requirements are different depending upon desired power bandwidth and output power
level, we can calculate the needed compensation capacitor for a given design based on the equation
below.
%%1/2 =
+6#+.
k2è × B × 81LG o
(17)
Shown in Table 8 are appropriate compensation capacitor values for 100kHz power bandwidths at the
stated amplifier output power levels.
Table 8. Compensation Capacitor Required Per Reference Design
20
Reference Design (8Ω)
Compensation Capacitor, CCOMP (pF)
Slew Rate (V/µs)
Power Bandwidth (kHz)
125W
20
28
100
250W
12
40
100
450W
10
53
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Figure 18 represents a 24V/µs slew rate from a 20pF compensation capacitor. This value is a tad shy of
the estimated 27V/µs, however, taking into account the tolerances of the compensation capacitor (±5%)
and the IC’s tail current, a 24V/µs slew rate is a realistic value.
Figure 18. Single-Pole Compensation Slew Rate
The power bandwidth for the power amplifier at 150W into 8Ω when using a 20pF compensation capacitor
is 10Hz - 90kHz (±0.5dB) and 10Hz - 130kHz (±3dB) as shown in Figure 19 below. The snubber is
removed before taking the graph with the CT capacitor still in place. The slew rate limitation of 24V/µs
dominates the frequency response.
Figure 19. Single-Pole Compensation Power Bandwidth vs Frequency
6.2
Two-Pole Compensation
In addition to single-pole compensation, there are component placeholders on the EF125WT1 FET PCB
amplifier module for a two-pole compensation scheme as shown in Figure 20. The addition of passive
components RC1 and CC2 create a pole at the frequency stated by the equation below.
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Performance Graphs (±60V)
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1
B22 =
:2è × %%2 × 4%1 ;
=
1
= 414G*V
:2è × 62L( × 6.2G3;
(18)
The two-pole compensation scheme allows for increased loop gain at higher frequencies, resulting in
increased slew rate, dynamics and reduced high-frequency distortion. Experimentation with these
components will show the benefit of reduced distortion at higher frequencies, but care must be taken to
not extend the pole out too far or instabilities may result.
The PCB comes from the factory with RC2 (0Ω) installed for a single-pole compensation scheme and must
be removed in order for CC2 to be effective in the circuit. Mica capacitors from Cornell Dubilier are used for
frequency compensation. Typically, the second compensation capacitor is chosen to be between two and
10 times the value of CC1. A value five times CC1 is a safe starting point. The resistance value is then
selected based on the location of the desired pole. Recommended starting values are 12pF for CC2 and
5.1kΩ for RC1.
Figure 20. Two-Pole Compensation Connections
Not only is there a reduction in higher frequency distortion, there is also a power bandwidth benefit from
using 2-pole compensation as a result of increase slew rate.
7
Performance Graphs (±60V)
The following pages contain standard audio performance graphs of the amplifier module, running off ±60V
power supply rails driving either an 8Ω or 4Ω load. These performance graphs represent the high
performance capabilities of the solution.
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8
Board Layer Views
Figure 21. PCB Composite View From Top
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Figure 22. PCB Top Silk Screen View
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Figure 23. PCB Top Layer View
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Bill of Materials
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Figure 24. PCB Bottom Layer View
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Bill of Materials
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Reference
Value
Tolerance
Description
Manufacturer
Part Number
CS1, CS2, CS3,
CS4, CS10, CS11,
CS9, CSN1
0.1µF
10%
250V, metalized
polyester film,
7.5mm lead spacing
Panasonic
ECQ-E2104KF
CS7, CS8
470µF
20%
100V, radial
electrolytic, 7.5mm
lead spacing
Panasonic
EEU-FC2A471
CC1
20pF
5%
500V multilayer
mica, 3.6mm lead
spacing
CDE Cornell Dubilier
CD15ED200J03
CB1
30pF
5%
500V multilayer
mica, 3.6mm lead
spacing
CDE Cornell Dubilier
CD15ED300J03
CB2, CM
47µF
20%
16V, radial
electrolytic, 2mm
lead spacing
Panasonic
EEU-FC1C470
CI1
220µF
20%
35V radial
electrolytic, 3.5mm
lead spacing
Panasonic
EEU-FC1V221L
CT
180pF
10%
Polyester film, 5mm
lead spacing
Panasonic
ECQ-B1H181KF
CC2, CI2, CI3
Not Used
D1
12V
5%
500mW Zener
Diode, DO-35
Fairchild
Semiconductor
1N5242BTR
DG1, DG2, DG3,
DG4, DG5, DG6,
DG7, DG8
10V
5%
1W Zener diode,
DO-41
Fairchild
Semiconductor
1N4740A
U1
200V
Complementary
MOSFET power
amplifier input stage
TI
LME49830
QVBE1
80V, 1.5A
NPN transistor, TO126
Fairchild
Semiconductor
BD13916STU
Q1, Q3
200V, 12A
N-Channel
MOSFET, 150W,
TO-3PL (2-21F1B)
Toshiba
2SK1530-YF
Q2, Q4
200V, 12A
P-Channel
MOSFET, 150W,
TO-3PL(2-21F1B)
Toshiba
2SJ201-YF
RSN1
10Ω
5%
3 Watt metail oxide,
axial through hole
Vishay/BCcompone
nts
NFR0300001009JAC
00
RG1, RG3
22.1Ω
1%
¼ Watt metal film,
axial through hole
International Yageo
Corp.
MFR-25FBF-22R1
RG2, RG4
10.0Ω
1%
¼ Watt metal film,
axial through hole
International Yageo
Corp.
MFR-25FBF-10R0
RE1, RE2, RE3,
RE4
0.1Ω
1%
5 Watt silicone
wirewound, through
hole
Vishay/Dale
RS005R1000FS73
RC2
0Ω
5%
¼ Watt metail film,
SMT 1206 (3216)
Panasonic
ERJ-S080R00V
RB1
392Ω
1%
¼ Watt metal film,
axial through hole
International Yageo
Corp.
MFR-25FBF-392R
RB2
750Ω
1%
¼ Watt metal film,
axial through hole
International Yageo
Corp.
MFR-25FBF-750R
RB3
1.10kΩ
1%
¼ Watt metal film,
axial through hole
International Yageo
Corp.
MFR-25FBF-1K10
RP1
200Ω
25%
0.2 Watt single turn
potentiometer,
through hole
Bourns Inc.
3306W-1-201
RIN, RI
249Ω
1%
¼ Watt metal film,
axial through hole
International Yageo
Corp.
MFR-25FBF-249R
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Reference
Value
Tolerance
Description
Manufacturer
Part Number
RT, RF1
6.81kΩ
1%
¼ Watt metal film,
axial through hole
International Yageo
Corp.
MFR-25FBF-6K81
RM1
75.0kΩ
1%
¼ Watt metal film,
axial through hole
International Yageo
Corp.
MFR-25FBF-75K0
RM2
20.0kΩ
1%
¼ Watt metal film,
axial through hole
International Yageo
Corp.
MFR-25FBF-20K0
RZ1
39.2kΩ
1%
¼ Watt metal film,
axial through hole
International Yageo
Corp.
MFR-25FBF-39K2
RBO1, RBO2, RC1
Not Used
S1
SPDT On-On right
angle, through hole
C & K Components
ET01MD1ABE
J1
3 pin 156mil header,
straight, tin plating
Molex/Waldom
Electronics Corp.
26-60-4030
J3
2 pin 156mil header,
straight, tin plating
Molex/Waldom
Electronics Corp.
26-60-4020
J4
RCA phono jack,
PCB mount, black
Kobiconn
161-0097-E
J2, J9, J10, J12
2 pin 100mil header,
straight, tin plating
Molex/Waldom
Electronics Corp.
22-23-2021
J11
3 pin 100mil header,
straight, tin plating
Molex/Waldom
Electronics Corp.
22-03-2031
6.3°C/W
LME49830 heat sink
Aavid Thermalloy
530101B00150
0.62°C/W
Output stage heat
sink, 4 inch length
Aavid Thermalloy
65605
20V
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