TI THS3091DRG4

THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
HIGH-VOLTAGE, LOW-DISTORTION, CURRENT-FEEDBACK
OPERATIONAL AMPLIFIERS
FEATURES
DESCRIPTION
1
• Low Distortion
– 77 dBc HD2 at 10 MHz, RL = 1 kΩ
– 69 dBc HD3 at 10 MHz, RL = 1 kΩ
• Low Noise
– 14 pA/√Hz Noninverting Current Noise
– 17 pA/√Hz Inverting Current Noise
– 2 nV/√Hz Voltage Noise
• High Slew Rate: 7300 V/µs (G = 5, VO = 20 VPP)
• Wide Bandwidth: 210 MHz (G = 2, RL = 100 Ω)
• High Output Current Drive: ±250 mA
• Wide Supply Range: ±5 V to ±15 V
• Power-Down Feature: (THS3095 Only)
2
APPLICATIONS
•
•
•
•
High-Voltage Arbitrary Waveform
Power FET Driver
Pin Driver
VDSL Line Driver
Total Harmonic Distortion − dBc
−30
−40
G = 5,
RF = 1 kΩ,
RL = 100 Ω,
VS = ±15 V
The THS3095 features a power-down pin (PD) that
puts the amplifier in low power standby mode, and
lowers the quiescent current from 9.5 mA to 500 µA.
The wide supply range combined with total harmonic
distortion as low as –69 dBc at 10 MHz, in addition,
to the high slew rate of 7300 V/µs makes the
THS3091/5 ideally suited for high-voltage arbitrary
waveform driver applications. Moreover, having the
ability to handle large voltage swings driving into
high-resistance and high-capacitance loads while
maintaining good settling time performance makes
the devices ideal for Pin driver and PowerFET driver
applications.
The THS3091 and THS3095 are offered in an 8-pin
SOIC (D), and the 8-pin SOIC (DDA) packages with
PowerPAD™.
TYPICAL ARBITRARY WAVEFORM
GENERATOR OUTPUT DRIVE CIRCUIT
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
−20
The THS3091 and THS3095 are high-voltage,
low-distortion,
high-speed,
current-feedback
amplifiers designed to operate over a wide supply
range of ±5 V to ±15 V for applications requiring
large, linear output signals such as Pin, Power FET,
and VDSL line drivers.
VO = 20 VPP
−
+
THS3091
VO = 10 VPP
−50
VOUT
−60
VO = 5 VPP
−70
IOUT1
DAC5686
IOUT2
−
+
−
+
THS3091
THS4271
−80
VO = 2 VPP
−90
100 k
1M
10 M
100 M
f − Frequency − Hz
−
+
THS3091
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2008, Texas Instruments Incorporated
THS3091
THS3095
SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008........................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TOP VIEW
D, DDA
TOP VIEW
THS3091
NC
VIN−
VIN+
VS−
1
8
2
7
3
6
4
5
D, DDA
THS3095
NC
VS+
VOUT
NC
REF
VIN −
VIN +
VS−
NC = No Internal Connection
1
8
2
7
3
6
4
5
PD
VS+
VOUT
NC
NC = No Internal Connection
See Note A.
Note A: The devices with the power−down option defaults to the ON state if no signal is applied to the PD pin. Additionallly, the REF
pin functional range is from VS− to (VS+ − 4 V).
ORDERING INFORMATION (1)
PART NUMBER
THS3091D
THS3091DR
THS3091DDA
THS3091DDAR
PACKAGE TYPE
SOIC-8
SOIC-8-PP (2)
TRANSPORT MEDIA, QUANTITY
Rails, 75
Tape and Reel, 2500
Rails, 75
Tape and Reel, 2500
Power-down
THS3095D
THS3095DR
THS3095DDA
THS3095DDAR
(1)
(2)
SOIC-8
SOIC-8-PP (2)
Rails, 75
Tape and Reel, 2500
Rails, 75
Tape and Reel, 2500
For the most current package and ordering information see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
The PowerPAD is electrically isolated from all other pins.
DISSIPATION RATINGS TABLE
PACKAGE
(1)
(2)
(3)
2
θJC (°C/W)
POWER RATING
TJ = 125°C
θJA (°C/W) (1)
(2)
TA = 25°C
TA = 85°C
D-8
38.3
97.5
1.02 W
410 mW
DDA-8 (3)
9.2
45.8
2.18 W
873 mW
This data was taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and
long-term reliability.
The THS3091 and THS3095 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heatsink and must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the
PowerPAD™ thermally enhanced package.
Submit Documentation Feedback
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
RECOMMENDED OPERATING CONDITIONS
Supply voltage
TA
MIN
MAX
Dual supply
±5
±15
Single supply
10
30
–40
85
Operating free-air temperature
UNIT
V
°C
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted) (1)
UNIT
VS- to VS+
Supply voltage
VI
Input voltage
33 V
± VS
VID
Differential input voltage
±4V
IO
Output current
350 mA
Continuous power dissipation
See Dissipation Ratings Table
TJ
Maximum junction temperature,
150°C
TJ (2)
Maximum junction temperature, continuous operation, long-term reliability
125°C
Tstg
Storage temperature
Lead temperature
–65°C to 150°C
(3)
HBM
2000
ESD ratings CDM
1500
MM
(1)
(2)
(3)
150
The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
See the MSL/Reflow Rating information provided with the material, or see TI's web site at www.ti.com for the latest information.
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
Submit Documentation Feedback
3
THS3091
THS3095
SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008........................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS
VS = ±15 V, RF = 1.21 kΩ, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
–40°C to
85°C
UNIT
MIN/TYP/
MAX
MHz
TYP
V/µs
TYP
ns
TYP
ns
TYP
dBc
TYP
AC PERFORMANCE
Small-signal bandwidth, –3 dB
G = 1, RF = 1.78 kΩ, VO = 200 mVPP
235
G = 2, RF = 1.21 kΩ, VO = 200 mVPP
210
G = 5, RF = 1 kΩ, VO = 200 mVPP
190
G = 10, RF = 866 Ω, VO = 200 mVPP
180
0.1-dB bandwidth flatness
G = 2, RF = 1.21 kΩ, VO = 200 mVPP
95
Large-signal bandwidth
G = 5, RF = 1 kΩ , VO = 4 VPP
135
G = 2, VO = 10-V step, RF = 1.21 kΩ
5000
G = 5, VO = 20-V step, RF = 1 kΩ
7300
Slew rate (25% to 75% level)
Rise and fall time
G = 2, VO = 5-VPP, RF = 1.21 kΩ
5
Settling time to 0.1%
G = –2, VO = 2 VPP step
42
Settling time to 0.01%
G = –2, VO = 2 VPP step
72
Harmonic distortion
2nd Harmonic distortion
G = 2, RF = 1.21 kΩ,
VO = 2 VPP, f = 10 MHz
3rd Harmonic distortion
RL = 100Ω
66
RL = 1 kΩ
77
RL = 100 Ω
74
RL = 1 kΩ
69
Input voltage noise
f > 10 kHz
2
nV / √Hz
TYP
Noninverting input current noise
f > 10 kHz
14
pA / √Hz
TYP
Inverting input current noise
f > 10 kHz
17
pA / √Hz
TYP
Differential gain
G = 2, RL = 150 Ω,
RF = 1.21 kΩ
Differential phase
NTSC
0.013%
PAL
0.011%
NTSC
0.020°
PAL
0.026°
TYP
DC PERFORMANCE
Transimpedance
Input offset voltage
Average offset voltage drift
Noninverting input bias current
Average bias current drift
Inverting input bias current
Average bias current drift
Input offset current
Average offset current drift
VO = ±7.5 V, Gain = 1
VCM = 0 V
VCM = 0 V
VCM = 0 V
VCM = 0 V
850
350
300
300
kΩ
MIN
0.9
3
4
4
mV
MAX
±10
±10
µV/°C
TYP
4
15
20
20
µA
MAX
±20
±20
nA/°C
TYP
3.5
15
20
20
µA
MAX
±20
±20
nA/°C
TYP
1.7
10
15
15
µA
MAX
±20
±20
nA/°C
TYP
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
VCM = ±10 V
±13.6
±13.3
±13
±13
V
MIN
69
62
59
59
dB
MIN
Noninverting input resistance
1.3
MΩ
TYP
Noninverting input capacitance
0.1
pF
TYP
Inverting input resistance
30
Ω
TYP
Inverting input capacitance
1.4
pF
TYP
4
Submit Documentation Feedback
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
ELECTRICAL CHARACTERISTICS (continued)
VS = ±15 V, RF = 1.21 kΩ, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
–40°C to
85°C
UNIT
MIN/TYP/
MAX
RL = 1 kΩ
±13.2
±12.8
±12.5
±12.5
RL = 100 Ω
±12.5
±12.1
±11.8
±11.8
V
MIN
Output current (sourcing)
RL = 40 Ω
280
225
200
Output current (sinking)
RL = 40 Ω
250
200
175
200
mA
MIN
175
mA
Output impedance
f = 1 MHz, Closed loop
0.06
MIN
Ω
TYP
OUTPUT CHARACTERISTICS
Output voltage swing
POWER SUPPLY
Specified operating voltage
±15
±16
±16
±16
V
MAX
Maximum quiescent current
9.5
10.5
11
11
mA
MAX
Minimum quiescent current
9.5
8.5
8
8
mA
MIN
Power supply rejection (+PSRR)
VS+ = 15.5 V to 14.5 V, VS– = 15 V
75
70
65
65
dB
MIN
Power supply rejection (–PSRR)
VS+ = 15 V, VS– = –15.5 V to –14.5 V
73
68
65
65
dB
MIN
VS+ –4
V
MAX
VS–
V
MIN
Enable
PD ≥ REF
+2
V
MIN
Disable
PD ≤ REF
+0.8
V
MAX
PD = 0V
500
700
800
800
µA
MAX
VPD = 0 V, REF = 0 V,
11
15
20
20
VPD = 3.3 V, REF = 0 V
11
15
20
20
µA
MAX
µs
TYP
POWER-DOWN CHARACTERISTICS (THS3095 ONLY)
REF voltage range (1)
Power-down voltage level (1)
Power-down quiescent current
VPD quiescent current
Turnon time delay
90% of final value
60
Turnoff time delay
10% of final value
150
(1)
For detailed information on the behavior of the power-down circuit, see the power-down functionality and power-down reference sections
in the Application Information section of this data sheet.
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
Submit Documentation Feedback
5
THS3091
THS3095
SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008........................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS
VS = ±5 V, RF = 1.15 kΩ, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
–40°C to
85°C
UNIT
MIN/TYP/
MAX
MHz
TYP
V/µs
TYP
ns
TYP
ns
TYP
dBc
TYP
AC PERFORMANCE
Small-signal bandwidth, –3 dB
G = 1, RF = 1.78 kΩ, VO = 200 mVPP
190
G = 2, RF = 1.15 kΩ, VO = 200 mVPP
180
G = 5, RF = 1 kΩ, VO = 200 mVPP
160
G = 10, RF = 866 Ω, VO = 200 mVPP
150
0.1-dB bandwidth flatness
G = 2, RF = 1.15 kΩ, VO = 200 mVPP
65
Large-signal bandwidth
G = 2, RF = 1.15 kΩ , VO = 4 VPP
160
G = 2, VO= 5-V step, RF = 1.21 kΩ
1400
G = 5, VO= 5-V step, RF = 1 kΩ
1900
Slew rate (25% to 75% level)
Rise and fall time
G = 2, VO = 5-V step, RF = 1.21 kΩ
5
Settling time to 0.1%
G = –2, VO = 2 VPP step
35
Settling time to 0.01%
G = –2, VO = 2 VPP step
73
Harmonic distortion
2nd Harmonic distortion
G = 2, RF = 1.15 kΩ,
VO = 2 VPP, f = 10 MHz
3rd Harmonic distortion
RL = 100 Ω
77
RL = 1 kΩ
73
RL = 100 Ω
70
RL = 1 kΩ
68
Input voltage noise
f > 10 kHz
2
nV / √Hz
TYP
Noninverting input current noise
f > 10 kHz
14
pA / √Hz
TYP
Inverting input current noise
f > 10 kHz
17
pA / √Hz
TYP
Differential gain
G = 2, RL = 150 Ω,
RF = 1.15 kΩ
Differential phase
NTSC
0.027%
PAL
0.025%
NTSC
0.04°
PAL
0.05°
TYP
DC PERFORMANCE
Transimpedance
Input offset voltage
Average offset voltage drift
Noninverting input bias current
Average bias current drift
Inverting input bias current
Average bias current drift
Input offset current
Average offset current drift
VO = ±2.5 V, Gain = 1
VCM = 0 V
VCM = 0 V
VCM = 0 V
VCM = 0 V
700
250
200
200
kΩ
MIN
0.3
2
3
3
mV
MAX
±10
±10
µV/°C
TYP
2
15
20
20
µA
MAX
±20
±20
nA/°C
TYP
5
15
20
20
µA
MAX
±20
±20
nA/°C
TYP
1
10
15
15
µA
MAX
±20
±20
nA/°C
TYP
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
VCM = ±2.0 V, VO = 0 V
±3.6
±3.3
±3
±3
V
MIN
66
60
57
57
dB
MIN
Noninverting input resistance
1.1
MΩ
TYP
Noninverting input capacitance
1.2
pF
TYP
Inverting input resistance
32
Ω
TYP
Inverting input capacitance
1.5
pF
TYP
6
Submit Documentation Feedback
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
ELECTRICAL CHARACTERISTICS (continued)
VS = ±5 V, RF = 1.15 kΩ, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
–40°C to
85°C
RL = 1 kΩ
±3.4
±3.1
±2.8
±2.8
RL = 100 Ω
±3.1
±2.7
±2.5
±2.5
UNIT
MIN/TYP/
MAX
V
MIN
MIN
OUTPUT CHARACTERISTICS
Output voltage swing
Output current (sourcing)
RL = 10 Ω
180
140
120
120
mA
Output current (sinking)
RL = 10 Ω
–160
–140
–120
–120
mA
MIN
Output impedance
f = 1 MHz, Closed loop
0.09
Ω
TYP
POWER SUPPLY
Specified operating voltage
±5
±4.5
±4.5
±4.5
V
MAX
Maximum quiescent current
8.2
9
9.5
9.5
mA
MAX
Minimum quiescent current
8.2
7
6.5
6.5
mA
MIN
Power supply rejection (+PSRR)
VS+ = 5.5 V to 4.5 V, VS– = 5 V
73
68
63
63
dB
MIN
Power supply rejection (–PSRR)
VS+ = 5 V, VS– = –4.5 V to –5.5 V
71
65
60
60
dB
MIN
VS+ –4
V
MAX
VS–
V
MIN
Enable
PD ≥ REF
+2
V
MIN
Disable
PD ≤ REF
+0.8
V
MAX
PD = 0V
300
500
600
600
µA
MAX
VPD = 0 V, REF = 0 V,
11
15
20
20
VPD = 3.3 V, REF = 0 V
11
15
20
20
µA
MAX
µs
TYP
POWER-DOWN CHARACTERISTICS (THS3095 ONLY)
REF voltage range (1)
Power-down voltage level (1)
Power-down quiescent current
VPD quiescent current
Turnon time delay
90% of final value
60
Turnoff time delay
10% of final value
150
(1)
For detailed information on the behavior of the power-down circuit, see the power-down functionality and power-down reference sections
in the Application Information section of this data sheet.
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
Submit Documentation Feedback
7
THS3091
THS3095
SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008........................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
±15-V GRAPHS
FIGURE
Noninverting small-signal frequency response
1, 2
Inverting small-signal frequency response
3
0.1-dB gain flatness frequency response
4
Noninverting large-signal frequency response
5
Inverting large-signal frequency response
6
Capacitive load frequency response
7
Recommended RISO
vs Capacitive load
8
2nd Harmonic distortion
vs Frequency
9, 11
3rd Harmonic distortion
vs Frequency
10, 12
2nd Harmonic distortion
vs Frequency
13
3rd Harmonic distortion
vs Frequency
Harmonic distortion
vs Output voltage swing
Slew rate
vs Output voltage step
Noise
vs Frequency
14
15, 16
17, 18, 19
20
Settling time
21, 22
Quiescent current
vs Supply voltage
23
Quiescent current
vs Frequency
24
Output voltage
vs Load resistance
25
Input bias and offset current
vs Case temperature
26
Input offset voltage
vs Case temperature
27
Transimpedance
vs Frequency
28
Rejection ratio
vs Frequency
29
Noninverting small-signal transient response
30
Inverting large-signal transient response
31, 32
Overdrive recovery time
33
Differential gain
vs Number of loads
34
Differential phase
vs Number of loads
35
Closed-loop output impedance
vs Frequency
36
Power-down quiescent current
vs Supply voltage
37
Turnon and turnoff time delay
8
Submit Documentation Feedback
38
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
TABLE OF GRAPHS (Continued)
±5-V GRAPHS
FIGURE
Noninverting small-signal frequency response
39
Inverting small-signal frequency response
40
0.1-dB gain flatness frequency response
41
Noninverting large-signal frequency response
42
Inverting large-signal frequency response
43
Settling time
44
2nd Harmonic distortion
vs Frequency
45, 47
3rd Harmonic distortion
vs Frequency
46, 48
Harmonic distortion
vs Output voltage swing
Slew rate
vs Output voltage step
Quiescent current
vs Frequency
54
Output voltage
vs Load resistance
55
Input bias and offset current
vs Case temperature
56
Overdrive recovery time
Rejection ratio
49, 50
51, 52, 53
57
vs Frequency
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
58
Submit Documentation Feedback
9
THS3091
THS3095
SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008........................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS (±15 V)
9
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
24
22
RF = 750 Ω
G = 10, RF = 866 Ω
20
18
7
Noninverting Gain − dB
6
RRFF==1.21
1.21kkΩ
Ω
5
4
RF = 1.5 kΩ
3
Gain = 2,
RL =100 Ω,
VO = 200 mVPP,
VS = ±15 V
2
1
0
1M
10 M
100 M
1G
16
14
G = 5, RF = 1 kΩ
12
10
8
6
4
RL = 100 Ω,
VO = 200 mVPP,
VS = ±15 V
G = 2, RF = 1.21 kΩ
2
0
−2
−4
G = 1, RF = 1.78 kΩ
1M
f − Frequency − Hz
G = −5, RF = 909 Ω
Inverting Gain − dB
10
8
G = 2, RF = 1.21 kΩ
6
10
8
G = −2, RF = 1 kΩ
6
4
2
4
−2
−4
1M
VO = 4 VPP,
RL = 100 Ω,
VS = ±15 V
0
VO = 4 VPP,
RL = 100 Ω,
VS = ±15 V
10 M
100 M
1G
1M
10 M
100 M
1G
f − Frequency − Hz
f − Frequency − Hz
Figure 4.
Figure 5.
Figure 6.
CAPACITIVE LOAD
FREQUENCY RESPONSE
RECOMMENDED RISO
vs
CAPACITIVE LOAD
2ND HARMONIC DISTORTION
vs
FREQUENCY
45
R(ISO) = 30.9 Ω
CL = 22 pF
R(ISO) = 22.1 Ω
CL = 47 pF
R(ISO) = 15.8 Ω
CL = 100 pF
Gain = 5,
RL = 100 Ω,
VS =±15 V
−40
Gain = 5,
RL = 100 Ω,
VS = ±15 V
40
Recommended R
−Ω
ISO
12
Signal Gain − dB
1G
12
12
1G
R(ISO) = 38.3 Ω
CL = 10 pF
10 M
100 M
14
0
14
35
−45
30
25
20
15
10
5
100 M
f − Frequency − Hz
1G
Figure 7.
10
16
14
1M
10 M
100 M
f - Frequency - Hz
16
0
10 M
f − Frequency − Hz
G = 5, RF = 1 kΩ
5.7
−2
1M
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
2
2
G = −1, RF = 1.05 kΩ
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
5.8
4
G = −2, RF = 1 kΩ
0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE
5.9
6
RL = 100 Ω,
VO = 200 mVPP,
VS = ±15 V
Figure 3.
6
8
12
10
8
6
4
2
0
−2
−4
1G
16
10
G = −5, RF = 909 Ω
Figure 2.
Gain = 2,
RF = 1.21 kΩ,
RL = 100 Ω,
VO = 200 mVPP,
VS = ±15 V
100 k
G = −10, RF = 866 Ω
Figure 1.
Noninverting Gain − dB
Noninverting Gain - dB
6.1
100 M
24
22
20
18
16
14
f − Frequency − Hz
6.3
6.2
10 M
2nd Harmonic Distortion − dBc
Noninverting Gain − dB
8
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Inverting Gain − dB
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Submit Documentation Feedback
−50
VO = 2 VPP,
RL = 100 Ω,
VS = ±15 V
−55
−60
G = 1, RF = 1.78 kΩ
−65
−70
−75
G = 2, RF = 1.21 kΩ
−80
−85
−90
0
10
100
100 k
1M
10 M
100 M
f − Frequency − Hz
CL − Capacitive Load − pF
Figure 8.
Figure 9.
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
TYPICAL CHARACTERISTICS (±15 V) (continued)
3RD HARMONIC DISTORTION
vs
FREQUENCY
2ND HARMONIC DISTORTION
vs
FREQUENCY
−40
-50
-60
G = 1, RF = 1.78 kΩ
-70
-80
G = 2, RF = 1.21 kΩ
-90
−40
VO = 2 VPP,
RL = 1 kΩ,
VS = ±15 V
−50
−60
G = 1, RF = 1.78 kΩ
−70
VO = 2 VPP,
RL = 1 kΩ,
VS = ±15 V
−45
3rd Harmonic Distortion − dBc
VO = 2 VPP,
RL = 100 Ω,
VS = ±15 V
2nd Harmonic Distortion − dBc
-40
3rd Harmonic Distortion - dBc
3RD HARMONIC DISTORTION
vs
FREQUENCY
−80
G = 2, RF = 1.21 kΩ
−90
−50
−55
−60
G = 1, RF = 1.78 kΩ
−65
−70
−75
G = 2, RF = 1.21 kΩ
−80
−85
−100
100 k
-100
100 k
1M
10 M
100 M
−90
1M
100 k
100 M
100 M
Figure 11.
Figure 12.
2ND HARMONIC DISTORTION
vs
FREQUENCY
3RD HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−30
3rd Harmonic Distortion − dBc
−40
−50
−60
VO = 10 VPP
−70
−80
VO = 2 VPP
-60
G = 5,
RF = 1 kΩ,
RL = 100 Ω,
VS = ±15 V
VO = 20 VPP
−40
-65
Harmonic Distortion - dBc
G = 5,
RF = 1 kΩ,
RL = 100 Ω,
VS = ±15 V
−50
VO = 20 VPP
−60
−70
VO = 10 VPP
−80
10 M
100 M
HD2
-75
-80
HD3
-85
Gain = 5,
RF = 1 kΩ
RL = 100 Ω,
f= 1 MHz
VS = ±15 V
-90
-100
−90
1M
-70
-95
VO = 2 VPP
−90
1M
10 M
f − Frequency − Hz
100 M
0
2
4
f − Frequency − Hz
6
8
10 12 14 16
18 20
VO - Output Voltage Swing - VPP
Figure 13.
Figure 14.
Figure 15.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
2000
Gain = 5,
RF = 1 kΩ
RL = 100 Ω,
f= 8 MHz
VS = ±15 V
SR − Slew Rate − V/ µ s
HD2
-60
-70
-80
6000
Gain = 1
RL = 100 Ω
RF = 1.78 kΩ
VS = ±15 V
1800
HD3
1600
Rise
1400
1200
Fall
1000
800
600
400
-90
Gain = 2
RL = 100 Ω
RF = 1.21 kΩ
VS = ±15 V
5000
SR - Slew Rate - V/ µ s
-40
Harmonic Distortion - dBc
10 M
f − Frequency − Hz
Figure 10.
−30
-50
1M
f − Frequency − Hz
f - Frequency - Hz
2nd Harmonic Distortion − dBc
10 M
4000
3000
2000
Rise
Fall
1000
200
-100
0
0
2
VO - Output Voltage Swing - VPP
1 1.5 2 2.5 3 3.5 4
VO − Output Voltage − VPP
Figure 16.
Figure 17.
4
6
8
10
12 14
16 18 20
0
0.5
4.5
5
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
0
0
1
2
3
4
5
6
7
8
9
10
VO - Output Voltage - VPP
Figure 18.
Submit Documentation Feedback
11
THS3091
THS3095
SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008........................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS (±15 V) (continued)
SLEW RATE
vs
OUTPUT VOLTAGE STEP
NOISE
vs
FREQUENCY
8000
5000
Rise
4000
Fall
3000
2000
100
In−
In+
10
Vn
0.5
0.25
-0.25
-0.5
-0.75
Falling Edge
-1
1
0
2
1k
10 k
0
100 k
5
6
7
8
SETTLING TIME
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
QUIESCENT CURRENT
vs
FREQUENCY
Falling Edge
4
6
8
10
TA = 25 °C
9
8.5
TA = −40 °C
8
7.5
7
6.5
18
16
4
5
6
7
8
VO = 4VPP
14
12
10
VO = 2VPP
8
6
4
2
3
Gain = 5
RF = 1 kΩ,
RL = 100 Ω,
VS = ±15 V
0
9 10 11 12 13 14 15
100 k
VS − Supply Voltage − ±V
100 M
10 M
1M
f − Frequency − Hz
Figure 22.
Figure 23.
Figure 24.
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
INPUT BIAS AND
OFFSET CURRENT
vs
CASE TEMPERATURE
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
7
12
6.5
6
8
4
VS = ±15 V
TA = -40 to 85°C
-4
-8
-12
100
1000
RL - Load Resistance - Ω
Figure 25.
Submit Documentation Feedback
3
5.5
5
4.5
4
IIB+
3.5
3
2.5
2
1.5
1
1G
VS = ±15 V
IIB-
VOS - Input Offset Voltage - mV
16
10
20
I Q − Quiescent Current − mA
9.5
12
9
22
TA = 85 °C
6
10
4
Figure 21.
Gain = -2
RL = 100 Ω
RF = 1 kΩ
VS = ±15 V
0
3
Figure 20.
Rising Edge
2
2
Figure 19.
10
0
1
t - Time - ns
I IB - Input Bias Currents - µ A
I OS - Input Offset Currents - µ A
VO - Output Voltage - V
100
f − Frequency − Hz
t - Time - ns
12
-1.25
10
4 6
8 10 12 14 16 18 20
VO - Output Voltage - VPP
I Q− Quiescent Current − mA
VO - Output Voltage - V
0
-16
Gain = -2
RL = 100 Ω
RF =1 kΩ
VS = ±15 V
0
1000
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
Rising Edge
0.75
VO - Output Voltage - V
Hz
Vn − Voltage Noise − nV/
6000
1.25
1
I n − Current Noise − pA/ Hz
Gain = 5
RL = 100 Ω
RF = 1 kΩ
VS = ±15 V
7000
SR - Slew Rate - V/ µ s
SETTLING TIME
1000
IOS
0.5
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
2.5
2
VS = ±15 V
1.5
1
0.5
VS = ±5 V
0
-40 -30 -20-10 0 10 20 30 40 50 60 70 80 90
TC - Case Temperature - °C
TC - Case Temperature - °C
Figure 26.
Figure 27.
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
TYPICAL CHARACTERISTICS (±15 V) (continued)
TRANSIMPEDANCE
vs
FREQUENCY
REJECTION RATIO
vs
FREQUENCY
70
VS = ±15 V and ±5 V
60
60
50
40
30
50
CMRR
40
30
PSRR+
20
0.15
Input
0.1
0.05
0
-0.05
Gain = 2
RL = 100 Ω
RF = 1 kΩ
VS = ±15 V
-0.1
-0.15
-0.2
10
10
-0.25
10 M
100 M
1G
100 k
1M
10 M
100 M
-0.3
1G
0
Figure 29.
INVERTING LARGE-SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE-SIGNAL
TRANSIENT RESPONSE
VO - Output Voltage - V
2
1
0
Input
−1
−2
Gain = −5
RL = 100 Ω
RF = 909 Ω
VS = ±15 V
−3
−4
−5
Gain = -5
RL = 100 Ω
RF =909 Ω
VS = ±15 V
8
3
6
4
Input
0
-2
-4
-6
Output
10
15
20
25
30
35
1
0
0
−5
−1
−10
−2
−15
−3
10
20
30
40
50
60
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
70
Figure 33.
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
CLOSED-LOOP OUTPUT
IMPEDANCE
vs
FREQUENCY
0.05
PAL
0.04
0.03
0.02
0
2
3
4
5
6
7
0.04
0.03
PAL
0.02
NTSC
0.01
NTSC
0.01
0
8
−4
100
Gain = 2
RF = 1.21 kΩ
VS = ±15 V
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
Closed-Loop Output Impedance − Ω
°
1
t − Time − µs
Figure 32.
0.05
1
2
5
t - Time - ns
0.06
0
3
Figure 31.
Differential Phase −
0.07
10
t − Time − ns
Gain = 2
RF = 1.21 kΩ
VS = ±15 V
40 IRE - NTSC and Pal
Worst Case ±100 IRE Ramp
0.08
4
−20
0
40
0.10
0.09
70
-10
-12
5
60
Gain = 5,
RL = 100 Ω,
RF = 1 kΩ,
VS = ±15 V
15
2
-8
−6
0
50
OVERDRIVE RECOVERY TIME
VO − Output Voltage − V
Output
40
20
10
5
30
Figure 30.
12
6
20
t - Time - ns
Figure 28.
4
10
f − Frequency − Hz
VI − Input Voltage − V
0
1M
f − Frequency − Hz
VO − Output Voltage − V
Output
0.2
20
0
100 k
Differential Gain - %
0.25
PSRR−
80
70
0.3
VS = ±15 V
VO - Output Voltage - V
90
Rejection Ratio − dB
Transimpedance Gain − dB Ohms
100
NONINVERTING SMALL-SIGNAL
TRANSIENT RESPONSE
Gain = 2,
RISO = 5.11 Ω,
RF = 1.21 KΩ,
VS = ±15 V
10
1
1.21 kΩ
1.21 kΩ
0.1
5.11 Ω VO
−
+
0.01
0
1
2
3
4
5
6
Number of Loads - 150 Ω
Number of Loads − 150 Ω
Figure 34.
Figure 35.
7
8
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 36.
Submit Documentation Feedback
13
THS3091
THS3095
SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008........................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS (±15 V) (continued)
POWER-DOWN QUIESCENT
CURRENT
vs
SUPPLY VOLTAGE
TURNON AND TURNOFF
TIME DELAY
6
Power-on Pulse
500
TA = 85°C
400
TA = -40°C
300
TA = 25°C
200
5
4
Gain = 2,
VI = 0.1 Vdc
RL = 100 Ω
VS = ±15 V and ±5 V
3
2
1
0
0.3
0.2
0.1
Power-on Pulse − V
VO − Output Voltage Level − V
Powerdown Quiescent Current - µ A
600
Output Voltage
100
0
−0.1
0
3
4
5
6
7
8
9
0
10 11 12 13 14 15
1
2
VS - Supply Voltage - ±V
3
4
5
6
7
t − Time − ms
Figure 37.
Figure 38.
TYPICAL CHARACTERISTICS (±5 V)
G = 5, RF = 1 kΩ
RL = 100 Ω,
VO = 200 mVPP.
VS = ±5 V
G = 2, RF = 1.15 kΩ
G =1, RF = 1.5 kΩ
1M
10 M
100 M
24
22
20
18
16
14
12
10
8
6
4
2
0
−2
−4
6.3
6.2
G = −5, RF = 909 Ω
RL = 100 Ω,
VO = 200 mVPP.
VS = ±5 V
G = −2, RF = 1 kΩ
Figure 40.
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
16
G = 5, RF = 1 kΩ
Inverting Gain − dB
Noninverting Gain − dB
12
10
8
G = 2, RF = 1.15 kΩ
6
4
2
10 M
100 M
1G
f − Frequency − Hz
Figure 42.
14
Submit Documentation Feedback
100 M
Figure 41.
SETTLING TIME
1.25
1
12
0.75
10
8
6
G = −2, RF = 1 kΩ
4
10 M
f - Frequency - Hz
Rising Edge
0.5
0.25
Gain = -2
RL = 100 Ω
RF = 1 kΩ
VS = ±5 V
0
-0.25
2
-0.5
-0.75
RL = 100 Ω,
VO = 4 VPP,
VS = ±5 V
Falling Edge
-1
-1.25
−4
1M
1M
G = −5, RF = 909 Ω
−2
0
1G
14
0
RL = 100 Ω,
VO = 4 VPP,
VS = ±5 V
5.9
5.7
10 M
100 M
f − Frequency − Hz
Figure 39.
14
6
5.8
f - Frequency - Hz
16
6.1
G = −1, RF = 1.05 Ω
1M
1G
Gain = 2,
RF = 1.21 kΩ,
RL = 100 Ω,
VO = 200 mVPP,
VS = ±5 V
G = −10, RF = 866 Ω
Noninverting Gain - dB
G = 10, RF = 909 Ω
0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE
VO - Output Voltage - V
24
22
20
18
16
14
12
10
8
6
4
2
0
-2
-4
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Inverting Gain − dB
Noninverting Gain - dB
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
1M
10 M
100 M
f − Frequency − Hz
1G
0
1
2
3
4
5
6
7
8
9
10
t - Time - ns
Figure 43.
Figure 44.
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
TYPICAL CHARACTERISTICS (±5 V) (continued)
2ND HARMONIC DISTORTION
vs
FREQUENCY
3RD HARMONIC DISTORTION
vs
FREQUENCY
G = 1, RF = 1.78 kΩ
−70
−80
G = 2, RF = 1.15 kΩ
−90
-50
-60
-70
G = 1, RF = 1.78 kΩ
-80
G = 2, RF = 1.15 kΩ
-90
1M
10 M
100 k
100 M
1M
1M
10 M
100 M
f − Frequency − Hz
3RD HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
-20
−20
Gain = 5,
RF = 1 kΩ
RL = 100 Ω,
f= 1 MHz
VS = ±5 V
Harmonic Distortion - dBc
-30
G = 1, RF = 1.78 kΩ
−80
G = 2, RF = 1.15 kΩ
−90
-40
-50
-60
HD3
-70
-80
HD2
-90
10 M
100 M
−40
−50
HD3
−60
HD2
−70
−80
−90
-100
1M
Gain = 5,
RF = 1 kΩ
RL = 100 Ω,
f= 8 MHz
VS = ±5 V
−30
Harmonic Distortion − dBc
VO = 2 VPP,
RL = 1 kΩ,
VS = ±5 V
−100
100 k
−100
0
f − Frequency − Hz
1
2
3
4
5
6
0
1
VO - Output Voltage Swing - VPP
2
3
4
5
Figure 49.
Figure 50.
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
2000
1600
Gain = 1
RL = 100 Ω
RF = 1.78 kΩ
VS = ±5 V
SR − Slew Rate − V/µ s
Fall
800
600
Rise
400
1200
1000
400
0
0
1 1.5
Rise
600
200
2
2.5
3 3.5
4
4.5
5
Gain = 5
RL = 100 Ω
RF = 1 kΩ
VS = ±5 V
1800
Fall
800
200
0 0.5
Gain = 1
RL = 100 Ω
RF = 1.21 kΩ
VS = ±5 V
1400
1000
6
VO − Output Voltage Swing − VPP
Figure 48.
1600
SR − Slew Rate − V/ µs
−100
100 k
100 M
Figure 47.
−70
1200
G = 2, RF = 1.15 kΩ
−90
Figure 46.
−60
1400
−80
Figure 45.
−40
3rd Harmonic Distortion − dBc
10 M
G = 1, RF = 1.78 kΩ
−70
f - Frequency - Hz
f − Frequency − Hz
−50
−60
-100
−100
100 k
VO = 2 VPP,
RL = 1 kΩ,
VS = ±5 V
−50
2nd Harmonic Distortion − dBc
−60
VO = 2 VPP,
RL = 100 Ω,
VS = ±5 V
SR - Slew Rate - V/ µ s
−50
−40
-40
VO = 2 VPP,
RL = 100 Ω,
VS = ±5 V
3rd Harmonic Distortion - dBc
2nd Harmonic Distortion − dBc
−40
2ND HARMONIC DISTORTION
vs
FREQUENCY
1600
1400
Fall
Rise
1200
1000
800
600
400
200
VO − Output Voltage −VPP
0
1
2
3
4
VO − Output Voltage −VPP
Figure 51.
Figure 52.
5
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
0
0
0.5
1 1.5 2 2.5 3 3.5 4
VO - Output Voltage -VPP
4.5
5
Figure 53.
Submit Documentation Feedback
15
THS3091
THS3095
SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008........................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS (±5 V) (continued)
QUIESCENT CURRENT
vs
FREQUENCY
I Q− Quiescent Current − mA
18
16
14
VO - Output Voltage - V
Gain = 5
RF = 1 kΩ,
RL = 100 Ω,
VS = ±5 V
VO = 4 VPP
12
10
VO = 2 VPP
8
6
4
3.5
8
3
2.5
7
2
1.5
1
0.5
I IB - Input Bias Current - µ A
I OS - Input Offset Current - µ A
22
20
INPUT BIAS AND
OFFSET CURRENT
vs
CASE TEMPERATURE
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
VS = ±5 V
TA = -40 to 85°C
0
-0.5
-1
-1.5
-2
-2.5
-3
2
0
100 k
10 M
100 M
1G
10
100
Figure 54.
Figure 56.
VS = ±5 V
0.6
0.2
0
0
-1
-0.2
-2
-0.4
-3
-0.6
-4
-0.8
-5
-1
0.4
0.6
0.8
1
PSRRRejection Ratio - dB
0.4
1
0.2
50
40
30
CMRR
PSRR+
20
10
0
100 k
1M
10 M
f - Frequency - Hz
Figure 57.
Submit Documentation Feedback
10 20 30 40 50 60 70 80 90
TC - Case Temperature - °C
60
VI - Input Voltage - V
VO - Output Voltage - A
IIB+
70
0.8
t - Time - µs
16
2
REJECTION RATIO
vs
FREQUENCY
1
Gain = 5,
RL = 100 Ω,
RF = 1 kΩ,
VS = ±5 V
0
3
Figure 55.
5
2
IOS
4
0
-40 -30 -20 -10 0
1000
OVERDRIVE RECOVERY
TIME
3
5
RL - Load Resistance - Ω
f − Frequency − Hz
4
IIB-
6
1
-3.5
1M
VS = ±5 V
100 M
Figure 58.
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
APPLICATION INFORMATION
WIDEBAND, NONINVERTING OPERATION
The THS3091/5 are unity gain stable 235-MHz
current- feedback operational amplifiers, designed to
operate from a ±5-V to ±15-V power supply.
Figure 59 shows the THS3091 in a noninverting gain
of 2-V/V configuration typically used to generate the
performance curves. Most of the curves were
characterized using signal sources with 50-Ω source
impedance, and with measurement equipment
presenting a 50-Ω load impedance.
15 V
Table 1. Recommended Resistor Values for
Optimum Frequency Response
+VS
+
0.1 µF
50-Ω Source
6.8 µF
THS3091 and THS3095 RF and RG values for minimal peaking
with RL = 100 Ω
GAIN (V/V)
+
VI
49.9 Ω
THS3091
49.9 Ω
RG
SUPPLY VOLTAGE
(V)
RG (Ω)
RF (Ω)
±15
–
1.78 k
1
_
±5
–
1.78 k
±15
1.21 k
1.21 k
±5
1.15 k
1.15 k
±15
249
1k
±5
249
1k
±15
95.3
866
±5
95.3
866
–1
±15 and ±5
1.05 k
1.05 k
–2
±15 and ±5
499
1k
–5
±15 and ±5
182
909
–10
±15 and ±5
86.6
866
50-Ω LOAD
RF
1.21 kΩ
Current-feedback amplifiers are highly dependent on
the feedback resistor RF for maximum performance
and stability. Table 1 shows the optimal gain-setting
resistors RF and RG at different gains to give
maximum bandwidth with minimal peaking in the
frequency response. Higher bandwidths can be
achieved, at the expense of added peaking in the
frequency response, by using even lower values for
RF. Conversely, increasing RF decreases the
bandwidth, but stability is improved.
2
1.21 kΩ
0.1 µF
6.8 µF
+
5
10
−VS
−15 V
Figure 59. Wideband, Noninverting Gain
Configuration
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
Submit Documentation Feedback
17
THS3091
THS3095
SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008........................................................................................................................................ www.ti.com
WIDEBAND, INVERTING OPERATION
+VS
Figure 60 shows the THS3091 in a typical inverting
gain configuration where the input and output
impedances and signal gain from Figure 59 are
retained in an inverting circuit configuration.
50-Ω Source
+
VI
RT
50-Ω LOAD
15 V +VS
+VS
2
+
0.1 µF
+
THS3091
49.9 Ω
49.9 Ω THS3091
_
RF
1.21 kΩ
RG
1.21 kΩ
6.8 µF
49.9 Ω
+VS
2
_
RF
50-Ω LOAD
50-Ω Source
VI
1 kΩ
RG
RF
499 Ω
RM
56.2 Ω
1 kΩ
0.1 µF
RG
VI
6.8 µF
499 Ω
RT
56.2 Ω
+
−15 V
VS
50-Ω Source
Figure 60. Wideband, Inverting Gain
Configuration
49.9 Ω
THS3091
+
50-Ω LOAD
+VS
2
+VS
2
−VS
_
Figure 61. DC-Coupled, Single-Supply Operation
Video Distribution
SINGLE-SUPPLY OPERATION
The THS3091/5 have the capability to operate from a
single-supply voltage ranging from 10 V to 30 V.
When operating from a single power supply, biasing
the input and output at mid-supply allows for the
maximum output voltage swing. The circuits shown in
Figure 61 show inverting and noninverting amplifiers
configured for single-supply operations.
The wide bandwidth, high slew rate, and high output
drive current of the THS3091/5 matches the demands
for video distribution for delivering video signals down
multiple cables. To ensure high signal quality with
minimal degradation of performance, a 0.1-dB gain
flatness should be at least 7x the passband
frequency to minimize group delay variations from the
amplifier. A high slew rate minimizes distortion of the
video signal, and supports component video and
RGB video signals that require fast transition times
and fast settling times for high signal quality.
1.21 kΩ
1.21 kΩ
15 V
−
+
VI
75 Ω
75-Ω Transmission Line
−15 V
n Lines
75 Ω
VO(1)
75 Ω
VO(n)
75 Ω
75 Ω
Figure 62. Video Distribution Amplifier
Application
18
Submit Documentation Feedback
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
Driving Capacitive Loads
Applications such as FET line drivers can be highly
capacitive and cause stability problems for
high-speed amplifiers.
Figure 63 through Figure 68 show recommended
methods for driving capacitive loads. The basic idea
is to use a resistor or ferrite chip to isolate the phase
shift at high frequency caused by the capacitive load
from the amplifier’s feedback path. See Figure 63 for
recommended resistor values versus capacitive load.
45
Gain = 5,
RL = 100 Ω,
VS = ±15 V
Recommended R
−Ω
ISO
40
35
30
25
20
15
10
5
0
10
100
CL − Capacitive Load − pF
Figure 63. Recommended RISO vs Capacitive Load
1 kΩ
Using a ferrite chip in place of RISO, as shown in
Figure 65, is another approach of isolating the output
of the amplifier. The ferrite's impedance characteristic
versus frequency is useful to maintain the
low-frequency load independence of the amplifier
while isolating the phase shift caused by the
capacitance at high frequency. Use a ferrite with
similar impedance to RISO, 20 Ω to 50 Ω, at 100 MHz
and low impedance at dc.
Figure 66 shows another method used to maintain
the low-frequency load independence of the amplifier
while isolating the phase shift caused by the
capacitance at high frequency. At low frequency,
feedback is mainly from the load side of RISO. At high
frequency, the feedback is mainly via the 27-pF
capacitor. The resistor RIN in series with the negative
input is used to stabilize the amplifier and should be
equal to the recommended value of RF at unity gain.
Replacing RIN with a ferrite of similar impedance at
about 100 MHz as shown in Figure 67 gives similar
results with reduced dc offset and low-frequency
noise. (See the ADDITIONAL REFERENCE
MATERIAL section for expanding the usability of
current-feedback amplifiers.)
RF
VS
249 Ω
_
5.11 Ω
+
RISO
100-Ω LOAD
1 kΩ
27 pF
RIN
1 µF
−VS
VS
Placing a small series resistor, RISO, between the
amplifier’s output and the capacitive load, as shown
in Figure 64, is an easy way of isolating the load
capacitance.
RG
49.9 Ω
249 Ω
1 kΩ
VS
_
+
−VS
Figure 64.
VS
100-Ω LOAD
5.11 Ω
1 µF
49.9 Ω
1 kΩ
249 Ω
Figure 66.
VS
Ferrite Bead
_
+
−VS
VS
100-Ω LOAD
1 µF
49.9 Ω
Figure 65.
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
Submit Documentation Feedback
19
THS3091
THS3095
SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008........................................................................................................................................ www.ti.com
RF
VS
VS
1 kΩ
5.11 Ω
+
_
27 pF
FIN
RG
FB
249 Ω
VS
−VS
_
5.11 Ω
+
866 Ω
191 Ω
1 µF
−VS
VS
100-Ω LOAD
866 Ω
49.9 Ω
VS
_
Figure 67.
+
Figure 68 is shown using two amplifiers in parallel to
double the output drive current to larger capacitive
loads. This technique is used when more output
current is needed to charge and discharge the load
faster like when driving large FET transistors.
1 kΩ
VS
249 Ω
24.9 Ω
+
−VS
1 kΩ
VS
VS
249 Ω
_
24.9 Ω
−VS
−VS
Figure 69. PowerFET Drive Circuit
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY AND SETTING
THRESHOLD LEVELS WITH THE
REFERENCE PIN
The THS3095 features a power-down pin (PD) which
lowers the quiescent current from 9.5 mA down to
500 µA, ideal for reducing system power.
5.11 Ω
_
5.11 Ω
1 nF
5.11 Ω
+
−VS
Figure 68.
Figure 69 shows a push-pull FET driver circuit typical
of ultrasound applications with isolation resistors to
isolate the gate capacitance from the amplifier.
The power-down pin of the amplifier defaults to the
positive supply voltage in the absence of an applied
voltage, putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the negative rail. The threshold voltages for
power-on and power-down are relative to the supply
rails and are given in the specification tables. Above
the Enable Threshold Voltage, the device is on.
Below the Disable Threshold Voltage, the device is
off. Behavior in between these threshold voltages is
not specified.
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and
gain-setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
Figure 70 shows the total system output impedance
which includes the amplifier output impedance in
parallel with the feedback plus gain resistors, which
cumulate to 2380 Ω. Figure 59 shows this circuit
configuration for reference.
20
Submit Documentation Feedback
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
ZOPD − Powerdown Output Impedance − Ω
2500
The recommended mode of operation is to tie the
REF pin to midrail, thus setting the enable/disable
thresholds to Vmidrail + 2.0 V and Vmidrail + 0.8 V
respectively.
VS = ±15 V and ±5 V
2000
POWER-DOWN THRESHOLD VOLTAGE LEVELS
1500
1000
1.21 kΩ
500
1.21 kΩ
−
+
50 Ω VO
1M
10 M
0
100 k
100 M
1G
SUPPLY
VOLTAGE (V)
REFERENCE PIN
VOLTAGE (V)
ENABLE
LEVEL (V)
DISABLE
LEVEL (V)
±15, ±5
0.0
2.0
0.8
±15
2.0
4.0
2.8
±15
–2.0
0.0
–1.2
±5
1.0
3.0
1.8
±5
–1.0
1.0
–0.2
+30
15
17
15.8
+10
5.0
7.0
5.8
f − Frequency − Hz
Figure 70. Power-Down Output Impedance vs
Frequency
As with most current feedback amplifiers, the internal
architecture places some limitations on the system
when in power-down mode. Most notably is the fact
that the amplifier actually turns ON if there is a ±0.7 V
or greater difference between the two input nodes
(V+ and V–) of the amplifier. If this difference
exceeds ±0.7 V, the output of the amplifier creates an
output voltage equal to approximately [(V+ – V–) –0.7
V] × Gain. This also implies that if a voltage is applied
to the output while in power-down mode, the V– node
voltage is equal to VO(applied) × RG/(RF + RG). For low
gain configurations and a large applied voltage at the
output, the amplifier may actually turn ON due to the
aforementioned behavior.
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
POWER-DOWN REFERENCE PIN
OPERATION
In addition to the power-down pin, the THS3095
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the PD pin. In most split-supply
applications, the reference pin is connected to
ground. In either case, the user needs to be aware of
voltage-level thresholds that apply to the power-down
pin. The tables below show examples and illustrate
the relationship between the reference voltage and
the power-down thresholds. In the table, the threshold
levels are derived by the following equations:
PD ≤ REF + 0.8 V for disable
PD ≥ REF + 2.0 V for enable
where the usable range at the REF pin is
VS– ≤ VREF ≤ (VS+ – 4 V).
Note that if the REF pin is left unterminated, it will
float to the positive rail and will fall outside of the
recommended operating range given above (VS– ≤
VREF ≤ VS+ – 4 V). As a result, it will no longer serve
as a reliable reference for the PD pin and the
enable/disable thresholds given above will no longer
apply. If the PD pin is also left unterminated, it will
also float to the positive rail and the device will be
enabled. If balanced, split supplies are used (±Vs)
and the REF and PD pins are grounded, the device
will be disabled.
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Achieving
optimum
performance
with
a
high-frequency amplifier, like the THS3091/5,
requires careful attention to board layout parasitic and
external component types.
Recommendations that optimize performance include:
• Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
• Minimize the distance [< 0.25 inch (6,35 mm)]
from the power supply pins to high-frequency
0.1-µF and 100-pF decoupling capacitors. At the
device pins, the ground and power plane layout
should not be in close proximity to the signal I/O
pins. Avoid narrow power and ground traces to
minimize inductance between the pins and the
decoupling capacitors. The power supply
connections should always be decoupled with
these capacitors. Larger (6.8 µF or more)
tantalum decoupling capacitors, effective at lower
frequency, should also be used on the main
supply pins. These may be placed somewhat
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
Submit Documentation Feedback
21
THS3091
THS3095
SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008........................................................................................................................................ www.ti.com
•
•
22
farther from the device and may be shared among
several devices in the same area of the PC board.
Careful selection and placement of external
components
preserve
the
high-frequency
performance of the THS3091/5. Resistors should
be a low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Again,
keep their leads and PC board trace length as
short as possible. Never use wirebound type
resistors in a high-frequency application. Because
the output pin and inverting input pins are the
most sensitive to parasitic capacitance, always
position the feedback and series output resistors,
if any, as close as possible to the inverting input
pins and output pins. Other network components,
such as input termination resistors, should be
placed close to the gain-setting resistors. Even
with a low parasitic capacitance shunting the
external resistors, excessively high resistor values
can create significant time constants that can
degrade performance. Good axial metal-film or
surface-mount resistors have approximately 0.2
pF in shunt with the resistor. For resistor values >
2 kΩ, this parasitic capacitance can add a pole
and/or a zero that can effect circuit operation.
Keep resistor values as low as possible,
consistent with load-driving considerations.
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces [0.05 inch (1,3 mm) to 0.1
inch (2,54 mm)] should be used, preferably with
ground and power planes opened up around
them. Estimate the total capacitive load and
determine if isolation resistors on the outputs are
necessary. Low parasitic capacitive loads (< 4 pF)
may not need an RS because the THS3091/5 are
nominally compensated to operate with a 2-pF
parasitic load. Higher parasitic capacitive loads
without an RS are allowed as the signal gain
increases (increasing the unloaded phase
margin). If a long trace is required, and the 6-dB
Submit Documentation Feedback
•
signal loss intrinsic to a doubly terminated
transmission line is acceptable, implement a
matched impedance transmission line using
microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline layout
techniques). A 50-Ω environment is not necessary
onboard, and in fact, a higher impedance
environment improves distortion as shown in the
distortion versus load plots. With a characteristic
board trace impedance based on board material
and trace dimensions, a matching series resistor
into the trace from the output of the THS3091/5 is
used as well as a terminating shunt resistor at the
input of the destination device. Remember also
that the terminating impedance is the parallel
combination of the shunt resistor and the input
impedance of the destination device; this total
effective impedance should be set to match the
trace impedance. If the 6-dB attenuation of a
doubly
terminated
transmission
line
is
unacceptable, a long trace can be seriesterminated at the source end only. Treat the trace
as a capacitive load in this case. This does not
preserve signal integrity as well as a doubly
terminated line. If the input impedance of the
destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
Socketing a high-speed part like the THS3091/5 is
not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket
can create an extremely troublesome parasitic
network which can make it almost impossible to
achieve a smooth, stable frequency response.
Best results are obtained by soldering the
THS3091/5 parts directly onto the board.
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
PowerPAD™ DESIGN CONSIDERATIONS
The
THS3091/5
are
available
in
a
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
leadframe on which the die is mounted [see
Figure 71(a) and Figure 71(b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see
Figure 71(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good
thermal path away from the thermal pad. Note that
devices such as the THS3091/5 have no electrical
connection between the PowerPAD and the die.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other
heat-dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward
mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
Figure 71. Views of Thermal Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
0.300
(7,62)
0.100
(2,54)
0.035
(0,89)
0.010
(0,254)
0.026
(0,66)
0.030
(0,732)
0.060
(1,52)
0.140
(3,56)
0.176
(4,47)
0.050
(1,27)
0.060
(1,52)
0.010
(0.254)
vias
0.035
(0,89)
0.080
(2,03)
All Units in inches (millimeters)
Figure 72. DDA PowerPAD PCB Etch and Via
Pattern
PowerPAD™ LAYOUT CONSIDERATIONS
1. PCB with a top-side etch pattern is shown in
Figure 72. There should be etch for the leads as
well as etch for the thermal pad.
2. Place 13 holes in the area of the thermal pad.
These holes should be 0.01 inch (0,254 mm) in
diameter. Keep them small so that solder wicking
through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. This helps dissipate the heat generated by
the THS3091/5 IC. These additional vias may be
larger than the 0.01-inch (0,254 mm) diameter
vias directly under the thermal pad. They can be
larger because they are not in the thermal pad
area to be soldered so that wicking is not a
problem.
4. Connect all holes to the internal ground plane.
Note that the PowerPAD is electrically isolated
from the silicon and all leads. Connecting the
PowerPAD to any potential voltage such as VS– is
acceptable as there is no electrical connection to
the silicon.
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This makes the soldering of
vias that have plane connections easier. In this
application, however, low thermal resistance is
desired for the most efficient heat transfer.
Therefore, the holes under the THS3091/5
PowerPAD
package
should
make
their
connection to the internal ground plane with a
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
Submit Documentation Feedback
23
THS3091
THS3095
SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008........................................................................................................................................ www.ti.com
complete
connection
around
the
entire
circumference of the plated-through hole.
6. The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its 13 holes exposed. The bottom-side
solder mask should cover the 13 holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This results in a part
that is properly installed.
above and detailed in the PowerPAD application note
(SLMA002). The following graph also illustrates the
effect of not soldering the PowerPAD to a PCB. The
thermal impedance increases substantially which may
cause serious heat and performance issues. Be sure
to always solder the PowerPAD to the PCB for
optimum performance.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS3091/5 incorporates automatic thermal
shutoff protection. This protection circuitry shuts down
the amplifier if the junction temperature exceeds
approximately 160°C. When the junction temperature
reduces to approximately 140°C, the amplifier turns
on again. But, for maximum performance and
reliability, the designer must ensure that the design
does not exceed a junction temperature of 125°C.
Between 125°C and 150°C, damage does not occur,
but the performance of the amplifier begins to
degrade and long-term reliability suffers. The thermal
characteristics of the device are dictated by the
package and the PC board. Maximum power
dissipation for a given package can be calculated
using the following formula.
T * TA
P Dmax + max
q JA
where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the
case (°C/W).
θCA is the thermal coefficient from the case to ambient air
(°C/W).
For systems where heat dissipation is more critical,
the THS3091 and THS3095 are offered in an 8-pin
SOIC (DDA) with PowerPAD package. The thermal
coefficient for the PowerPAD packages are
substantially improved over the traditional SOIC.
Maximum power dissipation levels are depicted in the
graph for the available packages. The data for the
PowerPAD packages assume a board layout that
follows the PowerPAD layout guidelines referenced
24
Submit Documentation Feedback
Results are With No Air Flow and PCB Size =
3 inches x 3 inches (76,2 mm x 76,2 mm)
Figure 73. Maximum Power Distribution vs
Ambient Temperature
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to consider not only quiescent power
dissipation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem.
DESIGN TOOLS
Evaluation Fixtures, Spice Models, and
Application Support
Texas Instruments is committed to providing its
customers with the highest quality of applications
support. To support this goal, an evaluation board
has been developed for the THS3091/5 operational
amplifier. The board is easy to use, allowing for
straightforward evaluation of the device. The
evaluation board can be ordered through the Texas
Instruments Web site, www.ti.com, or through your
local Texas Instruments sales representative.
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This is
particularly true for video and RF-amplifier circuits
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
where parasitic capacitance and inductance can have
a major effect on circuit performance. A SPICE model
for the THS3091/5 is available through the Texas
Instruments Web site (www.ti.com). The Product
Information Center (PIC) is also available for design
assistance and detailed product information. These
models do a good job of predicting small-signal ac
and transient performance under a wide variety of
operating conditions. They are not intended to model
the distortion characteristics of the amplifier, nor do
they attempt to distinguish between the package
types in their small-signal ac performance. Detailed
information about what is and is not modeled is
contained in the model file itself.
PIN8
(2)
REF
(2)
JP1
(2)
C9
J4
VS−
J5
GND
TP1
FB1
C3
6.8 µF
(2)
C10
(2)
JP2
J6
VS+
TP2
(2) THS3095 EVM Only
FB2
VS−
VS+
+
C4
0.1 µF
+
R9
Figure 75. THS3091 EVM Board Layout
(Top Layer)
C7
0.1 µF
C6
6.8 µF
J1
R3
R4
R1 249 Ω
0Ω
1 kΩ
PIN8
VS+
J2
2
7 8 1
6
3
R2
49.9 Ω
R5
REF
Open
R7
49.9 Ω
4
5
VS−
J3
R8
Open
R6
Open
THS3091DDA or THS3095DDA
Figure 74. THS3091 EVM Circuit Configuration
Figure 76. THS3091 EVM Board Layout
(Second and Third Layers)
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
Submit Documentation Feedback
25
THS3091
THS3095
SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008........................................................................................................................................ www.ti.com
Figure 77. THS3091 EVM Board Layout
(Bottom Layer)
26
Submit Documentation Feedback
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
Table 2. Bill of Materials
THS3091DDA and THS3095DDA EVM (1)
ITEM
DESCRIPTION
1
Bead, Ferrite, 3 A, 80 Ω
2
Cap, 6.8 µF, Tantalum, 50 V, 10%
3
SMD
SIZE
REFERENCE
DESIGNATOR
1206
PCB
QTY
MANUFACTURER'S
PART NUMBER
DISTRIBUTOR'S
PART NUMBER
FB1, FB2
2
(Steward) HI1206N800R-00
(Digi-Key) 240-1010-1-ND
D
C3, C6
2
(AVX) TAJD685K050R
(Garrett) TAJD685K050R
Cap, 0.1 µF, ceramic, X7R, 50 V
0805
C9, C10
2 (2)
(AVX) 08055C104KAT2A
(Garrett) 08055C104KAT2A
4
Cap, 0.1 µF, ceramic, X7R, 50 V
0805
C4, C7
2
(AVX) 08055C104KAT2A
(Garrett) 08055C104KAT2A
5
Resistor, 0 Ω, 1/8 W, 1%
0805
R9
1 (2)
(KOA) RK73Z2ALTD
(Garrett) RK73Z2ALTD
6
Resistor, 249 Ω, 1/8 W, 1%
0805
R3
1
(KOA) RK73H2ALTD2490F
(Garrett) RK73H2ALTD2490F
7
Resistor, 1 kΩ, 1/8 W, 1%
0805
R4
1
(KOA) RK73H2ALTD1001F
(Garrett) RK73H2ALTD1001F
8
Open
1206
R8
1
9
Resistor, 0 Ω, 1/4 W, 1%
1206
R1
1
(KOA) RK73Z2BLTD
(Garrett) RK73Z2BLTD
10
Resistor, 49.9 Ω, 1/4 W, 1%
1206
R2, R7
2
(KOA) RK73Z2BLTD49R9F
(Garrett) RK73Z2BLTD49R9F
11
Open
2512
R5, R6
2
12
Header, 0.1-inch (2,54 mm) centers,
0.025-inch (6,35 mm) square pins
JP1, JP2
(Sullins) PZC36SAAN
(Digi-Key) S1011-36-ND
13
Connector, SMA PCB Jack
J1, J2, J3
3
(Amphenol) 901-144-8RFX
(Newark) 01F2208
14
Jack, banana receptacle,
0.25-inch (6,35 mm) dia. hole
J4, J5, J6
3
(SPC) 813
(Newark) 39N867
15
Test point, black
TP1, TP2
2
(Keystone) 5001
(Digi-Key) 5001K-ND
16
Standoff, 4-40 hex,
0.625-inch (15,9 mm) length
4
(Keystone) 1808
(Newark) 89F1934
17
Screw, Phillips, 4-40,
0.25-inch (6,35 mm)
4
SHR-0440-016-SN
18
IC, THS3091(3)
IC, THS3095(2)
1
(TI) THS3091DDA (3)
(TI) THS3095DDA (2)
19
Board, printed-circuit
1
(TI) EDGE # 6446289 Rev. A (3)
(TI) EDGE # 6446290 Rev. A (2)
(1)
(2)
(3)
U1
2
(2)
All items are designated for both the THS3091DDA and THS3095 EVMs unless otherwise noted.
THS3095 EVM only.
THS3091 EVM only.
ADDITIONAL REFERENCE MATERIAL
• PowerPAD™ Made Easy, application brief (SLMA004)
• PowerPAD™ Thermally Enhanced Package, technical brief (SLMA002)
• Voltage Feedback vs Current Feedback Amplifiers, (SLVA051)
• Current Feedback Analysis and Compensation (SLOA021)
• Current Feedback Amplifiers: Review, Stability, and Application (SBOA081)
• Effect of Parasitic Capacitance in Op Amp Circuits (SLOA013)
• Expanding the Usability of Current-Feedback Amplifiers, 3Q 2003
(www.ti.com/sc/analogapps).
Analog
Applications
Journal
space
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February, 2007) to Revision G ............................................................................................ Page
•
•
•
•
Changed common-mode rejection ratio specifications from 78 dB (typ) to 69 dB (typ); from 68 dB at +25°C to 62
dB; from 65 dB at (0°C to +70°C) and (–40°C to +85°C) to 59 dB. ......................................................................................
Corrected load resistor value for output current specification (sourcing and sinking) from RL = 40 Ω to RL = 10 Ω ............
Changed output current (sourcing) specifications from 200 mA (typ) to 180 mA (typ); from 160 mA at +25°C to 140
mA; from 140 mA at (0°C to +70°C) and (–40°C to +85°C) to 120 mA ................................................................................
Corrected output current (sinking) specifications from 180 mA (typ) to –160 mA (typ); from 150 mA at +25°C to –140
mA; from 125 mA at (0°C to +70°C) and (–40°C to +85°C) to –120 mA ..............................................................................
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): THS3091 THS3095
Submit Documentation Feedback
4
7
7
7
27
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
THS3091D
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
3091
THS3091DDA
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
3091
THS3091DDAG3
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
3091
THS3091DDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
3091
THS3091DDARG3
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
3091
THS3091DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
3091
THS3091DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
3091
THS3091DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
3091
THS3095D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
3095
THS3095DDA
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
3095
THS3095DDAG4
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
3095
THS3095DDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
3095
THS3095DDARG3
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
3095
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
3095
THS3095DG4
ACTIVE
SOIC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
THS3091DDAR
SO
Power
PAD
THS3091DR
THS3095DDAR
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DDA
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SO
Power
PAD
DDA
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Aug-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS3091DDAR
SO PowerPAD
DDA
8
2500
367.0
367.0
35.0
THS3091DR
SOIC
D
8
2500
367.0
367.0
35.0
THS3095DDAR
SO PowerPAD
DDA
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated