Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPD1E05U06, TPD4E05U06, TPD6E05U06 SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 TPDxE05U06 1, 4, 6 Channel ESD Protection Device for Super-Speed (up to 6 GBPS) Interface 1 Features 3 Description • The TPDxE05U06 is a family of unidirectional Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diodes with ultra-low capacitance. Each device can dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 international standard. The TPDxE05U06's ultra-low loading capacitance makes it ideal for protecting any high-speed signal pins. IEC 61000-4-2 Level 4 ESD Protection – ±12-kV Contact Discharge – ±15-kV Air Gap Discharge IEC 61000-4-4 EFT Protection – 80 A (5/50 ns) IEC 61000-4-5 Surge Protection – 2.5 A (8/20 µs) IO Capacitance 0.42 pF to 0.5 pF (Typ) DC Breakdown Voltage 6.5 V (Min) Ultra low Leakage Current 10 nA (Max) Low ESD Clamping Voltage Industrial Temperature Range: –40°C to 125°C Easy Straight-Through Routing Packages 1 • • • • • • • • 2 Applications • • • • • • • • • HDMI 1.4b HDMI 2.0 USB 3.0 MHL LVDS Interfaces DisplayPort PCI-Express® eSata Interfaces V-by-One® HS Typical applications for TPDxE05U06 includes high speed signal lines in HDMI 1.4b, HDMI 2.0, USB 3.0, MHL, LVDS, DisplayPort, PCI-Express®, eSata, and V-by-One® HS. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPD1E05U06 X2SON (2) 1.00 mm × 0.60 mm TPD4E05U06 USON (10) 2.50 mm × 1.00 mm TPD6E05U06 USON (14) 3.50 mm × 1.35 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Simplified Schematic TPD4E05U06 TPD4E05U06 Functional Block Diagram 4 5 GND GND 3 1 2 8 D0+ D1+ Connector HDMI Controller D0- D1D2+ D1+ D1- D2+ D2- D2CLK+ CLK- GND GND TPD4E05U06 3 1 2 4 5 GND 8 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD1E05U06, TPD4E05U06, TPD6E05U06 SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 4 5 7.1 7.2 7.3 7.4 7.5 7.6 5 5 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 8.1 Overview ................................................................... 9 8.2 Functional Block Diagrams ....................................... 9 8.3 Feature Description................................................. 10 8.4 Device Functional Modes........................................ 10 9 Application and Implementation ........................ 11 9.1 Application Information............................................ 11 9.2 Typical Applications ................................................ 11 10 Layout................................................................... 15 10.1 Layout Guidelines ................................................. 15 10.2 Layout Example .................................................... 15 11 Device and Documentation Support ................. 17 11.1 11.2 11.3 11.4 11.5 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 17 17 17 17 17 12 Mechanical, Packaging, and Orderable Information ........................................................... 17 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (May 2015) to Revision I Page • Added Trademarks ................................................................................................................................................................ 1 • Corrected TPD6E05U06 Pin 13 name ................................................................................................................................... 4 • Corrected TLP definition ........................................................................................................................................................ 6 Changes from Revision G (July 2014) to Revision H Page • Added Additional Application.................................................................................................................................................. 1 • Updated with HDMI 2.0 Eye Diagrams................................................................................................................................. 12 Changes from Revision F (November 2013) to Revision G Page • Added 61000-4-4 EFT compliance......................................................................................................................................... 1 • Added Handling Ratings table. ............................................................................................................................................... 5 • Added Thermal Information table. ......................................................................................................................................... 5 • Added Detailed Description section. ...................................................................................................................................... 9 • Added Application and Implementation section. ................................................................................................................. 11 • Added Layout section. ......................................................................................................................................................... 15 Changes from Original (December 2012) to Revision A • Page Added TPS2EUSB30A part to document. .............................................................................................................................. 1 Changes from Revision A (December 2012) to Revision B Page • Added Insertion Loss Graphic. ............................................................................................................................................... 8 • Added Eye Diagrams............................................................................................................................................................ 12 2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 TPD1E05U06, TPD4E05U06, TPD6E05U06 www.ti.com SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 Changes from Revision B (January 2013) to Revision C Page • Changed IO Capacitance range ............................................................................................................................................. 1 • Changed test conditions and typ values for Vclamp ................................................................................................................. 6 • Added typ RDYN values for DQA and RVZ packages ............................................................................................................. 6 • Added CL values for DQA and RVZ packages ....................................................................................................................... 6 • Changed CURRENT vs VOLTAGE graphic ........................................................................................................................... 7 • Changed Insertion Loss graphic............................................................................................................................................. 8 • Changed HDMI Eye Diagrams ............................................................................................................................................. 12 Changes from Revision C (March 2013) to Revision D Page • Updated Title. ......................................................................................................................................................................... 1 • Removed Ordering Information table. .................................................................................................................................... 4 Changes from Revision D (August 2013) to Revision E Page • Updated document formatting. ............................................................................................................................................... 1 • Added additional application................................................................................................................................................... 1 Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 3 TPD1E05U06, TPD4E05U06, TPD6E05U06 SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 www.ti.com 6 Pin Configuration and Functions NC 1 14 D1+ NC 2 13 D1– I/O D1+ 1 10 N.C. D1– 2 9 N.C. NC 3 12 1 D2+ GND 3 8 GND NC 4 11 D2– 2 D2+ 4 7 N.C. GND 5 10 GND GND D2– 5 6 N.C. NC 6 9 D3+ NC 7 8 D3– DPY TOP VIEW 1 mm x 0.6 mm x 0.35 mm (0.65-mm pitch) DQA TOP VIEW 2.5 mm x 1 mm x 0.5 mm (0.5-mm pitch) RVZ TOP VIEW 3.5 mm x 1.35 mm x 0.5 mm (0.5-mm pitch) Pin Functions TPD1E05U06 DPY PIN NAME X2SON I/O DESCRIPTION I/O 1 I/O ESD Protected Channel (1) GND 2 Ground Ground; Connect to ground (1) Place as close to the connector as possible. Pin Functions TPD4E05U06 DQA PIN NAME USON I/O DESCRIPTION D1+ 1 I/O ESD Protected Channel (1) D1- 2 I/O ESD Protected Channel (1) D2+ 4 I/O ESD Protected Channel (1) D2- 5 I/O ESD Protected Channel (1) NC 6, 7, 9, 10 – 3, 8 Ground GND (1) Not Connected; Used for optional straight-through routing. Can be left floating or grounded. Ground; Connect to ground Place as close to the connector as possible. Pin Functions TPD6E05U06 RVZ PIN NAME USON I/O DESCRIPTION D1+ 14 I/O ESD Protected Channel (1) D1- 13 I/O ESD Protected Channel (1) D2+ 12 I/O ESD Protected Channel (1) D2- 11 I/O ESD Protected Channel (1) D3+ 9 I/O ESD Protected Channel (1) D3- 8 I/O ESD Protected Channel (1) NC 1, 2, 3, 4, 6, 7 – 5, 10 Ground GND (1) 4 Not Connected; Used for optional straight-through routing. Can be left floating or grounded. Ground; Connect to ground Place as close to the connector as possible. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 TPD1E05U06, TPD4E05U06, TPD6E05U06 www.ti.com SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 7 Specifications 7.1 Absolute Maximum Ratings (1) (2) (3) over operating free-air temperature range (unless otherwise noted) Operating Temperature Electrical Fast Transient Peak Pulse Tstg (1) (2) (3) (4) MIN MAX UNIT -40 125 °C 80 A 2.5 A IEC 61000-4-4 (5/50 ns) IEC 61000-4-5 Current (tp – 8/20 µs) (4) IEC 61000-4-5 Power (tp – 8/20 µs) (4) Storage temperature range –65 40 W 155 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. Absolute maximum ratings apply over recommended junction temperature range. Voltages are with respect to GND unless otherwise noted. Measured at 25°C. 7.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (2) UNIT ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) Electrostatic discharge 61000-4-2 ESD ratings (1) (1) ±1500 Contact ±12000 Air ±15000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±4000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1500 V may actually have higher performance. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VIO Input pin voltage TA Operating free-air temperature MIN MAX 0 5.5 UNIT V –40 125 °C 7.4 Thermal Information THERMAL METRIC (1) TPD1E05U06 TPD4E05U06 TPD6E05U06 DPY (X2SON) DQA (USON) RVZ (USON) 2 PINS 10 PINS 14 PINS 697.3 327 197.9 °C/W 471 189.5 119.1 °C/W UNIT RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance 575.9 257.7 92.6 °C/W ψJT Junction-to-top characterization parameter 175.7 60.9 22 °C/W ψJB Junction-to-board characterization parameter 575.1 257 91.6 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 5 TPD1E05U06, TPD4E05U06, TPD6E05U06 SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 www.ti.com 7.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VRWM Reverse stand-off voltage IIO < 10 µA VBR Break-down Voltage IIO = 1 mA Vclamp Clamp voltage MIN 6 I = 1 A, TLP, I/O to ground (1) 10 I = 5 A, TLP, I/O to ground (1) 14 (1) 3 I = 1 A, TLP, ground to I/O I = 5 A, TLP, ground to I/O (1) ILEAK Leakage current RDYN TYP UNIT 5.5 V 8.5 V V 7 VIO = 2.5 V 0.01 (2) 0.8 DPY package dynamic resistance I/O to GND GND to I/O (2) 0.8 DQA package dynamic resistance I/O to GND (2) 0.8 (2) 0.8 RVZ package dynamic resistance I/O to GND (2) 0.8 GND to I/O (2) 0.8 GND to I/O MAX 10 nA Ω Ω Ω Capacitance ΔCIO-TOGND CCROSS (1) (2) (3) 6 VIO = 2.5 V, f = 1 MHz, I/O to GND Line capacitance (3) CL TPD1E05U06 DPY package 0.42 TPD4E05U06 DQA package 0.5 TPD6E05U06 RVZ package 0.47 pF Variation of channel input capacitance GND Pin = 0 V, F = 1 GHz, VBIAS = 2.5 V, channel_x pin to GND – channel_y pin to GND 0.05 0.07 pF Channel to channel input capacitance GND Pin = 0 V, F = 1 GHz, VBIAS = 2.5 V, between channel pins 0.01 0.06 pF Transmission Line Pulse (TLP) with 100 ns width, 200 ps rise time. Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A. Capacitance data is taken at 25°C. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 TPD1E05U06, TPD4E05U06, TPD6E05U06 www.ti.com SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 7.6 Typical Characteristics 3.5 1.0 0.8 50 Current Power 3.0 45 40 0.6 2.5 0.2 0.0 ±0.2 ±0.4 35 Power (W) Current (A) Current (mA) 0.4 30 2.0 25 1.5 20 15 1.0 10 ±0.6 0.5 ±0.8 5 0.0 ±1.0 ±2 0 ±1 1 2 3 4 5 6 7 8 9 Voltage (V) 10 0 0 ±5 5 10 15 20 25 30 35 40 45 50 Time (s) C001 C002 Figure 2. Surge Curve (tp = 8/20 μs), Pin IO to GND Figure 1. DC Voltage Sweep I-V Curve 25 35 30 20 20 Current (A) Current (A) 25 15 10 5 15 10 5 0 0 ±5 0 5 10 15 20 25 30 35 Voltage (V) 0 40 5 10 15 20 25 Voltage (V) C003 Figure 3. Positive TLP Plot IO to GND C008 Figure 4. Negative TLP Plot IO to GND 300 80 70 250 Voltage (V) Current (pA) 60 200 150 100 50 40 30 20 10 50 0 0 ±10 ±40 ±20 0 20 40 60 80 100 Temperature (C) Figure 5. Leakage vs Temperature Copyright © 2012–2015, Texas Instruments Incorporated 120 0 25 50 75 100 125 150 175 Time (ns) C004 200 C005 Figure 6. +8-kV IEC Waveform Submit Documentation Feedback Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 7 TPD1E05U06, TPD4E05U06, TPD6E05U06 SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 www.ti.com Typical Characteristics (continued) 10 0 0 ±1 ±2 ±10 ±3 Insertion Loss (dB) Voltage (V) ±20 ±30 ±40 ±50 ±60 ±4 ±5 ±6 ±7 ±8 ±9 ±70 ±10 ±80 ±11 ±90 0 25 50 75 100 125 150 175 Time (ns) 200 ±12 100k 100M 1G 1000M 10G 10000M C007 Figure 8. TPD1E05U06 Insertion Loss 0 ±1 ±1 Insertion Loss (dB) Insertion Loss (dB) Figure 7. –8-kV IEC Waveform ±2 ±3 ±4 ±5 ±2 ±3 ±4 ±5 1M 10M 100M 1G 1000M Frequency (Hz) Figure 9. TPD4E05U06 Insertion Loss 8 10M Frequency (Hz) 0 ±6 100k 1M C006 Submit Documentation Feedback 10G 10000M C009 ±6 100k 1M 10M 100M 1G 1000M Frequency (Hz) 10G 10000M C010 Figure 10. TPD6E05U06 Insertion Loss Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 TPD1E05U06, TPD4E05U06, TPD6E05U06 www.ti.com SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 8 Detailed Description 8.1 Overview The TPDxE05U06 is a family of unidirectional Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diodes with ultra-low capacitance. Each device can dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 international standard. The TPDxE05U06's ultra-low loading capacitance makes it ideal for protecting any high-speed signal pins. 8.2 Functional Block Diagrams I/O GND Figure 11. TPD1E05U06 Block Diagram D1+ D1- D2+ D2- GND Figure 12. TPD4E05U06 Block Diagram D1+ D1- D2+ D2- D3+ D3- GND Figure 13. TPD4E05U06 Block Diagram Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 9 TPD1E05U06, TPD4E05U06, TPD6E05U06 SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 www.ti.com 8.3 Feature Description The TPDxE05U06 is a family of unidirectional Transient Voltage Suppressor (TVS) Electrostatic Discharge (ESD) protection diodes with ultra-low capacitance. Each device can dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 international standard. The TPDxE05U06's ultra-low loading capacitance makes it ideal for protecting any high-speed signal pins. 8.3.1 ±15-kV IEC61000-4-2 Level 4 ESD Protection The I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air. An ESD/surge clamp diverts the current to ground. 8.3.2 IEC61000-4-4 EFT Protection The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50 Ω impedance). An ESD/surge clamp diverts the current to ground. This has been validated on the TPD4E05U06 only. 8.3.3 IEC61000-4-5 Surge Protection The I/O pins can withstand surge events up to 2.5 A and 40 W (8/20 µs waveform). An ESD/surge clamp diverts this current to ground. 8.3.4 I/O Capacitance The capacitance between each I/O pin to ground is 0.42 pF (TPD1E05U06), 0.5 pF (TPD4E05U06) or 0.47 pF (TPD6E05U06). These devices support data rates up to 6.0 Gbps. 8.3.5 DC Breakdown Voltage The DC breakdown voltage of each I/O pin is a minimum of 6 V. This ensures that sensitive equipment is protected from surges above the reverse standoff voltage of 5 V. 8.3.6 Ultra-Low Leakage Current The I/O pins feature an ultra-low leakage current of 10 nA (max) with a bias of 2.5 V. 8.3.7 Low ESD Clamping Voltage The I/O pins feature an ESD clamp that is capable of clamping the voltage to 10 V (IPP = 1 A). 8.3.8 Industrial Temperature Range This device features an industrial operating range of –40°C to 125°C. 8.3.9 Easy Flow-Through Routing The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers flow-through routing, requiring minimal modification to an existing layout. 8.4 Device Functional Modes TPDxE05U06 is a passive integrated circuit that triggers when voltages are above VBR or below the lower diodes Vf (–0.6 V). During ESD events, voltages as high as ±15 kV (air) can be directed to ground via the internal diode network. Once the voltages on the protected line fall below the trigger levels of TPDxE05U06 (usually within 10’s of nano-seconds) the device reverts to passive. 10 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 TPD1E05U06, TPD4E05U06, TPD6E05U06 www.ti.com SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information TPDxE05U06 is a diode type TVS which is typically used to provide a path to ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC. 9.2 Typical Applications 9.2.1 HDMI 2.0 Application TPD4E05U06DQA HOT PLUG 1 UTILITY 2 D2+ 1 10 D2- 2 9 3 8 4 7 5 6 UTI_CON TMDS D2+ 3 D2- 5V Source D1+ D1+ TMDS_GND 4 D2+ D1- D1- TMDS D2- 5 HDMI Connector TMDS D1+ 6 TPD4E05U06DQA TMDS_GND 7 TMDS D1- 8 D0+ 1 10 D0- 2 9 3 8 4 7 5 6 D0+ D0- TMDS D0+ 9 TMDS_GND 10 CLK+ TMDS D0- 11 CLK- CLK+ CLK- TMDS CLK+ 12 TMDS_GND 13 TPD5S116YFF TMDS CLK- 14 CEC 15 CEC_CON DDC/CEC GND 16 SCL_CON SCL 17 SDA_CON SDA 18 EN GND 20 5V_SYS HPD_CON 0.1 µF SCL_SYS SDA_SYS VCCA 5V_CON P 5V0 19 HDMI Controller CEC_SYS UTI_CON HPD_SYS GND 0.1 µF UTI_CON Figure 14. HDMI 2.0 Schematic Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 11 TPD1E05U06, TPD4E05U06, TPD6E05U06 SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 www.ti.com Typical Applications (continued) 9.2.1.1 Design Requirements For this design example, two TPD4E05U06 devices, and a TPD5S116 are being used in an HDMI 2.0 application. This will provide a complete port protection scheme. Given the HDMI 2.0 application, the following parameters are known. DESIGN PARAMETER VALUE Signal range on Pins 1, 2, 4, or 5 0 V to 5 V Operating Frequency 3.0 GHz 9.2.1.2 Detailed Design Procedure To begin the design process, some parameters must be decided upon; the designer needs to know the following: • Signal range on all the protected lines • Operating frequency 9.2.1.2.1 Signal Range on Pin 1, 2, 4, or 5 TPD4E05U06 has 4 identical protection channels for signal lines. The symmetry of the device provides flexibility when selecting which of the 4 I/O channels will protect which signal lines. Any I/O will support a signal range of 0 to 5.5 V. 9.2.1.3 Application Curves 12 Figure 15. 3.4 Gbps HDMI 1.4 TP1 Eye Diagram Unpopulated EVM Figure 16. 3.4 Gbps HDMI 1.4 TP1 Eye Diagram TPD1E05U06 Figure 17. 3.4 Gbps HDMI 1.4 TP1 Eye Diagram TPD4E05U06 Figure 18. 3.4 Gbps HDMI 1.4 TP1 Eye Diagram TPD6E05U06 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 TPD1E05U06, TPD4E05U06, TPD6E05U06 www.ti.com SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 Figure 19. 6 Gbps HDMI 2.0 (TP1) Eye Diagram Unpopulated EVM Figure 20. 6 Gbps HDMI 2.0 (TP1) Eye Diagram TPD1E05U06 Figure 21. 6 Gbps HDMI 2.0 (TP1) Eye Diagram TPD4E05U06 Figure 22. 6 Gbps HDMI 2.0 (TP1) Eye Diagram TPD6E05U06 Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 13 TPD1E05U06, TPD4E05U06, TPD6E05U06 SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 www.ti.com 9.2.2 HDMI 2.0 Application 1 TPD1E05U06 1 TPD1E05U06 1 TPD1E05U06 2 1 GND 2 GND GND GND TPD1E05U06 2 2 D0D1+ Connector HDMI 2.0 Controller D0+ D1D2+ D2CLK+ CLK1 TPD1E05U06 1 TPD1E05U06 1 2 2 GND GND 2 1 TPD1E05U06 GND GND TPD1E05U06 2 Figure 23. HDMI 2.0 Schematic 9.2.2.1 Design Requirements For this design example, the TPD1E05U06 and the TPD5S116 will be used to protect the data pairs and control lines of the HDMI 2.0 connection. This will provide full HDMI 2.0 port protection. Given the HDMI 2.0 application, the following parameters are known. DESIGN PARAMETER VALUE Signal Range on Data Lines 0 V to 5 V Operating Frequency 3 GHz 9.2.2.2 Detailed Design Procedure To begin the design process, some parameters must be decided upon; the designer needs to know the following: • Signal range on all the protected lines • Operating frequency 9.2.2.2.1 Signal Range TPD1E05U06 has 1 protection channel for signal lines, supporting a signal range of 0 to 5.5 V. 9.2.2.2.2 Operating Frequency The TPD1E05U06 has 0.42 pF of capacitance, which supports HDMI 2.0 data rates. 9.2.2.3 Application Curves Refer to Application Curves 14 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 TPD1E05U06, TPD4E05U06, TPD6E05U06 www.ti.com SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 10 Layout 10.1 Layout Guidelines • • • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. Route the protected traces as straight as possible. Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. 10.2 Layout Example 10.2.1 TPD4E05U06 Layout Example This application is typical of an HDMI 1.4 layout. Clk+ Clk- D0+ D0- D1+ D1- D2+ D2- VIA to GND Plane D1+ NC NC NC D1- NC D0+ D0+ NC NC D0- GND D0- GND NC GND D1+ NC GND D1- Figure 24. TPD4E05U06 Layout Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 15 TPD1E05U06, TPD4E05U06, TPD6E05U06 SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 www.ti.com Layout Example (continued) 10.2.2 TPD1E05U06 Layout Example This application is typical of an HDMI 2.0 layout. Clk+ Clk- GND GND I/O I/O D0+ D0GND GND I/O I/O GND I/O GND I/O GND I/O GND I/O D2+ D2- D1+ D1- VIA to GND Plane Figure 25. TPD1E05U06 Layout 16 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 TPD1E05U06, TPD4E05U06, TPD6E05U06 www.ti.com SLVSBO7I – DECEMBER 2012 – REVISED JULY 2015 11 Device and Documentation Support 11.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPD1E05U06 Click here Click here Click here Click here Click here TPD4E05U06 Click here Click here Click here Click here Click here TPD6E05U06 Click here Click here Click here Click here Click here 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. PCI-Express is a registered trademark of PCI-SIG . V-by-One is a registered trademark of Thine Electronics, Inc. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06 17 PACKAGE OPTION ADDENDUM www.ti.com 17-Sep-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TPD1E05U06DPYR ACTIVE X1SON DPY 2 10000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C1 ~ C6) TPD1E05U06DPYT ACTIVE X1SON DPY 2 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C1 ~ C6) TPD4E05U06DQAR ACTIVE USON DQA 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BR BRY TPD6E05U06RVZR ACTIVE USON RVZ 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (BVL ~ BVY) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 17-Sep-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF TPD4E05U06 : • Automotive: TPD4E05U06-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jun-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPD1E05U06DPYR X1SON DPY 2 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10000 180.0 9.5 0.66 1.15 0.66 2.0 8.0 Q1 TPD1E05U06DPYT X1SON DPY 2 250 180.0 9.5 0.66 1.15 0.66 2.0 8.0 Q1 TPD4E05U06DQAR USON DQA 10 3000 180.0 9.5 1.23 2.7 0.7 4.0 8.0 Q1 TPD6E05U06RVZR USON RVZ 14 3000 180.0 13.2 1.65 3.8 0.7 4.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jun-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD1E05U06DPYR X1SON DPY 2 10000 184.0 184.0 19.0 TPD1E05U06DPYT X1SON DPY 2 250 184.0 184.0 19.0 TPD4E05U06DQAR USON DQA 10 3000 184.0 184.0 19.0 TPD6E05U06RVZR USON RVZ 14 3000 184.0 184.0 19.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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