TI TPD5S116YFFR

TPD5S116
www.ti.com
SLVSBP3 – DECEMBER 2012
HDMI COMPANION CHIP WITH LEVEL SHIFTING BUFFER 5V LOAD SWITCH AND ESD
PROTECTION
Check for Samples: TPD5S116
FEATURES
APPLICATIONS
•
•
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•
•
•
•
•
•
•
•
•
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Conforms to HDMI Control and 5VOUT
Compliance Tests Without External
Components
Supports HDMI1.3 and HDMI1.4 Standard
Auto-direction Sensing I2C Level Shifter With
One-Shot Circuit to Drive Long HDMI Cable
(750-pF Load)
Back Drive Protection
55mA Load Switch With Short Circuit
Protection
Pb-free and RoHS Compliant (Dark Green
Compliant)
Hot Plug Detect Module With Pull Down
Resistor
Integrated Pull-up and Pull-down Resistors per
HDMI Specification
IEC61000-4-2 ±15kV Contact Rating
IEC61000-4-2 ±15kV Air-gap Rating
Utility Pin ESD Protection for Ethernet and
Audio Return
Cell Phones
eBook
Portable Media Players
Tablet
YFF Package
(Top View)
1.374 mm
2.174 mm
1
A1
A2
A3
B1
B2
B3
C1
C2
C3
D1
D2
D3
E1
E2
E3
Pin Mapping (Top View)
1
2
3
CEC_SYS
VCCA
CEC_CON
B
SCL_SYS
GND
SCL_CON
C
SDA_SYS
EN
SDA_CON
D
5V_SYS
GND
5V_CON
E
HPD_SYS
UTI_CON
HPD_CON
A
DESCRIPTION/ORDERING INFORMATION
TPD5S116 is a single-chip HDMI interface device with auto-direction sensing I2C voltage level shift buffers, 5V
HDMI compliant current limited load switch, hot-plug-detect, and integrated ESD protection clamps for all
connector side pins. The device pin mapping can be routed to either HDMI Type D or Type C connector. An
internal 3.3V node powers the CEC pin, eliminating the need for a 3.3V supply on board.
TPD5S116 integrates all external termination resistors at the HPD, CEC, SCL, and SDA lines. There are three
non-inverting bi-directional translation circuits for the SDA, SCL, and CEC lines. Each has a common power rail
(VCCA) on system side from 1.1 V to 3.6V. A 55mA current limiting switch regulates current sent from 5V_SYS
to 5V_CON. The SCL and SDA pins meet the I2C specification and can drive up to 750 pF capacitive loads,
which exceeds HDMI1.4 specifications. The HPD_CON port has a glitch filter to avoid false detection due to plug
bouncing during the HDMI connector insertion.
The TPD5S116 offers reverse current block at the 5V_CON pin. In fault conditions, such as when two HDMI
transmitters are connected to the same HDMI cable, TPD5S116 ensures that the system is safe from powering
up through external HDMI transmitter. The SCL_CON, SDA_CON, CEC_CON pins also feature reverse-current
blocking, which ensures that the system sees no leakage if an HDMI receiver is connected while the system if
powered off.
The EN pin enables the hot-plug detect and load switch. The level shifters are enabled after a valid HPD signal is
detected.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPD5S116
SLVSBP3 – DECEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
(2)
YFF
(2)
ORDERABLE PART NUMBER
Tape and reel
TPD5S116YFFR
TOP-SIDE MARKING
RE116
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
CIRCUIT SCHEMATIC DIAGRAM
55mA
Load Switch
5V_SYS
5V_CON
EN
1.
2.
470kΩ
VCCA
EN pin enables the load switch and HPD buffer
When EN = H & HPD_CON = H, the 3.3V LDO
for CEC pin, DDC and CEC level shifting buffers
are enabled
5V
HPD_SYS
HPD_CON
UTI_CON
100kΩ
100kΩ
5V_CON
VCCA
Level Shifter
& LDO
Control
ERC
5kΩ
1.75kΩ
3.3V (Internal) 2
LDO
SCL_SYS
SCL_CON
5V_CON
VCCA
VCCA
ERC
5kΩ
26kΩ
CEC_CON
ERC
CEC_SYS
5kΩ
10MΩ
1.75kΩ
SDA_SYS
SDA_CON
Figure 1. Circuit Schematics
2
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APPLICATION INFORMATION
D2+
HOT PLUG 1
UTILITY 2
TPD4E05U06DQA
D2+
D2-
UTI_CON
TMDS D2+ 3
D1+
TMDS_GND 4
D1-
HDMI Connector
TMDS D2- 5
TMDS D1+ 6
1
10
2
9
3
8
4
7
5
6
D2-
5V Source
D1+
D1-
TPD4E05U06DQA
D0+
TMDS_GND 7
D0+
TMDS D1- 8
D0-
TMDS D0+ 9
TMDS_GND 10
CLK+
TMDS D0- 11
CLK-
TMDS CLK+ 12
TMDS_GND 13
1
10
2
9
3
8
4
7
5
6
D0CLK+
CLK-
TPD5S116YFF
TMDS CLK- 14
CEC 15
CEC_CON
CEC_SYS
DDC/CEC GND 16
SCL_CON
SCL_SYS
SCL 17
SDA_CON
SDA_SYS
SDA 18
EN
VCCA
5V_CON
P 5V0 19
5V_SYS
HPD_CON
GND 20
UTI_CON
HPD_SYS
GND
0.1µF
UTI_CON
0.1µF
HDMI Controller
Figure 2. Application Schematics for HDMI Controllers with one GPIO for HDMI Interface Control
HDMI Driver Chip is controlling the TPD5S116 via only one control line (EN). The DDC and CEC level shifting
buffers become active after HPD_CON receives a valid high signal and EN is high.
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Table 1. FUNCTION TABLE – POWER SAVING OPTIONS
4
HPD_CON
EN
VCCA
5V_SYS
5V_CON
Dxx_SYS
CEC_SYS
Pull-ups
DCC_C ON
Pull-ups
CEC_CON
Pull-ups
CEC
LDO
LOAD SW
& HPD
DCC/CEC
VLTs
ICCA
Typ
ICC5V
Typ
Comments
L
L
1.2V –
5.0V
5.0V
High-Z
Off
Off
Off
Off
Off
Off
1µA
2µA
Fully
Disabled
L
H
1.2V –
5.0V
5.0V
5.0V
On
On
Off
Off
On
Off
1µA
30µA
Load Switch
on
H
L
1.2V –
5.0V
5.0V
High-Z
Off
Off
Off
Off
Off
Off
1µA
2µA
Not Valid
State
H
H
1.2V –
5.0V
5.0V
5.0V
On
On
On
On
On
On
24µA
125µA
Fully On
X
X
0V
0V
High-Z
High-Z
High-Z
High-Z
Off
Off
Off
0
0
Power Down
X
X
1.2V –
5.0V
0V
High-Z
High-Z
High-Z
High-Z
Off
Off
Off
1
0
Power Down
X
X
0V
5.0V
High-Z
High-Z
High-Z
High-Z
Off
Off
Off
0
1
Power Down
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SLVSBP3 – DECEMBER 2012
TERMINAL FUNCTIONS
PIN
NAME
YFF
PIN
TYPE
DESCRIPTION
HPD_SYS
E1
Output
HDMI system side: Hot plug detect Output referenced to VCCA. Connect to
HDMI controller Hot plug detect input pin
HPD_CON
E3
Input
CEC_SYS
A1
IO Port
HDMI system side CEC signal pin referenced to VCCA. Connect to HDMI
controller.
CEC_CON
A3
IO Port
HDMI connector side CEC signal pin referenced to internal 3.3V supply.
Connect to HDMI connector CEC pin.
SCL_SYS
B1
IO Port
HDMI system side SCL signal pin referenced to VCCA. Connect to HDMI
controller.
SCL_CON
B3
IO Port
HDMI connector side SCL signal pin referenced to 5V_CON supply. Connect
to HDMI connector SCL pin.
SDA_SYS
C1
IO Port
HDMI system side SDA signal pin referenced to VCCA. Connect to HDMI
controller.
SDA_CON
C3
IO Port
HDMI connector side SDA signal pin referenced to 5V_CON supply.
Connect to HDMI connector SDA pin.
EN
C2
Control Input
HDMI connector side: Hot plug detect Input. Connect directly to HDMI
Connector Hot Plug Detect pin
Disables the load switch and HPD when EN =L. The EN pin is referenced to
VCCA
UTI_CON
E2
IO Port
5V_SYS
D1
Input Power
Protects the HDMI connector's utility pin
System side PCB 5V supply; input of load switch
VCCA
A2
Input Supply
Internal PCB Low Voltage Supply (Same as the HDMI Controller Chip
Supply)
5V_CON
D3
Output Power
HDMI connector side external 5V Supply; output of load switch
GND
B2, D2
Ground
Connect to System Ground Plane
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCCA
Supply voltage range
PARAMETER
–0.3
6.0
V
5V_SYS
Supply voltage range
–0.3
6.0
V
SCL_SYS, SDA_SYS, CEC_SYS,
EN
–0.3
6.0
SCL_CON, SDA_CON, CEC_CON,
HPD_CON
–0.3
6.0
SCL_SYS, SDA_SYS, CEC_SYS,
HPD_SYS
–0.3
6.0
SCL_CON, SDA_CON, CEC_CON,
HPD_CON
–0.3
6.0
SCL_SYS, SDA_SYS,
CEC_SYS,HPD_SYS
–0.3
VCCA +
0.5
SCL_CON, SDA_CON, CEC_CON
–0.3
5V_SYS
+ 0.5
VI
Input voltage range
(2)
VO
Voltage range applied to any output in the highimpedance or power-off state (2) (3)
VO
Voltage range applied to any output in the high or low
state(2)(3)
UNIT
V
V
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
±100
mA
150
°C
Continuous current through 5V_SYS, or GND
Tstg
(1)
(2)
(3)
Storage temperature range
–65
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCCA
Supply Voltage
1.1
5.5
V
5V_SYS
Supply Voltage
4.5
5.5
V
High-level input
voltage
VIH
Low-level input
voltage
VIL
SCL_SYS,
SDA_SYS,
VCCA = 1.1 V to 5.5 V
0.7 × VCCA
VCCA
V
CEC_SYS,
VCCA = 1.1 V to 5.5 V
0.7 × VCCA
VCCA
V
EN
VCCA = 1.1 V to 5.5 V
1.0
VCCA
V
SCL_CON,
SDA_CON,
5V_ SYS = 5.5 V
0.7 × 5V_SYS
5V_SYS
V
CEC_CON
5V_ SYS = 5.5 V
0.7 ×V3P3
V3P3
HPD_CON
5V_ SYS = 5.5 V
2.0
5V_SYS
SCL_SYS,
SDA_SYS,
VCCA = 1.1 V to 5.5 V
–0.5
0.082 × VCCA
V
CEC_SYS,
VCCA = 1.1 V to 5.5 V
–0.5
0.082 × VCCA
V
EN
VCCA = 1.1 V to 5.5 V
–0.5
0.4
V
SCL_CON,
SDA_CON,
5V_ SYS = 5.5 V
–0.5
0.3 × 5V_SYS
V
CEC_CON
5V_ SYS = 5.5 V
–0.5
0.3 × V3P3
V
HPD_CON
5V_ SYS = 5.5 V
0
0.8
V
–0.5
0.0524 × VCCA
V
VILC
SCL_SYS,
(contention) LowSDA_SYS,
level input voltage
CEC_SYS
VOL –
VILC
Delta between
VOL and VILC
TA
Operating free-air temperature
SCL_SYS,
SDA_SYS,
CEC_SYS
VCCA = 1.1 V to 5.5 V
VCCA = 1.8 V
0.1 × VCCA
mV
–40
85
°C
ESD TABLE
over operating free-air temperature range (unless otherwise noted)
TYP
UNIT
HBM ESD
PARAMETER
SCL_SYS, SDA_SYS, CEC_SYS, HPD_SYS, 5V_SYS, VCCA, EN
±2
kV
IEC 61000-4-2 Contact Discharge
SCL_CON, SDA_CON, CEC_CON, HPD_CON, 5V_CON,
UTI_CON
±15
kV
IEC 61000-4-2 Air-gap ESD
SCL_CON, SDA_CON, CEC_CON, HPD_CON, 5V_CON,
UTI_CON
±15
kV
6
SIGNALS
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ELECTRICAL CHARACTERISTICS
Max values measured across temp and VCCA=1.1V to 5.5V and 5V_SYS=5.5V. Typical values measured at VCCA=1.8V and
5V_SYS=5V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Current
ICC5V
Disabled
5V_SYS =5V, 5V_CON =Open EN =
GND, HPD_CON=GND
2
10
µA
Load Switch active
5V_SYS =5V, 5V_CON =Open EN =
VCCA, HPD_CON=GND
30
50
µA
Active
5V_SYS =5V, 5V_CON =Open EN =
VCCA, HPD_CON=5V
125
200
µA
5V_SYS=4V, 5V_CON > 5V_SYS
100
Load Switch
VREV
IOFF
Reverse voltage comparator trip
point
Leakage Current
ISC
mV
5V_CON=0V, 5V_SYS=5V ,
EN=GND, HPD_CON=GND
Measured at 5V_SYS pin.
1
5
µA
5V_CON=0V, 5V_SYS=5V ,
EN=GND, HPD_CON=5V Measured
at 5V_SYS pin
1
5
µA
5V_CON =5V, 5V_SYS =0V ,
EN=GND, HPD_CON=GND
Measured at 5V_CON pin.
1
5
µA
5V_CON =5V, 5V_SYS =0V
EN=GND, HPD_CON=5V Measured
at 5V_CON pin.
1
5
µA
5V_CON =5V, 5V_SYS =0V,
EN=VCCA, HPD_CON=GND
Measured at 5V_CON pin.
1
5
µA
5V_CON =5V, 5V_SYS =0V,
EN=VCCA, HPD_CON=5V Measured
at 5V_CON pin.
1
5
µA
140
170
mA
Short circuit current at 5V_CON
5V_SYS=5V, 5V_CON = GND
TDEGLITCH
Deglitch time against false short
5V_SYS=5V , EN=VCCA, Short
5V_CON
UVLO
Under voltage lockout rising
UVLO_HY
S
VDROP
110
3
µs
5V_SYS=0V to 5V, RL = 100 Ω, CL =
1uF
2.85
V
Under voltage lockout falling
hysteresis
5V_SYS=5V to 0V, RL = 100 Ω, CL =
1uF
200
mV
5V_OUT output voltage drop
5V_SYS =5V, I5V_OUT = 55 mA
38.5
IRUSH
Inrush Current
5V_SYS=5V, RL=100 Ω, Cin=10uF,
C=1uF
140
mA
TON
Turn on Time, EN to 5V_CON
5V_SYS=5V, RL=100 Ω, Cin=10uF,
C=1uF
92.3
µs
TOFF
Turn off Time, EN to 5V_CON
5V_SYS=5V, RL=100 Ω, Cin=10uF,
C=1uF
5
µs
TSHUT
Thermal Shutdown
(1)
(2)
Shutdown threshold, TRIP (1)
HYST (2)
55
166
23
mV
°C
The TPD5S116 turns off after the device temperature reaches the TRIP temperature.
Once the thermal shut-down circuit turns off the load switch, the switch turns on again after the device junction temperature cools down
to a temperature equals to or less than TRIP-HYST.
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Voltage Level Shifter - SCL, SDA Lines
PARAMETER
TEST CONDITIONS
VOH_SYS
IOH = –10 µA
VI = VIH
VOL_SYS
IOL = 10 µA
VI = VIL
VOH_CON
IOH = –10 µA
VI = VIH
VOL_CON
IOH = 3 mA
VI = VIL
VCCA
–40°C to 85°C
MIN
TYP
0.8 × VCCA
0.8 x
5V_SYS
0.3
ΔVT Hysteresis at the SDx_IN
(VT+ - VT-)
ΔVT Hysteresis at the SDx_OUT
(VT+ - VT-)
V
0.17 ×
VCCA
V
5V_SYS+
0.02
V
0.4
V
400
mV
SCL_CON,
SDA_CON
Pull-up
connected to 5V
rail
1.75
IPULLUPAC Transient Boosted Pull- SCL_CON,
up Current (rise-time accelerator) SDA_CON
Pull-up
connected to 5V
rail
13
IOZ
VCCA+0.0
2
mV
Pull-up
connected to
VCCA rail
Ioff
UNIT
40
SCL_SYS,
SDA_SYS
RPU (Internal pull-up)
MAX
5
kΩ
mA
SYS Port
VCCA = 0V, VI or VO = 0 to 3.6 V
0V
±5
CON Port
5V_CON=0V, VI or VO = 0 to 5.5 V
0V
±5
SYS Port
VI = VCCI or GND
µA
±5
Voltage Level Shifter - CEC Line
PARAMETER
TEST CONDITIONS
VOH_SYS
IOH = –10 µA
VI = VIH
VOL_SYS
IOL = 10 µA
VI = VIL
VOH_CON
IOH = –10 µA
VI = VIH
VOL_CON
IOH = 3 mA
VI = VIL
VCCA
–40°C to 85°C
MIN
TYP
0.8 × VCCA
MAX
UNIT
VCCA+0.0
2
V
0.17 ×
VCCA
V
0.8 x V3P3
V
0.3
0.4
V
ΔVT Hysteresis at the CEC_SYS
(VT+ - VT-)
30
mV
ΔVT Hysteresis at the CEC_CON
(VT+ - VT-)
283
mV
5
kΩ
CEC_SYS
Pull-up
connected to
VCCA rail
CEC_CON
Pull-up
connected to
3.3V rail
CEC_CON
Pull-down
connected
connector side
RPU (Internal pull-up)
RPD (Internal pull-down)
Ioff
IOZ
8
22
26
30
10
kΩ
MΩ
SYS Port
VCCA = 0V, VI or VO = 0 to 3.6 V
0V
±5
CON Port
5V_CON=0V, VI or VO = 0 to 5.5 V
0V
±1.8
SYS Port
VI = VCCI or GND
µA
±5
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Voltage Level Shifter - HPD Line
PARAMETER
TEST CONDITIONS
–40°C to 85°C
VCCA
MIN
TYP
UNIT
MAX
VOH_SYS
IOH = 1 mA
VI = VIH
1.2 V to 5.0 V
VCCA × 0.7
VOH_SYS_1P1
IOH = 100 µA
VI = VIH
1.1V
VCCA × 0.7
VOL_SYS
IOL = 3 µA
VI = VIL
1.2 V to 5.0 V
0.4
V
VOL_SYS_1P1
IOL = 3 mA
VI = VIL
1.1 V
0.68
V
ΔVT Hysteresis at the CEC_CON
(VT+ - VT-)
V
V
1.2 V to 5.0 V
500
mV
RPD_IN (Input internal pull-down
resistor)
Pull-down
connected to
GND
60
100
140
kΩ
RPD_OUT (Output internal pulldown resistor)
Pull-down
connected to
GND
60
100
140
kΩ
Glitch Filter
Duration
TFILT
HPD_CON = 5 V, EN = VCCA,
Short HPD_SYS
10
µs
EN
PARAMETER
TEST CONDITIONS
VCCA
RPD EN (Internal pull-down
resistor)
Pull-down connected to GND
1.8 V
–40°C to 85°C
MIN
TYP
UNIT
MAX
470
kΩ
UTILITY PIN
PARAMETER
VRWM
VCLAMP
(1)
(2)
DESCRIPTION
TEST CONDITIONS
MIN
TYP
Reverse stand-off voltage
Clamp voltage with ESD strike
MAX
UNIT
6
V
IPP = 1 A, tp = 8/20 μSec, from
I/O to GND (1)
8
IPP = 5 A, tp = 8/20 μSec, , from
I/O to GND (1)
10
UTI pin to GND Pin (2)
033
Ω
VIO=0V, f=1GHz, I/O to GND
5.5
pF
RDYN
Dynamic resistance
CUTI
Line capacitance
VBR
Break-down voltage
IIO = 1mA
ILEAK
Leakage current
VIO = 3V
V
7
V
1
10
nA
Non-repetitive current pulse 8/20us exponentially decaying waveform according to IEC61000-4-5
Extraction of RDYN using least squares fit of TLP characteristics between I=10A and I=20A
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I/O Capacitances
PARAMETER
TEST CONDITONS
SUPPLY & EN
SIGNAL
–40°C to 85°C
MIN
TYP
MAX
UNIT
CI
EN
VBIAS = VCCA/2, f =1MHz, 30mV pp ac signal
8
9
pF
CI
HPD_CON
VBIAS = 0V- 5V, f =1MHz, 30mV p-p
ac signal
7
7.5
pF
SYS port
VBIAS = 1.8 V, f =1MHz, 30mV p-p
ac signal
6.5
9.5
pF
CON port
VBIAS = 2.5 V, f =1MHz, 30mV p-p
ac signal
15
20
pF
SCL_CON,
SDA_CON
VBIAS = 2.5V, f =100KHz, 3.5V p-p
ac signal
VCCA= 3.6 V,
5V_SYS =5V,
EN=HPD_CON=0
V
17
pF
CEC_CON
VBIAS = 1.65 V, f =100KHz, 2.5V pp ac signal
VCCA= 3.6 V,
5V_SYS =5V,
EN=HPD_CON=0
V
13
pF
CEC_CON
VBIAS = 1.65 V, f =100KHz, 2.5V pp ac signal
VCCA= 0V 5V_SYS
=0V
EN=HPD_CON=0
V
12
pF
CIO
Dynamic Load Characteristics
Propagation delays measured from 50% threshold to 50% threshold
Rise time measured from 30% to 70% threshold
Fall time measured from 70% to 30% threshold
PARAMETER
CL
10
DESCRIPTION
TEST CONDITION
MIN
TYP
Max
Bus Load Capacitance
(Connector Side)
750
Bus Load Capacitance
(System Side)
30
UNIT
pF
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SLVSBP3 – DECEMBER 2012
Dynamic Characteristics - SCL, SDA Lines
5V_CON=5V; VCCA = 1.2V
PARAMETER
TPHL
TPLH
DESCRIPTION
PINS
Propagation Delay
SYS to CON
DDC Channels Enabled
316
ns
CON to SYS
DDC Channels Enabled
286
ns
SYS to CON
DDC Channels Enabled
489
ns
CON to SYS
DDC Channels Enabled
199
ns
Propagation Delay
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TFALL
SYS Port Fall Time
SYS Port
DDC Channels Enabled
110
ns
TFALL
CON Port Fall Time
CON Port
DDC Channels Enabled
82
ns
TRISE
SYS Port Rise Time
SYS Port
DDC Channels Enabled
229
ns
TRISE
CON Port Rise Time
CON Port
DDC Channels Enabled
FMAX
Maximum Switching
Frequency
86
DDC Channels Enabled
400
TEST CONDITIONS
MIN
ns
kHz
Dynamic Characteristics - CEC Lines
5V_CON=5V; VCCA = 1.2V
PARAMETER
TPHL
TPLH
DESCRIPTION
PINS
Propagation Delay
SYS to CON
CEC Channels Enabled
436
ns
CON to SYS
CEC Channels Enabled
97
ns
SYS to CON
CEC Channels Enabled
13.8
µs
CON to SYS
CEC Channels Enabled
319
ns
Propagation Delay
TYP
MAX
UNIT
TFALL
SYS Port Fall Time
SYS Port
CEC Channels Enabled
37
ns
TFALL
CON Port Fall Time
CON Port
CEC Channels Enabled
114
ns
TRISE
SYS Port Rise Time
SYS Port
CEC Channels Enabled
234
ns
TRISE
CON Port Rise Time
CON Port
CEC Channels Enabled
16.6
µs
Dynamic Characteristics - HPD Lines
5V_CON=5V; VCCA = 1.2V
DESCRIPTION
PINS
TPHL
PARAMETER
Propagation Delay
CON to SYS
CEC Channels Enabled
TEST CONDITIONS
MIN
TYP
10.1
MAX
µs
TPLH
Propagation Delay
CON to SYS
CEC Channels Enabled
9.7
µs
TFALL
SYS Port Fall Time
SYS Port
CEC Channels Enabled
14
ns
TRISE
SYS Port Rise Time
SYS Port
CEC Channels Enabled
18
ns
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UNIT
11
TPD5S116
SLVSBP3 – DECEMBER 2012
www.ti.com
Dynamic Characteristics - SCL, SDA Lines
5V_CON=5V; VCCA = 1.5V
PARAMETER
TPHL
DESCRIPTION
PINS
Propagation Delay
TPLH
Propagation Delay
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A to B
DDC Channels Enabled
297
ns
B to A
DDC Channels Enabled
224
ns
A to B
DDC Channels Enabled
473
ns
B to A
DDC Channels Enabled
193
ns
TFALL
A Port Fall Time
A-Port
DDC Channels Enabled
87
ns
TFALL
B Port Fall Time
B-Port
DDC Channels Enabled
82
ns
TRISE
A Port Rise Time
A-Port
DDC Channels Enabled
226
ns
TRISE
B Port Rise Time
B-Port
DDC Channels Enabled
FMAX
Maximum Switching
Frequency
86
DDC Channels Enabled
400
TEST CONDITIONS
MIN
ns
kHz
Dynamic Characteristics - CEC Lines
5V_CON=5V; VCCA = 1.5V
PARAMETER
TPHL
DESCRIPTION
PINS
Propagation Delay
TPLH
Propagation Delay
TYP
MAX
UNIT
A to B
CEC Channels Enabled
419
ns
B to A
CEC Channels Enabled
102
ns
A to B
CEC Channels Enabled
13.7
µs
B to A
CEC Channels Enabled
314
ns
TFALL
A Port Fall Time
A-Port
CEC Channels Enabled
39
ns
TFALL
B Port Fall Time
B-Port
CEC Channels Enabled
115
ns
TRISE
A Port Rise Time
A-Port
CEC Channels Enabled
230
ns
TRISE
B Port Rise Time
B-Port
CEC Channels Enabled
16.6
µs
Dynamic Characteristics - HPD Lines
5V_CON=5V; VCCA = 1.5V
PARAMETER
DESCRIPTION
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPHL
Propagation Delay
B to A
CEC Channels Enabled
10.1
µs
TPLH
Propagation Delay
B to A
CEC Channels Enabled
9.7
µs
TFALL
A Port Fall Time
A-Port
CEC Channels Enabled
8
ns
TRISE
A Port Rise Time
A-Port
CEC Channels Enabled
9.5
ns
12
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SLVSBP3 – DECEMBER 2012
Dynamic Characteristics - SCL, SDA Lines
5V_CON=5V; VCCA = 1.8V
PARAMETER
TPHL
DESCRIPTION
PINS
Propagation Delay
TPLH
Propagation Delay
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A to B
DDC Channels Enabled
292
ns
B to A
DDC Channels Enabled
192
ns
A to B
DDC Channels Enabled
466
ns
B to A
DDC Channels Enabled
190
ns
TFALL
A Port Fall Time
A-Port
DDC Channels Enabled
75
ns
TFALL
B Port Fall Time
B-Port
DDC Channels Enabled
82
ns
TRISE
A Port Rise Time
A-Port
DDC Channels Enabled
224
ns
TRISE
B Port Rise Time
B-Port
DDC Channels Enabled
FMAX
Maximum Switching
Frequency
86
DDC Channels Enabled
400
TEST CONDITIONS
MIN
ns
kHz
Dynamic Characteristics - CEC Lines
5V_CON=5V; VCCA = 1.8V
PARAMETER
TPHL
DESCRIPTION
PINS
Propagation Delay
TPLH
Propagation Delay
TYP
MAX
UNIT
A to B
CEC Channels Enabled
417
ns
B to A
CEC Channels Enabled
108
ns
A to B
CEC Channels Enabled
13.7
µs
B to A
CEC Channels Enabled
312
ns
TFALL
A Port Fall Time
A-Port
CEC Channels Enabled
41
ns
TFALL
B Port Fall Time
B-Port
CEC Channels Enabled
114
ns
TRISE
A Port Rise Time
A-Port
CEC Channels Enabled
228
ns
TRISE
B Port Rise Time
B-Port
CEC Channels Enabled
16.6
µs
Dynamic Characteristics - HPD Lines
5V_CON=5V; VCCA = 1.8V
PARAMETER
DESCRIPTION
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPHL
Propagation Delay
B to A
CEC Channels Enabled
10.1
µs
TPLH
Propagation Delay
B to A
CEC Channels Enabled
9.7
µs
TFALL
A Port Fall Time
A-Port
CEC Channels Enabled
5.5
ns
TRISE
A Port Rise Time
A-Port
CEC Channels Enabled
7
ns
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SLVSBP3 – DECEMBER 2012
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Dynamic Characteristics - SCL, SDA Lines
5V_CON=5V; VCCA = 2.5V
PARAMETER
TPHL
DESCRIPTION
PINS
Propagation Delay
TPLH
Propagation Delay
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A to B
DDC Channels Enabled
291
ns
B to A
DDC Channels Enabled
154
ns
A to B
DDC Channels Enabled
455
ns
B to A
DDC Channels Enabled
186
ns
TFALL
A Port Fall Time
A-Port
DDC Channels Enabled
64
ns
TFALL
B Port Fall Time
B-Port
DDC Channels Enabled
82
ns
TRISE
A Port Rise Time
A-Port
DDC Channels Enabled
221
ns
TRISE
B Port Rise Time
B-Port
DDC Channels Enabled
FMAX
Maximum Switching
Frequency
86
DDC Channels Enabled
400
TEST CONDITIONS
MIN
ns
kHz
Dynamic Characteristics - CEC Lines
5V_CON=5V; VCCA = 2.5V
PARAMETER
TPHL
DESCRIPTION
PINS
Propagation Delay
TPLH
Propagation Delay
TYP
MAX
UNIT
A to B
CEC Channels Enabled
421
ns
B to A
CEC Channels Enabled
122
ns
A to B
CEC Channels Enabled
13.7
µs
B to A
CEC Channels Enabled
311
ns
TFALL
A Port Fall Time
A-Port
CEC Channels Enabled
49
ns
TFALL
B Port Fall Time
B-Port
CEC Channels Enabled
114
ns
TRISE
A Port Rise Time
A-Port
CEC Channels Enabled
225
ns
TRISE
B Port Rise Time
B-Port
CEC Channels Enabled
16.6
µs
Dynamic Characteristics - HPD Lines
5V_CON=5V; VCCA = 2.5V
PARAMETER
DESCRIPTION
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPHL
Propagation Delay
B to A
CEC Channels Enabled
10.1
µs
TPLH
Propagation Delay
B to A
CEC Channels Enabled
9.7
µs
TFALL
A Port Fall Time
A-Port
CEC Channels Enabled
4
ns
TRISE
A Port Rise Time
A-Port
CEC Channels Enabled
5
ns
14
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SLVSBP3 – DECEMBER 2012
Dynamic Characteristics - SCL, SDA Lines
5V_CON=5V; VCCA = 3.3V
PARAMETER
TPHL
DESCRIPTION
PINS
Propagation Delay
TPLH
Propagation Delay
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A to B
DDC Channels Enabled
292
ns
B to A
DDC Channels Enabled
133
ns
A to B
DDC Channels Enabled
449
ns
B to A
DDC Channels Enabled
184
ns
TFALL
A Port Fall Time
A-Port
DDC Channels Enabled
57
ns
TFALL
B Port Fall Time
B-Port
DDC Channels Enabled
82
ns
TRISE
A Port Rise Time
A-Port
DDC Channels Enabled
218
ns
TRISE
B Port Rise Time
B-Port
DDC Channels Enabled
FMAX
Maximum Switching
Frequency
86
DDC Channels Enabled
400
TEST CONDITIONS
MIN
ns
kHz
Dynamic Characteristics - CEC Lines
5V_CON=5V; VCCA = 3.3V
PARAMETER
TPHL
DESCRIPTION
PINS
Propagation Delay
TPLH
Propagation Delay
TYP
MAX
UNIT
A to B
CEC Channels Enabled
428
ns
B to A
CEC Channels Enabled
138
ns
A to B
CEC Channels Enabled
13.7
µs
B to A
CEC Channels Enabled
309
ns
TFALL
A Port Fall Time
A-Port
CEC Channels Enabled
59
ns
TFALL
B Port Fall Time
B-Port
CEC Channels Enabled
114
ns
TRISE
A Port Rise Time
A-Port
CEC Channels Enabled
223
ns
TRISE
B Port Rise Time
B-Port
CEC Channels Enabled
16.6
µs
Dynamic Characteristics - HPD Lines
5V_CON=5V; VCCA = 3.3V
PARAMETER
DESCRIPTION
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPHL
Propagation Delay
B to A
CEC Channels Enabled
10.1
µs
TPLH
Propagation Delay
B to A
CEC Channels Enabled
9.7
µs
TFALL
A Port Fall Time
A-Port
CEC Channels Enabled
3
ns
TRISE
A Port Rise Time
A-Port
CEC Channels Enabled
3.5
ns
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TPD5S116
SLVSBP3 – DECEMBER 2012
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Dynamic Characteristics - SCL, SDA Lines
5V_CON=5V; VCCA = 5V
PARAMETER
TPHL
DESCRIPTION
PINS
Propagation Delay
TPLH
Propagation Delay
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A to B
DDC Channels Enabled
298
ns
B to A
DDC Channels Enabled
113
ns
A to B
DDC Channels Enabled
442
ns
B to A
DDC Channels Enabled
182
ns
TFALL
A Port Fall Time
A-Port
DDC Channels Enabled
52
ns
TFALL
B Port Fall Time
B-Port
DDC Channels Enabled
82
ns
TRISE
A Port Rise Time
A-Port
DDC Channels Enabled
217
ns
TRISE
B Port Rise Time
B-Port
DDC Channels Enabled
FMAX
Maximum Switching
Frequency
86
DDC Channels Enabled
400
TEST CONDITIONS
MIN
ns
kHz
Dynamic Characteristics - CEC Lines
5V_CON=5V; VCCA = 5V
PARAMETER
TPHL
DESCRIPTION
PINS
Propagation Delay
TPLH
Propagation Delay
TYP
MAX
UNIT
A to B
CEC Channels Enabled
446
ns
B to A
CEC Channels Enabled
169
ns
A to B
CEC Channels Enabled
13.7
µs
B to A
CEC Channels Enabled
306
ns
TFALL
A Port Fall Time
A-Port
CEC Channels Enabled
82
ns
TFALL
B Port Fall Time
B-Port
CEC Channels Enabled
114
ns
TRISE
A Port Rise Time
A-Port
CEC Channels Enabled
221
ns
TRISE
B Port Rise Time
B-Port
CEC Channels Enabled
16.6
µs
Dynamic Characteristics - HPD Lines
5V_CON=5V; VCCA = 5V
PARAMETER
DESCRIPTION
PINS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPHL
Propagation Delay
B to A
CEC Channels Enabled
10.1
µs
TPLH
Propagation Delay
B to A
CEC Channels Enabled
9.7
µs
TFALL
A Port Fall Time
A-Port
CEC Channels Enabled
2.5
ns
TRISE
A Port Rise Time
A-Port
CEC Channels Enabled
2.5
ns
16
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SLVSBP3 – DECEMBER 2012
TYPICAL CHARACTERISTICS
Conditions TBD
Voltage (V)
5
7
210
180
6
180
150
5
150
4
120
3
90
2
60
1
30
0
0
±40
0
±20
20
40
60
80
100
120
140
90
160
30
0
±30
±40
0
±20
20
40
60
80
100
120
140
160
Time ( s)
C001
C002
Figure 3. Powerup to Short Circuit
Figure 4. Enable to Short Circuit
UTILITY PIN CURRENT
vs
VOLTAGE
UTILITY PIN CURRENT and POWER
vs
TIME
9
Rd
40
60
±1
45
90
Current
8
80
Power
7
70
30
6
60
5
50
4
40
15
3
30
10
2
20
5
1
10
0
0
Current (A)
35
25
20
0
0
3
6
9
12
15
18
21
24
27
Voltage (V)
0
30
10
15
20
C003
25
30
35
40
45
50
C004
Figure 5. TLP Curve
Figure 6. Surge Curves
UTILITY PIN GAIN
vs
FREQUENCY
UTILITY PIN AMPLITUDE
vs
TIME
3
60
0
50
Amplitude (V)
40
±6
±9
±12
30
20
10
±15
0
±18
±21
100k
5
Time ( s)
±3
Gain (dB)
EN
5V_SYS
5V_CON
Isc
2
0
Time ( s)
Current (A)
120
3
1
±30
±1
4
Power (W)
6
210
Voltage (V)
5V_SYS
5V_CON
Isc
Current (mA)
7
VOLTAGE and CURRENT
vs
TIME
Current (mA)
VOLTAGE and CURRENT
vs
TIME
±10
1M
10M
100M
1G
Frequency (Hz)
10G
±25
Figure 7. Insertion Loss Waveform Data
0
25
50
75
100
125
150
175
200
Time (ns)
C005
225
C006
Figure 8. Keytek, +8kV IEC Voltage Clamp Waveform
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TPD5S116
SLVSBP3 – DECEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Conditions TBD
UTILITY PIN AMPLITUDE
vs
TIME
UTILITY PIN INPUT CURRENT
vs
INPUT VOLTAGE
10
1.0
0.8
0
0.6
Input Current (mA)
Amplitude (V)
±10
±20
±30
±40
0.4
0.2
0.0
±0.2
±0.4
±0.6
±50
±0.8
±60
±1.0
±25
0
25
50
75
100
125
150
175
200
225
4
6
8
10
12
14
Input Voltage (V)
Figure 10. DC Curve Data
5V_CON VOLTAGE
vs
EN INPUT VOLTAGE
SWITCH RESISTANCE
vs
TEMPERATURE
C008
1000
TA = 25ƒC
900
ISWITCH | 55 mA
800
5V_SYS = 4.5V
5V_SYS = 5.0V
700
600
500
400
300
200
100
5V_SYS = 5.5V
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
5.0
±40
2.0
VEN Input Voltage (V)
4.0
±20
0
20
40
60
80
Temperature (ƒC)
C009
Figure 11. EN VTH
Figure 12. Rds Data
5V_SYS CURRENT
vs
TEMPERATURE
5V_CON CURRENT
vs
5V_CON VOLTAGE
2.0
4.5V
5.0V
5.5V
4.5
EN Low
EN High
1.8
C010
VCCA = 3.3 V
V5V_SYS = 0 V
1.6
3.5
I5V_CON ( A)
1.4
3.0
2.5
2.0
1.2
1.0
0.8
1.5
0.6
1.0
0.4
0.5
0.2
0.0
0.0
±40
±20
0
20
40
Temperature (ƒC)
60
80
0.0
C011
Figure 13. I5V_SYS Data
18
2
Figure 9. Keytek, -8kV IEC Voltage Clamp Waveform
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
±0.5
I5V_SYS ( A)
0
±2
C007
Switch Resistance (m
V5V_CON (V)
Time (ns)
1.0
2.0
3.0
4.0
V5V_CON (V)
5.0
C012
Figure 14. Reverse Switch Current Data
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SLVSBP3 – DECEMBER 2012
TYPICAL CHARACTERISTICS (continued)
Conditions TBD
6
200
5
4
160
4
160
3
120
3
120
2
80
2
80
Voltage (V)
5
1
CIN = 10 F
CLOAD = 1 F
VCCA = 3.3 V
V5V_SYS = 0 V
0
±1
40
1
0
0
±40
±40
±20
0
20
40
60
80
100
120
140
Time ( s)
Voltage (V)
240
EN
5V_SYS
Iinrush
Current (mA)
6
VOLTAGE and CURRENT
vs
TIME
±1
±100 ±50
160
C013
Figure 15. IINRUSH Waveform Data
240
EN
5V_SYS
Iinrush
200
40
CIN = 4.7 F
CLOAD = 4.7 F
VCCA = 3.3 V
V5V_SYS = 0 V
0
±40
0
50
100
150
200
250
300
350
400
Time ( s)
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C014
Figure 16. IINRUSH Waveform Data
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Current (mA)
VOLTAGE and CURRENT
vs
TIME
19
TPD5S116
SLVSBP3 – DECEMBER 2012
www.ti.com
APPLICATION INFORMATION
DDC/CEC LEVEL SHIFT Circuit Operation
The TPD5S116 enables DDC translation from VCCA (system side) voltage levels to 5V_CON (HDMI connector
side) voltage levels without degradation of system performance. The TPD5S116 contains 2 bidirectional opendrain buffers specifically designed to support up-translation/down-translation between the low voltage, system
side DDC-bus and the 5V connector side DDC-bus. The connector port I/Os are over-voltage tolerant to 5.5 V
even when the device is un-powered. After power-up and with enable pin and HPD_CON pin HIGH, a LOW level
on system port (below approximately VILC = 0.08 × VCCA V) turns the corresponding connector port driver
(either SDA or SCL) on and drives it down to VOL_CON V. When system port rises above approximately 0.10 ×
VCCA V, the connector port pull-down driver is turned off and the internal pull-up resistor pulls the pin HIGH.
When connector port falls first and goes below 0.3 × 5V_CON, a CMOS hysteresis input buffer detects the falling
edge, turns on the system port driver, and pulls it down to approximately VOLA V. The connector port pull-down is
not enabled unless the system port voltage goes below VILC, in which case the connector port pull-down driver
is enabled until system port rises above (VILC + ΔVT-HYSTA). If the connector port is not externally driven LOW, its
voltage will continue to rise due to the internal pull-up resistor.
5VOUT
VCCA
IACCEL
CMP1
CMP2
ACCEL
700mV
RPUB
RPUA
150mV
GLITCH
FILTER
Port A
Port B
DDC
Lines
Only
l
300mV
Figure 17. DDC/CEC Level Shifter Block Diagram
20
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SLVSBP3 – DECEMBER 2012
DDC/CEC Level Shifter Operational Notes for VCCA=1.8V
•
•
•
•
•
•
•
•
The threshold of CMP1 is ~150mV +/- the 40mV of total hysteresis.
The comparator will trip for a falling waveform at ~130mV
The comparator will trip for a rising waveform at ~170mV
To be recognized as a zero, the level at system port must first go below 130mV (VILC in spec) and then stay
below 170mV (VIL_SYS in spec)
To be recognized as a one, the level at system port must first go above 170mV and then stay above 130mV
VILC is set to 110mV in Electrical Characteristics Table to give some margin to the 130mV
VIL_SYS is set to 140mV in the Electrical Characteristics Table to give some margin to the 170mV
VIH_SYS is set to 70% of VCCA to be consistent with standard CMOS levels
Figure 18. DDC Level Shifter Operation (Connector to System Direction)
Rise-Time Accelerators
The HDMI cable side of the DDC lines incorporates rise-time accelerators to support the high capacitive load on
the HDMI cable side. The rise time accelerator boosts the cable side DDC signal independent of which side of
the bus is releasing the signal.
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Product Folder Links: TPD5S116
21
TPD5S116
SLVSBP3 – DECEMBER 2012
www.ti.com
Normal HDMI Transmit and Recieve Sequence
Figure 19. Tx Device Connecting with Rx Device
Hot Plug Detect
Once TPD5S116 is enabled and the system’s 5V source is on, TPD5S116 is ready for continual HDMI receiver
detection. When a HDMI cable connects receiving and transmitting device together, the 5V on the load switch
(5V_CON) flows through the receiving device’s internal resistor and into HPD’s input (HPD_CON). The HPD
buffer’s output then goes high, indicating to the transmitter that a receiving device is connected. To save power,
periodic detection can be done by turning on and off the TPD5S116 before a receiving device is connected.
Noise Considerations: Ground offset between the TPD5S116 ground and the ground of devices on system port
of the TPD5S116 must be avoided. The reason for this cautionary remark is that a CMOS/NMOS open-drain
capable of sinking 3 mA of current at 0.4 V will have an output resistance of 133Ω or less (R = E / I). Such a
driver will share enough current with the system port output pull-down of the TPD5S116 to be seen as a LOW as
long as the ground offset is zero. If the ground offset is greater than 0 V, then the driver resistance must be less.
Since VILC can be as low as 90 mV at cold temperatures and the low end of the current distribution, the
maximum ground offset should not exceed 50 mV. Bus repeaters that use an output offset are not interoperable
with the system port of the TPD5S116 as their output LOW levels will not be recognized by the TPD5S116 as a
LOW. If the TPD5S116 is placed in an application where the VIL_SYS does not go below VILC, it will pull connector
port LOW initially when system port input transitions LOW but the connector port will return HIGH, so it will not
reproduce the system port input on connector port. Such applications should be avoided. Connector port is
interoperable with all I2C-bus slaves, masters and repeaters.
Resistor Pull-Up Value Selection
The system is designed to work properly with no external pull-up resistors on the DDC, CEC, and HPD lines.
22
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TPD5S116
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SLVSBP3 – DECEMBER 2012
INPUT CAPACITOR (OPTIONAL)
To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a
discharged load capacitor or short-circuit, a capacitor needs to be placed between 5V_SYS and GND. A 10-μF
ceramic capacitor, CIN, placed close to the pins, is usually sufficient. Higher values of CIN can be used to further
reduce the voltage drop during high-current application. When switching heavy loads, it is recommended to have
an input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop.
OUTPUT CAPACITOR (OPTIONAL)
Due to the integrated body diode in the NMOS switch, a CIN greater than CLOAD is highly recommended. A CLOAD
greater than CIN can cause 5V_CON to exceed 5V_SYS when the system supply is removed. A CIN to CLOAD
ratio of 10 to 1 is recommended for minimizing 5V_SYS dip caused by inrush currents during startup.
HDMI Compliance
The TPD5S116 is designed to be fully compliant to HDMI 7-13 capacitance specification. Both power on and
power off capacitance measurements are done on the CEC, SDA, and SCL connector side pins using a Hioki
3522-50 meter. In power on setup, connect TPD5S116’s EN and HPD_CON pins low and 5V_SYS and VCCA
pins high. Use the Hioki meter to measure the test fixture with and without the TPD5S116 and subtract to obtain
capacitance. In power off setup, connect TPD5S116’s EN, HPD_CON, 5V_SYS, and VCCA pins low and
conduct same test with the Hioki meter. Read the Cp result from the Hioki meter.
• SCL_CON, SDA_CON Test
– Measure large signal capacitance at SCL_CON & SDA_CON pins either power-up or power down
conditions:
– VBIAS = 2.5 V
– f = 100KHz
– 3.5V p-p ac signal
• CEC Test
– Measure large signal capacitance of the CEC_CON pin at both power-up and power down conditions:
– VBIAS = 1.65 V,
– f = 100KHz
– 2.5V p-p ac signal
3.5V P-P
2.5V DC BIAS
F= 100KHz
Figure 20. Hioki Meter Signal Set-up for SCL, SDA Cap Measurement
2.5V P-P
1.65V DC BIAS
F= 100KHz
Figure 21. Hioki Meter Signal Set-up for CEC Cap Measurement
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23
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPD5S116YFFR
ACTIVE
Package Type Package Pins Package Qty
Drawing
DSBGA
YFF
15
3000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
SNAGCU
MSL Peak Temp
Samples
(3)
(Requires Login)
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Dec-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPD5S116YFFR
Package Package Pins
Type Drawing
SPQ
DSBGA
3000
YFF
15
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
8.4
Pack Materials-Page 1
1.46
B0
(mm)
K0
(mm)
P1
(mm)
2.28
0.71
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Dec-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD5S116YFFR
DSBGA
YFF
15
3000
210.0
185.0
35.0
Pack Materials-Page 2
D: Max = 2.164 mm, Min =2.104 mm
E: Max = 1.364 mm, Min =1.304 mm
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