TI TPD13S523PWR

TPD13S523
www.ti.com
SLVSBC5A – MARCH 2012 – REVISED MAY 2012
13 Channel ESD Protection Solution with Current-Limit Load Switch for HDMI Port
Check for Samples: TPD13S523
FEATURES
1
•
•
•
•
Set-top Box
Smart Phone
Digital Camcorder
Portable Game Console
D0+
D0-
CTRL1
CTRL2
4
IEW
EV
5V_OUT
D1-
10
D2+
9
D2-
5
6
7
8
16-TSSOP: 6.4mm x 5.0mm
(TOP VIEW)
APPLICATIONS
•
•
•
•
3
D1+
11
D3-
•
5V_SUPPLY
12
D3+
•
1
CTRL4 2
PR
•
16 15 14 13
CTRL3
GND
•
16-RSV: 2.6mm x 1.8mm
(TOP VIEW)
Single Chip ESD Solution for HDMI 1.4 and
HDMI 1.3 Interface
On-chip 5V Load Switch with Current Limit and
Reverse Current Protection
Supports UTILITY Line Protection for HDMI 1.4
Audio Return Line
<0.05-pF Differential Capacitance Between the
TMDS Signal Pair
Industry Standard 16-TSSOP and Space
Saving 16-RSV Package
Supports Data Rates in Excess of 3.3Gbps
RDYN 0.5Ω
IEC 61000-4-2 (Level 4) ESD Compliance
Commercial Temperature Range: –40°C to
85°C
CTRL5
•
CTRL1
1
16
D0+
CTRL2
2
15
D0-
CTRL3
3
14
D1+
CTRL4
4
13
D1-
5V_SUPPLY
5
12
D2+
5VOUT
6
11
D2-
CTRL5
7
10
D3+
GND
8
9
D3-
All the CTRLx pins have the same ESD
circuit and are interchangeable.
DESCRIPTION
The TPD13S523 is a single-chip integrated ESD protection solution for HDMI 1.4 or HDMI 1.3 interface. This
device offers 13 channels of ESD clamp circuits with flow-through pin mapping that matches HDMI connector
high-speed lines. While providing ESD protection, the TPD13S523 adds little to no additional distortion to the
high-speed differential signals. The monolithic integrated circuit technology ensures that there is excellent
matching between the two-signal pair of the differential line (<0.05pF differential matching between TMDS lines).
This is a advantage over discrete ESD clamp solutions where variations between two different ESD clamps may
significantly degrade the differential signal quality.
The TPD13S523 incorporates an on-chip current limited load switch that is compliant with HDMI 5V out electrical
specifications. The short circuit protection at 5V_OUT ensures that the device is not damaged in case there is
accidental short to GND. The load switch also incorporates reverse current blocking feature which ensures that
the HDMI driver side is not erroneously turned on when two HDMI drivers are connected together.
Connecting a 0.1µF to 1µF capacitor at 5V_OUT, TPD13S523 protects the system against ±12kV contact and
±14kV air-gap ESD discharge.
ORDERING INFORMATION
PACKAGE (1) (2)
TA
–40°C to 85°C
(1)
(2)
3000
Tape and reel
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TPD13S523PWR
RA523
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPD13S523
SLVSBC5A – MARCH 2012 – REVISED MAY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CIRCUIT BLOCK DIAGRAMS
5V_SUPPLY
D3-
D3+
D2-
D2+
D1-
D1+
D0-
D0+
55 mA
Current
Switch
CTRL1
CTRL2
CTRL3
CTRL4
CTRL5
5V OUT
Figure 1. Electrical Equivalent Circuit Diagrams
ESD TERMINAL DESCRIPTIONS
SIGNAL
Dx+, DxCTRLx
(1)
TSSOP PIN
NO.
RSV PIN NO.
TYPE
DESCRIPTION
9, 10, 11, 12,
13, 14, 15, 16
7, 8, 9, 10, 11,
12, 13, 14
connector
pins (1)
High-speed ESD Clamp: provides ESD protection for TMDS lines.
1, 2, 3, 4, 7
1, 2, 5, 15, 16
connector
pins (1)
ESD Clamp for Control Lines: provides ESD protection to HDMI
control lines: CEC, SCL, SDA, HPD, and UTILITY. All the control
pins have the same ESD circuit and are interchangeable.
Connector pins are Dx+, Dx–, CTRLx, and 5V_OUT
SUPPLY TERMINAL DESCRIPTIONS
2
SIGNAL
TSSOP PIN
NO.
RSV PIN NO.
5V_SUPPLY
5
3
Supply pin
Supply Pin for HDMI 5V_OUT 5.0 Volts, connects to internal VCC
plane on the PCB board; connect a 0.1 to 1µF capacitor shunt to
ground.
5V_OUT
6
4
HDMI 5VOUT pin
Current Limited HDMI 5V_OUT: connect to HDMI 5V_OUT; offers
IEC61000-4-2 ESD protection; connect a 0.1 to 1µF capacitor
shunt to ground.
TYPE
DESCRIPTION
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TPD13S523
www.ti.com
SLVSBC5A – MARCH 2012 – REVISED MAY 2012
LAYOUT SCHEME USING TPD13S523
The TPD13S523 device offers little or no signal distortion during normal operation due to low IO capacitance and
ultra-low leakage current specifications. In the event of an ESD stress, this device ensures that the core circuitry
is protected and the system is functioning properly. For proper operation, the following layout/ design guidelines
should be followed:
1. Place the TPD13S523 as close to the connector as possible. This allows the TPD13S523 to take away the
energy associated with ESD strike before it reaches the internal circuitry of the system board.
2. Place two 0.1-μF capacitors very close to the 5V_SUPPLY and 5VOUT pins. These capacitors will help limit
the noise at the 5VOUT power line, and also help with system level ESD protection.
3. Ensure that there is enough metallization for the GND pad. During normal operation, the TPD13S523 ESD
pins consume ultra low leakage current. During the ESD event, GND pin will see multiple amps current.
Sufficient current paths enables safe discharge of all the energy associated with the ESD strike.
4. Leave the unused IO pins floating. If there is no UTILITY pin protection required, it is recommended to leave
CTRL5 open (Figure 2). Connect the CEC, SCL, SDA, and HPD lines to CTRL1-CTRL4 pins.
5. The critical routing paths for HMDI interface are the high-speed TMDS lines. With the PW package, all the
TMDS lines (pin Dxx) can be routed in a single signal plane and still maintain the differential coupling & trace
symmetry. This helps reduce the overall board manufacturing cost. The slow speed control lines can be
routed in another signal layer through VIAs.
Top Layer
HDMI Controller
Bottom Layer
TPD13S523PWR
To 5V Supply
0.1µF
HDMI – Class A
0.1µF
GND Vias
Figure 2. TPD13S523PWR Layout Example 12-Line HDMI Protection (Leave CTRL5 Open)
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TPD13S523
SLVSBC5A – MARCH 2012 – REVISED MAY 2012
www.ti.com
Top Layer
Bottom Layer
HDMI Controller
TPD13S523PWR
To 5V Supply
0.1µF
HDMI – Class A
0.1µF
GND Vias
Figure 3. TPD13S523PWR Layout Example 13-Line HDMI Protection (Additional UTILITY Line Protection)
ABSOLUTE MAXIMUM RATINGS
TA = –40°C to 85°C
MIN
MAX
VCC Voltage Tolerance
5V_SUPPLY
DESCRIPTION
–0.3
6
IO Voltage Tolerance
Connector Pins (1)
–0.3
6
V
–65
125
°C
Storage Temperature
UNIT
V
IEC 61000-4-2 Contact Discharge
Connector Pins (1)
±12
kV
IEC 61000-4-2 Air-gap Discharge
Connector Pins (1)
±14
kV
IEC 61000-4-5 Peak current (8/20 µs)
Connector Pins (1)
3
A
(1)
30
W
IEC 61000-4-5 Peak Power (8/20 µs)
(1)
Connector Pins
Connector pins are Dx+, Dx–, CTRLx, and 5V_OUT
THERMAL INFORMATION
TPD13S523PW
THERMAL METRIC (1)
TSSOP
UNITS
16 PINS
θJA
Junction-to-ambient thermal resistance
119.9
θJCtop
Junction-to-case (top) thermal resistance
54.5
θJB
Junction-to-board thermal resistance
65.0
ψJT
Junction-to-top characterization parameter
9.7
ψJB
Junction-to-board characterization parameter
n/a
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Product Folder Link(s) :TPD13S523
TPD13S523
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SLVSBC5A – MARCH 2012 – REVISED MAY 2012
RECOMMENDED OPERATING CONDITIONS
TA = –40°C to 85°C
DESCRIPTION
VCC Voltage
5V_SUPPLY
IO voltage at external signal pins
Signal Pins (1)
MIN
5.5
Operating free-air temperature range
(1)
MAX
UNIT
V
–0.3
5.5
V
–40
85
°C
External Signal pins are Dx+, Dx–, CTRLx, and 5V_OUT
ELECTRICAL CHARACTERISTICS
TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
LOAD SWITCH
ICC
Supply current at 5V_SUPPLY
5V_SUPPLY =5V, 5V OUT = Open
6.5
7
10
µA
ISC
Short circuit current at 5V_OUT
5V_SUPPLY =5V, 5V_OUT = GND
100
116
147
mA
IBACKDRIVE
Reverse leakage current at 5VOUT
5V_SUPPLY =0V, 5V_OUT = 5V
0.01
0.69
µA
VDROP
5V_OUT output voltage drop
5V_SUPPLY =5V, I5V_OUT = 55 mA
170
205
mV
5.5
V
CONNECTOR PINS
VRWM
Reverse stand-off voltage
Ipp = 1A, 8/20 μs (1)
13
Ipp = 3A, 8/20 μs (1)
15
VCLAMP
Clamp voltage with ESD strike
IIO
Leakage current through external signal pins (2)
IOFF
Current from IO Port to supply pins when powered
5V_SUPPLY = 0 V, VIO = 2.5 V
down through signal pins (3)
VD
Diode forward voltage through external signal
pins (2); lower clamp diode
ID = 8 mA
RDYN
Dynamic resistance of ESD clamps external
pins (3)
Pin to ground (2)
CIO_TMDS
IO capacitance Dx+, Dx– pins to GND
ΔCIO_TMDS
Differential capacitance for the Dx+, Dx– lines
CIO_CONTRO
CTRLx pin capacitance
L
VBR
(1)
(2)
(3)
Break-down voltage through signal pins
(3)
5V_SUPPLY =5V, VIO = 5 V
V
2
7
65
nA
1
5
44
nA
0.7
0.85
0.95
V
0.5
Ω
5V_SUPPLY = 5 V, VIO = 2.5 V
1
pF
5V_SUPPLY = 5 V, VIO = 2.5 V
0.05
pF
5V_SUPPLY = 5 V, VIO = 2.5 V
1
pF
IIO = 1 mA
6
V
Non-repetitive current pulse 8/20 µs exponentially decaying waveform according to IEC61000-4-5
Extraction of RDYN using least squares fit of TLP characteristics between I=1A AND I=10A
Signal pins are Dx+, Dx–, and CTRLx
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TPD13S523
SLVSBC5A – MARCH 2012 – REVISED MAY 2012
www.ti.com
1.98
Capacitance - pF
1.48
0.98
0.48
-0.02
0
0.5
1
1.5
2
2.5
VBIAS - V
3
3.5
4
4.5
5
3.6
36
3.2
32
2.8
28
2.4
24
2
20
Current
16
1.6
1.2
12
Power
0.8
8
0.4
4
0
0
5
10
15
Power - W
Current - A
Figure 4. Pin Capacitance
20
25
30
Time - mS
35
40
45
0
50
Figure 5. IEC61000-4-5 (Surge) IPP and PPP Waveform
6
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TPD13S523
SLVSBC5A – MARCH 2012 – REVISED MAY 2012
200
60
180
40
160
20
140
0
120
-20
Voltage - V
Voltage - V
www.ti.com
100
80
60
-40
-60
-80
40
-100
20
-120
0
-140
-20
-160
-40
-180
-60
-15
15
45
75
105 135 165 195 225
Time - nS
Figure 6. IEC Positive Clamping Waveform using +8kV
Contact
-200
-15
15
45
75
105 135
Time - nS
165
195
225
Figure 7. IEC Negative Clamping Waveform using -8kV
Contact
10
RD ~ 0.5 W
9
8
Current - A
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10 11
Voltage - V
Figure 8. TLP Plot on Connector Pins
12
13
14
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TPD13S523
SLVSBC5A – MARCH 2012 – REVISED MAY 2012
www.ti.com
1
0.8
0.6
Current - mA
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1
0
1
2
3
4
5
Voltage - V
6
7
8
9
10
Figure 9. IV Curve on Signal Pins
7.5
7
6.5
6
V5VS
5.5
Voltage - V
5
4.5
4
3.5
3
2.5
V5VO
2
1.5
1
0.5
0
-0.5
0
10
20
30
40
50
60
Time - mS
70
80
90
100
Figure 10. Load Switch Start-up Transient Waveform. Cin=1µF, Cout=1µF, ISWITCH=55mA, TA=25°C
8
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TPD13S523
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SLVSBC5A – MARCH 2012 – REVISED MAY 2012
10
9
8
Current - mA
7
6
5
4
3
2
1
0
-40
-15
10
35
Temperature - °C
60
85
Figure 11. Load Switch Supply Current; 5V_SUPPLY=5V, 5VOUT=open
3
2.7
2.4
Resistance - W
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
-40
-15
10
35
Temperature - °C
60
85
Figure 12. Load Switch Resistance vs. Temperature
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TPD13S523
SLVSBC5A – MARCH 2012 – REVISED MAY 2012
www.ti.com
Figure 13. Eye diagram using EVM without TPD13S523 for
the TMDS Lines at 1080p, 340MHz pixel clock, 3.4Gbps
10
Figure 14. Eye diagram using EVM with TPD13S523 for the
TMDS Lines at 1080p, 340MHz pixel clock, 3.4Gbps
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PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2012
PACKAGING INFORMATION
Orderable Device
TPD13S523PWR
Status
(1)
ACTIVE
Package Type Package
Drawing
TSSOP
PW
Pins
Package Qty
16
2000
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CU NIPDAU Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-May-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPD13S523PWR
Package Package Pins
Type Drawing
TSSOP
PW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-May-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD13S523PWR
TSSOP
PW
16
2000
346.0
346.0
29.0
Pack Materials-Page 2
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