TI TPD4E1B06DCKR

TPD4E1B06
www.ti.com
SLVSBQ8A – DECEMBER 2012 – REVISED JANUARY 2013
Quad Channel High Speed ESD Protection Device
Check for Samples: TPD4E1B06
FEATURES
APPLICATIONS
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Provides System Level ESD Protection for
Low-Voltage IO Interfaces
IEC 61000-4-2 Level 4
– ±12kV (Contact discharge)
– ±15kV (Air-gap discharge)
IO Capacitance 1.0pF (Typ)
DC Breakdown Voltage 7V (Min)
Ultra low Leakage Current 10nA (Max)
Low ESD Clamping Voltage
Industrial Temperature Range: –40°C to 125°C
Small, Easy-to-Route DCK package
USB2.0
HDMI control lines
MIPI Bus
LVDS
SATA
DCK PACKAGE
2 mm x 2.1 mm x 0.95 mm
(0.65 mm pitch)
IO1
1
6
NC
IO2
2
5
IO4
GND
3
4
IO3
DESCRIPTION
The TPD4E1B06 is a quad channel ultra low cap ESD protection device. It offers ±12KV IEC air-gap and ±15KV
contact ESD protection. Its 1.0pF line capacitance makes it suitable for a wide range of applications. Typical
application areas are HDMI, USB2.0, Ethernet, and 1394 interfaces.
ORDERING INFORMATION
PACKAGE (1) (2)
TA
–40°C to 125°C
(1)
(2)
3000
Tape and reel
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TPD4E1B06DCKR
BYI
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TPD4E1B06
SLVSBQ8A – DECEMBER 2012 – REVISED JANUARY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
IO1
IO2
IO4
IO3
GND
GND
Figure 1. Circuit Schematic Diagram
TERMINAL FUNCTIONS
PIN
2
NAME
NUMBER
TYPE
IO1
1
I/O
IO2
2
I/O
IO3
4
I/O
IO4
5
I/O
NC
6
NC
GND
3
GND
DESCRIPTION
USAGE
ESD protected channel
Connect to data line as close to the connector as possible
No connect
Can be left floating, grounded, or connected to Vcc
Ground
Connect to ground
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPD4E1B06
TPD4E1B06
www.ti.com
SLVSBQ8A – DECEMBER 2012 – REVISED JANUARY 2013
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Operating temperature range
–40
125
°C
Storage temperature
–65
155
°C
IEC 61000-4-2 contact ESD
±12
kV
IEC 61000-4-2 air-gap ESD
±15
kV
IPP, peak pulse current (tp = 8/20 μs), IO pin to GND
3.5
A
PPP, peak pulse power (tp = 8/20 μs)
45
W
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VRWM
VCLAMP
TEST CONDITION
MIN
TYP MAX
Reverse stand-off voltage
Clamp voltage with ESD strike,
IO to GND
5.5
UNIT
V
IPP = 1 A, tp = 8/20 μSec, from I/O to GND or GND to I/O
10.5
V
IPP = 3A, tp = 8/20 μSec, from I/O to GND or GND to I/O
14.5
V
ITLP = 10A to 20 A, I/O to GND
1
ITLP = 10A to 20 A, GND to I/O
0.8
RDYN
Dynamic resistance
CL
Line capacitance
f = 1 MHz, VBIAS = 2.5 V
VBR
Break-down voltage
IIO = 1 mA, from I/O to GND or GND to I/O
ILEAK
Leakage current
VIO = 5.0 V
Ω
1
7
1
pF
9.5
V
10
nA
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPD4E1B06
3
TPD4E1B06
SLVSBQ8A – DECEMBER 2012 – REVISED JANUARY 2013
www.ti.com
TYPICAL CHARACTERISTICS
CURRENT
vs
VOLTAGE
CURRENT and POWER
vs
TIME
3.5
1.0
0.8
50
Current
Power
3.0
45
40
0.6
2.5
0.2
0.0
±0.2
25
1.5
20
15
10
±0.6
0.5
±0.8
5
0.0
±1.0
±10
±8
±6
±4
±2
0
2
4
6
8
Voltage (V)
0
0
±5
10
10
15
20
25
30
35
40
45
50
Time ( s)
C002
Figure 2. DC Voltage Sweep I-V Curve
Figure 3. Surge Curve (tp = 8/20μs), Pin IO to GND
CURRENT
vs
VOLTAGE
CURRENT
vs
TEMPERATURE
10
1.2
8
1.1
1.0
0.9
Current (nA)
4
2
0
±2
±4
0.8
0.7
0.6
0.5
0.4
0.3
±6
0.2
±8
0.1
0.0
±10
±24 ±20 ±16 ±12 ±8
±4
0
4
8
12
16
20
Voltage (V)
±40
24
±20
0
20
40
60
80
100
Temperature (ƒC)
C003
120
C004
Figure 4. TLP Plot IO to GND
Figure 5. Leakage vs Temperature
VOLTAGE
vs
TIME
VOLTAGE
vs
TIME
110
10
0
90
±10
80
±20
70
±30
Voltage (V)
100
60
50
40
±40
±50
±60
30
±70
20
±80
10
±90
0
±100
±10
±110
0
25
50
75
100
125
150
Time ( s)
175
200
0
C005
Figure 6. +8kV IEC Waveform
4
5
C001
6
Current (A)
30
2.0
1.0
±0.4
Voltage (V)
35
Power (W)
Current (A)
Current (mA)
0.4
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25
50
75
100
125
150
Time ( s)
175
200
C006
Figure 7. –8kV IEC Waveform
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPD4E1B06
TPD4E1B06
www.ti.com
SLVSBQ8A – DECEMBER 2012 – REVISED JANUARY 2013
APPLICATION INFORMATION
The TPD4E1B06DCK offers a unique pinout that allows straight through routing with no stubs. Figure 8 shows an
example layout. Pins 1 & 2 and pins 4 & 5 are routed differentially. Pin 3 is routed to the ground plane. Pin 6 is
not bonded internally in the device and does not need to be routed anywhere on the board. It is also okay if pin 6
is connected to power plane or a capacitor.
Figure 8. TPD4E1B06 Layout Example
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPD4E1B06
5
TPD4E1B06
SLVSBQ8A – DECEMBER 2012 – REVISED JANUARY 2013
www.ti.com
REVISION HISTORY
Changes from Original (December 2012) to Revision A
•
6
Page
Fixed "f" units typo from GHz to MHz for CL parameter in ELECTRICAL CHARACTERISTICS table. ............................... 3
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPD4E1B06
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPD4E1B06DCKR
ACTIVE
Package Type Package Pins Package Qty
Drawing
SC70
DCK
6
3000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU NIPDAU
Level-1-260C-UNLIM
(4)
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPD4E1B06DCKR
Package Package Pins
Type Drawing
SC70
DCK
6
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
178.0
9.0
Pack Materials-Page 1
2.4
B0
(mm)
K0
(mm)
P1
(mm)
2.5
1.2
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD4E1B06DCKR
SC70
DCK
6
3000
180.0
180.0
18.0
Pack Materials-Page 2
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