TDA7498MV 100 W mono BTL class-D audio amplifier Datasheet - production data • • • • • Differential inputs minimize common-mode noise Standby and mute features Short-circuit protection Thermal overload protection Externally synchronizable Description PowerSSO-36 exposed pad up The TDA7498MV is a mono BTL class-D audio amplifier with single power supply designed for home systems and active speaker applications. Features • • • • • 100 W output power at THD = 10% with RL = 6 Ω and VCC = 36 V 80 W output power at THD = 10% with RL = 8 Ω and VCC = 34 V Wide-range single-supply operation (14 - 39 V) High efficiency (η = 90%) Four selectable, fixed gain settings of nominally 25.6 dB, 31.6 dB, 35.1 dB and 37.6 dB September 2015 It comes in a 36-pin PowerSSO package with exposed pad up (EPU) to facilitate mounting a separate heatsink. Table 1: Device summary Order code TDA7498MVTR DocID016505 Rev 6 This is information on a product in full production. Operating temp. range -40 to 85 °C Package PowerSSO36 (EPU) Packaging Tape and reel 1/26 www.st.com Contents TDA7498MV Contents 1 Device block diagram...................................................................... 5 2 Pin description ................................................................................ 6 3 4 5 6 2.1 Pinout ................................................................................................ 6 2.2 Pin list ............................................................................................... 7 Electrical specifications .................................................................. 8 3.1 Absolute maximum ratings ................................................................ 8 3.2 Thermal data ..................................................................................... 8 3.3 Recommended operating conditions ................................................. 8 3.4 Electrical specifications ..................................................................... 9 Characterization curves ................................................................ 11 4.1 Test board ....................................................................................... 11 4.2 Characterization curves .................................................................. 12 2/26 For RL = 6 Ω...................................................................................... 12 4.2.2 For RL = 8 Ω...................................................................................... 14 Application information ................................................................ 16 5.1 Application circuit ............................................................................ 16 5.2 Mode selection ................................................................................ 17 5.3 Gain setting ..................................................................................... 18 5.4 Input resistance and capacitance .................................................... 18 5.5 Internal and external clocks ............................................................ 19 5.5.1 Master mode (internal clock) ............................................................ 19 5.5.2 Slave mode (external clock) ............................................................. 19 5.6 Output low-pass filter ...................................................................... 20 5.7 Protection functions......................................................................... 20 5.8 Diagnostic output ............................................................................ 21 Package information ..................................................................... 22 6.1 7 4.2.1 PowerSSO-36 EPU package information ........................................ 22 Revision history ............................................................................ 25 DocID016505 Rev 6 TDA7498MV List of tables List of tables Table 1: Device summary ........................................................................................................................... 1 Table 2: Pin description list ......................................................................................................................... 7 Table 3: Absolute maximum ratings ........................................................................................................... 8 Table 4: Thermal data ................................................................................................................................. 8 Table 5: Recommended operating conditions ............................................................................................ 8 Table 6: Electrical specifications ................................................................................................................. 9 Table 7: Mode settings.............................................................................................................................. 17 Table 8: Gain settings ............................................................................................................................... 18 Table 9: How to set up SYNCLK .............................................................................................................. 19 Table 10: PowerSSO-36 EPU package mechanical data ........................................................................ 24 Table 11: Document revision history ........................................................................................................ 25 DocID016505 Rev 6 3/26 List of figures TDA7498MV List of figures Figure 1: Internal block diagram ................................................................................................................. 5 Figure 2: Pin connections (top view, PCB view) ......................................................................................... 6 Figure 3: Test board.................................................................................................................................. 11 Figure 4: Output power (THD = 10%) vs. supply voltage ......................................................................... 12 Figure 5: THD vs. output power ................................................................................................................ 12 Figure 6: THD vs. frequency (1 W) ........................................................................................................... 12 Figure 7: THD vs. frequency (100 mW) .................................................................................................... 12 Figure 8: Frequency response .................................................................................................................. 13 Figure 9: FFT performance (0 dBFS) ....................................................................................................... 13 Figure 10: FFT performance (-60 dBFS) .................................................................................................. 13 Figure 11: Output power (THD = 10%) vs. supply voltage ....................................................................... 14 Figure 12: THD vs. output power .............................................................................................................. 14 Figure 13: THD vs. frequency (1 W) ......................................................................................................... 14 Figure 14: THD vs. frequency (100 mW) .................................................................................................. 14 Figure 15: Frequency response ................................................................................................................ 15 Figure 16: FFT performance (0 dB) .......................................................................................................... 15 Figure 17: FFT performance (-60 dB) ....................................................................................................... 15 Figure 18: Application circuit ..................................................................................................................... 16 Figure 19: Standby and mute circuits ....................................................................................................... 17 Figure 20: Turn on/off sequence for minimizing speaker “pop” ................................................................ 17 Figure 21: Input circuit and frequency response ...................................................................................... 18 Figure 22: Master and slave connection ................................................................................................... 19 Figure 23: Typical LC filter for an 8 Ω speaker ......................................................................................... 20 Figure 24: Typical LC filter for a 6 Ω speaker ........................................................................................... 20 Figure 25: Behavior of pin DIAG for various protection conditions ........................................................... 21 Figure 26: PowerSSO-36 EPU package outline ....................................................................................... 23 4/26 DocID016505 Rev 6 TDA7498MV 1 Device block diagram Device block diagram Figure 1: "Internal block diagram" shows the block diagram of the TDA7498MV. Figure 1: Internal block diagram DocID016505 Rev 6 5/26 Pin description TDA7498MV 2 Pin description 2.1 Pinout Figure 2: Pin connections (top view, PCB view) SUB_GND 1 SVCC N.C. 2 34 VREF N.C. 3 33 SGND2 N.C. 4 32 VDDS2 N.C. 5 31 GAIN1 N.C. 6 30 GAIN0 N.C. 7 29 SVR N.C. 8 N.C. 9 36 VSS 35 28 DIAG 27 SGND OUTN 10 26 VDDS OUTN 25 SYNCLK PVCC 12 24 ROSC PVCC 13 23 INN PGND 14 22 INP 21 MUTE 6/26 EP, exposed pad Connect to ground 11 PGND 15 OUTP 16 20 STBY OUTP 17 19 VDDPW PGND 18 DocID016505 Rev 6 TDA7498MV 2.2 Pin description Pin list Table 2: Pin description list Number Name Type Description 1 SUB_GND PWR Connect to the frame 2, 3 NC - No internal connection 4, 5 NC - No internal connection 6, 7 NC - No internal connection 8, 9 NC - No internal connection 10, 11 OUTN O Negative PWM output for audio channel 12, 13 PVCC PWR Power supply for audio channel 14, 15 PGND PWR Power stage ground 16, 17 OUTP O Positive PWM output for audio channel 18 PGND PWR Power stage ground 19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power stage 20 STBY I Standby mode control 21 MUTE I Mute mode control 22 INP I Positive differential input 23 INN I Negative differential input 24 ROSC O Master oscillator frequency-setting pin 25 SYNCLK I/O Clock in/out for external oscillator 26 VDDS O 3.3-V (nominal) regulator output referred to ground for signal blocks 27 SGND PWR Signal ground 28 DIAG O Open-drain diagnostic output 29 SVR O Supply voltage rejection 30 GAIN0 I Gain setting input 1 31 GAIN1 I Gain setting input 2 32 VDDS2 O Connect to VDDS (pin 26) 33 SGND2 PWR Connect to SGND (pin 27) 34 VREF O Half VDDS (nominal) referred to ground 35 SVCC PWR Signal power supply decoupling 36 VSS O 3.3-V (nominal) regulator output referred to power supply - EP - Exposed pad for heatsink, to be connected to ground DocID016505 Rev 6 7/26 Electrical specifications TDA7498MV 3 Electrical specifications 3.1 Absolute maximum ratings Table 3: Absolute maximum ratings Symbol Parameter Value Unit VCC_MAX DC supply voltage for pins PVCCA, PVCCB, SVCC 45 V VL_MAX Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN0, GAIN1 -0.3 to 3.6 V Tj_MAX Operating junction temperature 0 to 150 °C Top_MAX Operating temperature -40 to 85 °C Tstg Storage temperature -40 to 150 °C Warning: Stresses beyond those listed under “Absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended operating condition” are not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. In the real application, the power supply with nominal value rated inside recommended operating conditions may rise beyond the maximum operating condition for a short time when no or very low current is sunk (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum rating is not exceeded. 3.2 Thermal data Table 4: Thermal data Symbol Rth j-case 3.3 Parameter Thermal resistance, junction to case Min Typ Max - 2 3 Unit °C/W Recommended operating conditions Table 5: Recommended operating conditions Symbol 8/26 Parameter Min Typ Max Unit VCC Supply voltage for pins PVCCA, PVCCB 14 - 39 V Tamb Ambient operating temperature -20 - 85 °C DocID016505 Rev 6 TDA7498MV 3.4 Electrical specifications Electrical specifications Unless otherwise stated, the values in the table below are specified for the conditions: VCC = 36 V, RL = 6 Ω, ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 25.6 dB and Tamb = 25 °C. Table 6: Electrical specifications Symbol Parameter Condition Min Typ Max Unit Iq Total quiescent current No LC filter, no load - 40 60 mA IqSTBY Quiescent current in standby - - 1 10 µA VOS Output offset voltage Play mode -100 - 100 Mute mode -60 - 60 IOCP Overcurrent protection threshold RL = 0 Ω 5.5 7 - A TjS Junction temperature at thermal shutdown - - 150 - °C Ri Input resistance Differential input 48 60 - kΩ VOVP Overvoltage protection threshold - 42 43 - V VUVP Undervoltage protection threshold - - - 8 V RdsON Power transistor on-resistance High side - 0.2 - Low side - 0.2 - Po Output power THD = 10% - 100 - THD = 1% - 78 - Po Output power RL = 8 Ω, THD = 10%, VCC = 36 V - 80 - W PD Dissipated power Po = 100 W, THD = 10% - 10 - W η Efficiency Po = 100 W - 90 - % THD Total harmonic distortion Po = 1 W - 0.1 - % GAIN0 = L, GAIN1 = L 24.6 25.6 26.6 GAIN0 = L, GAIN1 = H 30.6 31.6 32.6 GAIN0 = H, GAIN1 = L 34.1 35.1 36.1 GAIN0 = H, GAIN1 = H 36.6 37.6 38.6 - -1 - 1 A Curve, GV = 20 dB - 15 - f = 22 Hz to 22 kHz - 25 50 GV Closed-loop gain mV Ω W dB ΔGV Gain matching eN Total input noise SVRR Supply voltage rejection ratio fr = 100 Hz, Vr = 0.5 Vpp, CSVR = 10 µF - 70 - dB Tr, Tf Rise and fall times - - 50 - ns fSW Switching frequency Internal oscillator 290 310 330 kHz 250 - 400 250 - 400 2.3 - - With internal oscillator (1) fSWR Output switching frequency range With external oscillator VinH Digital input high (H) - DocID016505 Rev 6 (2) dB µV kHz V 9/26 Electrical specifications Symbol TDA7498MV Parameter VinL Condition Digital input low (L) Pin STBY voltage high (H) VSTBY Pin STBY voltage low (L) Pin MUTE voltage high (H) VMUTE Pin MUTE voltage low (L) AMUTE Mute attenuation - VMUTE < 0.8 V Min Typ Max - - 0.8 2.9 - - - - 0.5 2.5 - - - - 0.8 - 70 - Notes: (1) 6 fSW = 10 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 kΩ (see Figure 18: "Application circuit"). (2) 10/26 fSW = fSYNCLK / 2 with the external oscillator. DocID016505 Rev 6 Unit V V dB TDA7498MV 4 Characterization curves Characterization curves Figure 18: "Application circuit" shows the test circuit with which the characterization curves, shown in the next sections, were measured. Figure 3: "Test board" shows the PCB layout. 4.1 Test board Figure 3: Test board Top view Top copper Bottom view Bottom copper DocID016505 Rev 6 11/26 Characterization curves 4.2 TDA7498MV Characterization curves Unless otherwise stated the measurements were made under the following conditions: VCC = 36 V, f = 1 kHz, GV = 25.6 dB, ROSC = 39 kΩ, COSC = 100 nF, Tamb = 25 °C 4.2.1 For RL = 6 Ω Figure 4: Output power (THD = 10%) vs. supply voltage Figure 5: THD vs. output power 10 120 5 110 2 100 1 80 THD+N (%) Output power (W) 90 70 0.5 0.2 60 f = 1 kHz 0.1 50 0.05 40 f = 100 Hz 30 0.02 20 0.01 10 0.005 100m +10 +12 +14 +16 +1 8 +20 +22 +24 +26 +2 8 +30 +32 +34 200m 500m 1 2 +36 5 10 20 50 100 200 Output power (W) Su pply voltage (V) Figure 7: THD vs. frequency (100 mW) 2 2 1 1 0.5 0.5 0.2 0.2 THD+N ( %) THD+N (%) Figure 6: THD vs. frequency (1 W) 0.1 0.05 0.05 0.02 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 20k 0.01 20 50 100 200 500 1k Fre quency (Hz) Fre quency (Hz) 12/26 0.1 DocID016505 Rev 6 2k 5k 10k 20k TDA7498MV Characterization curves Figure 8: Frequency response Figure 9: FFT performance (0 dBFS) +3 +0 -10 +2.5 -20 +2 -30 -40 +1.5 -50 -60 -70 +0.5 FFT (dB) Ampl (dB) +1 +0 -0.5 -80 -90 -100 -110 -120 -1 -130 -1.5 -140 -150 -2 -160 -2.5 -3 -170 -180 10 20 50 100 200 500 1k 2k 5k 10k 20k Fre quency (Hz) 20 50 100 200 500 1k 2k 5k 10k 20k Fre quency (Hz) Figure 10: FFT performance (-60 dBFS) +0 -10 -20 -30 -40 -50 -60 FFT (dB) -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Fre quency (Hz) DocID016505 Rev 6 13/26 Characterization curves 4.2.2 TDA7498MV For RL = 8 Ω Figure 11: Output power (THD = 10%) vs. supply voltage Figure 12: THD vs. output power 10 120 5 110 2 100 1 0.5 80 THD+N (% ) O utput power (W) 90 70 60 50 0.2 f = 1 kHz 0.1 0.05 40 0.02 30 f = 100 Hz 0.01 20 10 +10 +12 +14 +16 +1 8 +20 +22 +24 +26 +2 8 +30 +32 +34 0.005 100m +36 200m 500m 1 2 2 1 1 0.5 0.5 0.2 0.2 THD+N ( % ) THD+N ( % ) 2 0.1 0.05 0.02 0.02 50 100 200 500 1k 2k 5k 10k 20k 0.01 20 50 100 200 500 1k Fre quency (Hz) Fre quency (Hz) 14/26 20 50 100 200 0.1 0.05 20 10 Figure 14: THD vs. frequency (100 mW) Figure 13: THD vs. frequency (1 W) 0.01 5 O utput power (W) Su pply voltage (V) DocID016505 Rev 6 2k 5k 10k 20k TDA7498MV Characterization curves Figure 16: FFT performance (0 dB) Figure 15: Frequency response Figure 17: FFT performance (-60 dB) +0 -10 -20 -30 -40 -50 -60 FFT (dB) -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Fre quency (Hz) DocID016505 Rev 6 15/26 Application information TDA7498MV 5 Application information 5.1 Application circuit Figure 18: Application circuit 1 C1 1µF C2 1µF J9 C5 100nF 1 SUB_GN D 22 IN P C3 1nF 23 INN C4 1nF 27 SGND VDDS 26 VDDS J7 For R7 100k 22R DIAG PGND 14 PGND 15 28 DIAG PVCC 12 PVCC 13 OUTN 18 PGND 25 SYNC LK Frequency shift 100nF 39K J5 30 VDDS 31 10 ROSC TDA7498M V GAIN 0 * C3 0 C2 6 1µ F 680nF C4 0 J3 * OU T-1 OU T-2 C4 1 C2 4 220nF 220nF OUTPU T R1 6 Load = 6 ohm 8R 330pF L3 11 * IC 3 22µH C2 3 R3 24 8R 220n F C2 7 C6 100nF R1 5 * C2 8 22R 19 VDD PW OUTN C8 * 22µH R6 C2 5 input R9 Q1 KTC3875(S) 180K 3 R1 3 FS 1 47k 2 R1 4 100k L4 100nF R1 single-ended 16 17 220nF 2 INPU T OUT P OUT P NC 3 NC 2 2 VC C + 2200µF 1 50 V NC 7 NC 6 GN D J2 GAIN 1 J6 35 SVC C C1 0 100nF 36 32 3V3 33 J4 S2 MUTE 1 3 2 S1 STB Y 1 3 2 120k R2 C2 9 2.2µF IN IC 2 L4931CZ3 3 3 2 GN D C9 100nF 4 NC 9 Load L1,L2 C26 C24,C28 NC 8 6 ohm 22 µH 680 nF 220 nF 34 8 oh m 22 µH 470 nF 21 220 nF + + C1 5 2.2µF 16V 20 LC filter components SGND2 MUTE C1 7 STB Y SVR 29 10µF 10V C1 6 C7 2.2µF 16V 10µF TDA7498MV VCC CLASS-D AMPLIFIER 3V3 Power supply 16/26 5 10V R8 6.8k D1 18V NC NC VREF R4 33k 1 VDDS2 VDDS FS OU T VSS DocID016505 Rev 6 TDA7498MV 5.2 Application information Mode selection The three operating modes of the TDA7498MV are set by the two inputs, STBY (pin 20) and MUTE (pin 21). • • Standby mode: all circuits are turned off, very low current consumption. Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty cycle. Play mode: the amplifiers are active. • The protection functions of the TDA7498MV are enabled by pulling down the voltages of the STBY and MUTE inputs shown in Figure 19: "Standby and mute circuits". The input current of the corresponding pins must be limited to 200 µA. Table 7: Mode settings Mode STBY MUTE L (1) X (don’t care) Mute H (1) L Play H Standby H Notes: (1) Drive levels defined in Figure 19: Standby and mute circuits Figure 20: Turn on/off sequence for minimizing speaker “pop” DocID016505 Rev 6 17/26 Application information 5.3 TDA7498MV Gain setting The gain of the TDA7498MV is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin31). Internally, the gain is set by changing the feedback resistors of the amplifier. Table 8: Gain settings GAIN0 5.4 GAIN1 Nominal gain, Gv (dB) L L 25.6 L H 31.6 H L 35.6 H H 37.6 Input resistance and capacitance The input impedance is set by an internal resistor Ri = 60 kΩ (typical). An input capacitor (Ci) is required to couple the AC input signal. The equivalent circuit and frequency response of the input components are shown in Figure 21: "Input circuit and frequency response". For Ci = 470 nF the high-pass filter cutoff frequency is below 20 Hz: fC = 1 / (2 * π * Ri * Ci) Figure 21: Input circuit and frequency response 18/26 DocID016505 Rev 6 TDA7498MV 5.5 Application information Internal and external clocks The clock of the class-D amplifier can be generated internally or can be driven by an external source. If two or more class-D amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. This can be implemented by using one TDA7498MV as master clock, while the other devices are in slave mode, that is, externally clocked. The clock interconnect is via pin SYNCLK of each device. As explained below, SYNCLK is an output in master mode and an input in slave mode. 5.5.1 Master mode (internal clock) Using the internal oscillator, the output switching frequency, fSW , is controlled by the resistor, ROSC, connected to pin ROSC: 6 fSW = 10 / [(ROSC * 16 + 182) * 4] kHz where ROSC is in kΩ. In master mode, pin SYNCLK is used as a clock output pin whose frequency is: fSYNCLK = 2 * fSW For master mode to operate correctly then resistor ROSC must be less than 60 kΩ as given below in Table 9: "How to set up SYNCLK". 5.5.2 Slave mode (external clock) In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin SYNCLK to be internally configured as an input as given in Table 9: "How to set up SYNCLK". The output switching frequency of the slave devices is: fSW = fSYNCLK / 2 Table 9: How to set up SYNCLK Mode ROSC SYNCLK Master ROSC < 60 kΩ Output Slave Floating (not connected) Input Figure 22: Master and slave connection DocID016505 Rev 6 19/26 Application information 5.6 TDA7498MV Output low-pass filter To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The cutoff frequency should be larger than 22 kHz and much lower than the output switching frequency. It is necessary to choose the L and C component values depending on the loudspeaker impedance. Some typical values, which give a cutoff frequency of 27 kHz, are shown in Figure 23: "Typical LC filter for an 8 Ω speaker" and Figure 24: "Typical LC filter for a 6 Ω speaker" below. Figure 23: Typical LC filter for an 8 Ω speaker Figure 24: Typical LC filter for a 6 Ω speaker 5.7 Protection functions The TDA7498MV is fully protected against overvoltages, undervoltages, overcurrents and thermal overloads as explained here. Overvoltage protection (OVP) If the supply voltage exceeds the value for VOVP given in Table 6: "Electrical specifications ", the overvoltage protection is activated which forces the outputs to the high impedance state. When the supply voltage falls back to within the operating range, the device restarts. 20/26 DocID016505 Rev 6 TDA7498MV Application information Undervoltage protection (UVP) If the supply voltage drops below the value for VUVP given in Table 6: "Electrical specifications ", the undervoltage protection is activated which forces the outputs to the high impedance state. When the supply voltage recovers to within the operating range, the device restarts. Overcurrent protection (OCP) If the output current exceeds the value for IOCP given in Table 6: "Electrical specifications ", the overcurrent protection is activated which forces the outputs to the high impedance state. Periodically, the device attempts to restart. If the overcurrent condition is still present, then the OCP remains active. The restart time, TOC, is determined by the RC components connected to pin STBY. Thermal protection (OTP) If the junction temperature, Tj, reaches 145 °C (nominally), the device goes to mute mode and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction temperature reaches the value for Tj given in Table 6: "Electrical specifications ", the device shuts down and the output is forced to the high-impedance state. When the device cools sufficiently, the device restarts. 5.8 Diagnostic output The output pin DIAG is an open drain transistor. When any protection is activated, it switches to the high impedance state. The pin can be connected to a power supply (< 39 V) by a pull-up resistor whose value is limited by the maximum sinking current (200 µA) of the pin. Figure 25: Behavior of pin DIAG for various protection conditions VDD TDA7498MV R1 DIAG Protection logic VDD Restart Restart Overcurrent protection OV, UV, OT protection DocID016505 Rev 6 21/26 Package information 6 TDA7498MV Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 6.1 PowerSSO-36 EPU package information The device comes in a 36-pin PowerSSO package with exposed pad up (EPU). Figure 26: "PowerSSO-36 EPU package outline" shows the package outline and Table 10: "PowerSSO-36 EPU package mechanical data" gives the dimensions. 22/26 DocID016505 Rev 6 TDA7498MV Package information Figure 26: PowerSSO-36 EPU package outline 7618147_F DocID016505 Rev 6 23/26 Package information TDA7498MV Table 10: PowerSSO-36 EPU package mechanical data Dimensions in mm Dimensions in inches Symbol 24/26 Min. Typ. Max. Min. Typ. Max. A 2.15 - 2.45 0.085 - 0.096 A2 2.15 - 2.35 0.085 - 0.093 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees L 0.55 - 0.85 0.022 - 0.033 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 4.90 - 7.10 0.193 - 0.280 DocID016505 Rev 6 TDA7498MV 7 Revision history Revision history Table 11: Document revision history Date 30-Nov-2009 Revision Changes 1 Initial release. 28-Jul-2010 2 Removed datasheet preliminary status, updated features list and updated Table 1: "Device summary" Added operating temperature range to Table 3: "Absolute maximum ratings" Updated minimum supply voltage and temperature range in Table 5: "Recommended operating conditions" Updated voltage for logical 1 on pin STBY in Table 6: "Electrical specifications " 27-Jan-2011 3 Updated application circuit in Figure 18: "Application circuit". 24-Feb-2014 4 Updated order code in Table 1: "Device summary" 19-Sep-2014 5 Updated Figure 2: "Pin connections (top view, PCB view)" Updated package information (representation on page 1, Figure 26: "PowerSSO-36 EPU package outline", Table 10: "PowerSSO-36 EPU package mechanical data"). 09-Sep-2015 6 Updated VCC_MAX in Table 3: "Absolute maximum ratings" Updated dimension L in Table 10: "PowerSSO-36 EPU package mechanical data". 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All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 26/26 DocID016505 Rev 6