TDA7498L 80-watt + 80-watt dual BTL class-D audio amplifier Datasheet - production data • • • • • Differential inputs minimize common-mode noise Standby and mute features Short-circuit protection Thermal overload protection Externally synchronizable Description PowerSSO-36 exposed pad up The TDA7498L is a dual BTL class-D audio amplifier with single power supply designed for home systems and active speaker applications. Features • • • • • 80 W + 80 W output power at THD = 10% with RL = 6 Ω and VCC = 32 V 70 W + 70 W output power at THD = 10% with RL = 8 Ω and VCC = 34 V Wide-range single-supply operation (14 - 36 V) High efficiency (η = 90%) Four selectable, fixed gain settings of nominally 25.6 dB, 31.6 dB, 35.1 dB and 37.6 dB September 2015 It comes in a 36-pin PowerSSO package with exposed pad up (EPU) to facilitate mounting a separate heatsink. Table 1: Device summary Order code Package Packaging TDA7498L -40 to 85 °C PowerSSO36 (EPU) Tube TDA7498LTR -40 to 85 °C PowerSSO36 (EPU) Tape and reel DocID16504 Rev 4 This is information on a product in full production. Operating temp. range 1/27 www.st.com Contents TDA7498L Contents 1 Device block diagram...................................................................... 5 2 Pin description ................................................................................ 6 3 4 5 6 2.1 Pinout ................................................................................................ 6 2.2 Pin list ............................................................................................... 7 Electrical specifications .................................................................. 8 3.1 Absolute maximum ratings ................................................................ 8 3.2 Thermal data ..................................................................................... 8 3.3 Recommended operating conditions ................................................. 8 3.4 Electrical specifications ..................................................................... 9 Characterization curves ................................................................ 11 4.1 PCB layout ...................................................................................... 11 4.2 Characterization curves .................................................................. 12 2/27 For RL = 6 Ω...................................................................................... 12 4.2.2 For RL = 8 Ω...................................................................................... 14 Application information ................................................................ 16 5.1 Application circuit ............................................................................ 16 5.2 Mode selection ................................................................................ 17 5.3 Gain setting ..................................................................................... 18 5.4 Input resistance and capacitance .................................................... 19 5.5 Internal and external clocks ............................................................ 20 5.5.1 Master mode (internal clock) ............................................................ 20 5.5.2 Slave mode (external clock) ............................................................. 20 5.6 Output low-pass filter ...................................................................... 21 5.7 Protection functions......................................................................... 22 5.8 Diagnostic output ............................................................................ 22 Package information ..................................................................... 23 6.1 7 4.2.1 PowerSSO-36 EPU package information ........................................ 23 Revision history ............................................................................ 26 DocID16504 Rev 4 TDA7498L List of tables List of tables Table 1: Device summary ........................................................................................................................... 1 Table 2: Pin description list ......................................................................................................................... 7 Table 3: Absolute maximum ratings ........................................................................................................... 8 Table 4: Thermal data ................................................................................................................................. 8 Table 5: Recommended operating conditions ............................................................................................ 8 Table 6: Electrical specifications ................................................................................................................. 9 Table 7: Mode settings.............................................................................................................................. 17 Table 8: Gain settings ............................................................................................................................... 18 Table 9: How to set up SYNCLK .............................................................................................................. 20 Table 10: PowerSSO-36 EPU package mechanical data ........................................................................ 25 Table 11: Document revision history ........................................................................................................ 26 DocID16504 Rev 4 3/27 List of figures TDA7498L List of figures Figure 1: Internal block diagram (showing one channel only) .................................................................... 5 Figure 2: Pin connections (top view, PCB view) ......................................................................................... 6 Figure 3: Test board.................................................................................................................................. 11 Figure 4: Output power vs. supply voltage ............................................................................................... 12 Figure 5: THD vs. output power (1 kHz) ................................................................................................... 12 Figure 6: THD vs. output power (100 Hz) ................................................................................................. 12 Figure 7: THD vs. frequency (1 W) ........................................................................................................... 12 Figure 8: THD vs. frequency (100 mW) .................................................................................................... 13 Figure 9: Frequency response .................................................................................................................. 13 Figure 10: FFT performance (0 dBFS) ..................................................................................................... 13 Figure 11: FFT performance (-60 dBFS) .................................................................................................. 13 Figure 12: Output power vs. supply voltage ............................................................................................. 14 Figure 13: THD vs. output power (1 kHz) ................................................................................................. 14 Figure 14: THD vs. output power (100 Hz) ............................................................................................... 14 Figure 15: THD vs. frequency (1 W) ......................................................................................................... 14 Figure 16: THD vs. frequency (100 mW) .................................................................................................. 15 Figure 17: Frequency response ................................................................................................................ 15 Figure 18: FFT performance (0 dB) .......................................................................................................... 15 Figure 19: FFT performance (-60 dB) ....................................................................................................... 15 Figure 20: Application circuit ..................................................................................................................... 16 Figure 21: Standby and mute circuits ....................................................................................................... 17 Figure 22: Turn on/off sequence for minimizing speaker “pop” ................................................................ 18 Figure 23: Input circuit and frequency response ...................................................................................... 19 Figure 24: Master and slave connection ................................................................................................... 20 Figure 25: Typical LC filter for an 8 Ω speaker ......................................................................................... 21 Figure 26: Typical LC filter for a 6 Ω speaker ........................................................................................... 21 Figure 27: Behavior of pin DIAG for various protection conditions ........................................................... 22 Figure 28: PowerSSO-36 EPU package outline ....................................................................................... 24 4/27 DocID16504 Rev 4 TDA7498L 1 Device block diagram Device block diagram Figure 1: "Internal block diagram (showing one channel only)" shows the block diagram of one of the two identical channels of the TDA7498L. Figure 1: Internal block diagram (showing one channel only) DocID16504 Rev 4 5/27 Pin description TDA7498L 2 Pin description 2.1 Pinout Figure 2: Pin connections (top view, PCB view) SUB_GND 1 SVCC OUTPB 2 VREF OUTPB 3 33 INNB PGNDB 4 32 PGNDB 5 31 GAIN1 PVCCB 6 30 GAIN0 PVCCB 7 OUTNB 8 28 DIAG OUTNB 9 27 SGND OUTNA 10 26 VDDS OUTNA 11 25 SYNCLK PVCCA 12 24 ROSC PVCCA 13 23 INNA PGNDA 14 PGNDA 15 OUTPA 16 OUTPA 17 PGND 18 36 VSS 35 34 29 INPB SVR 22 INPA 21 MUTE EP, exposed pad Connect to ground 20 STBY 19 VDDPW 6/27 DocID16504 Rev 4 TDA7498L 2.2 Pin description Pin list Table 2: Pin description list Number Name Type Description 1 SUB_GND PWR Connect to the frame 2,3 OUTPB O Positive PWM for right channel 4,5 PGNDB PWR Power stage ground for right channel 6,7 PVCCB PWR Power supply for right channel 8,9 OUTNB O Negative PWM output for right channel 10,11 OUTNA O Negative PWM output for left channel 12,13 PVCCA PWR Power supply for left channel 14,15 PGNDA PWR Power stage ground for left channel 16,17 OUTPA O Positive PWM output for left channel 18 PGND PWR Power stage ground 19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power stage 20 STBY I Standby mode control 21 MUTE I Mute mode control 22 INPA I Positive differential input of left channel 23 INNA I Negative differential input of left channel 24 ROSC O Master oscillator frequency-setting pin 25 SYNCLK I/O Clock in/out for external oscillator 26 VDDS O 3.3-V (nominal) regulator output referred to ground for signal blocks 27 SGND PWR Signal ground 28 DIAG O Open-drain diagnostic output 29 SVR O Supply voltage rejection 30 GAIN0 I Gain setting input 1 31 GAIN1 I Gain setting input 2 32 INPB I Positive differential input of right channel 33 INNB I Negative differential input of right channel 34 VREF O Half VDDS (nominal) referred to ground 35 SVCC PWR Signal power supply decoupling 36 VSS O 3.3-V (nominal) regulator output referred to power supply - EP - Exposed pad for heatsink, to be connected to ground DocID16504 Rev 4 7/27 Electrical specifications TDA7498L 3 Electrical specifications 3.1 Absolute maximum ratings Table 3: Absolute maximum ratings Symbol Parameter VCC_MAX DC supply voltage for pins PVCCA, PVCCB, SVCC VL_MAX Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN0, GAIN1 Tj_MAX Operating junction temperature Tstg Storage temperature Value Unit 45 V -0.3 to 3.6 V 0 to 150 °C -40 to 150 °C Warning: Stresses beyond those listed under “Absolute maximum ratings” make cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended operating condition” are not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. In the real application, the power supply with the nominal value rated in the recommended operating conditions may rise beyond the maximum operating condition for a short time when no or very low current is sunk (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum rating is not exceeded. 3.2 Thermal data Table 4: Thermal data Symbol Rth j-case 3.3 Parameter Thermal resistance, junction to case Min Typ Max - 2 3 Unit °C/W Recommended operating conditions Table 5: Recommended operating conditions Symbol 8/27 Parameter Min Typ Max Unit VCC Supply voltage for pins PVCCA, PVCCB 14 - 36 V Tamb Ambient operating temperature -20 - 85 °C DocID16504 Rev 4 TDA7498L 3.4 Electrical specifications Electrical specifications Unless otherwise stated, the values in the table below are specified for the conditions: VCC = 32 V, RL = 6 Ω, ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 25.6 dB Tamb = 25 °C. Table 6: Electrical specifications Symbol Parameter Condition Min Typ Max Unit Iq Total quiescent current No LC filter, no load - 40 60 mA IqSTBY Quiescent current in standby - - 1 10 µA VOS Output offset voltage Play mode -100 - 100 Mute mode -60 - 60 IOCP Overcurrent protection threshold RL = 0 Ω 5.0 6.0 - A TjS Junction temperature at thermal shutdown - - 150 - °C Ri Input resistance Differential input 48 60 - kΩ VOVP Overvoltage protection threshold - 42 43 - V VUVP Undervoltage protection threshold - - - 8 V RdsON Power transistor on-resistance High side - 0.2 - Low side - 0.2 - Po Output power THD = 10% - 80 - THD = 1% - 65 - Po Output power RL = 8 Ω, THD = 10%, VCC = 32 V - 65 - W PD Dissipated power Po = 80 W + 80 W, THD = 10% - 16 - W η Efficiency Po = 80 W + 80 W - 90 - % THD Total harmonic distortion Po = 1 W - 0.1 - % GAIN0 = L, GAIN1 = L 24.6 25.6 26.6 GAIN0 = L, GAIN1 = H 30.6 31.6 32.6 GAIN0 = H, GAIN1 = L 34.1 35.1 36.1 GAIN0 = H, GAIN1 = H 36.6 37.6 38.6 GV Closed-loop gain mV Ω W dB ΔGV Gain matching - -1 - 1 dB CT Crosstalk f = 1 kHz, Po = 1 W 50 70 - dB eN Total input noise A Curve, GV = 20 dB - 15 - f = 22 Hz to 22 kHz - 25 50 SVRR Supply voltage rejection ratio fr = 100 Hz, Vr = 0.5 Vpp, CSVR = 10 µF - 70 - dB Tr, Tf Rise and fall times - - 50 - ns fSW Switching frequency Internal oscillator 290 310 330 kHz 250 - 400 250 - 400 fSWR Output switching frequency range With internal oscillator (1) With external oscillator DocID16504 Rev 4 (2) µV kHz 9/27 Electrical specifications Symbol TDA7498L Parameter VinH Digital input high (H) VinL Digital input low (L) Condition - Pin STBY voltage high (H) VSTBY Pin STBY voltage low (L) Pin MUTE voltage high (H) VMUTE Pin MUTE voltage low (L) AMUTE Mute attenuation - VMUTE < 0.8 V Min Typ Max 2.3 - - - - 0.8 2.7 - - - - 0.5 2.5 - - - - 0.8 - 70 - Notes: (1) 6 fSW = 10 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 kΩ (see Figure 20: "Application circuit"). (2) 10/27 fSW = fSYNCLK / 2 with the external oscillator. DocID16504 Rev 4 Unit V V V dB TDA7498L 4 Characterization curves Characterization curves Figure 20: "Application circuit" shows the test circuit with which the characterization curves, shown in the next sections, were measured. Figure 3: "Test board" below shows the PCB layout. 4.1 PCB layout Figure 3: Test board Top view Top copper Bottom view Bottom copper DocID16504 Rev 4 11/27 Characterization curves 4.2 TDA7498L Characterization curves Unless otherwise stated the measurements were made under the following conditions: VCC = 32 V, f = 1 kHz, GV = 25.6 dB, ROSC = 39 kΩ, COSC = 100 nF, Tamb = 25 °C 4.2.1 For RL = 6 Ω Figure 4: Output power vs. supply voltage Figure 5: THD vs. output power (1 kHz) 10 5 2 1 0.5 0.2 0.1 % 0.05 0.02 0.01 0.005 0.002 0.001 100m 200m 500m 1 2 5 10 20 50 90 W Figure 6: THD vs. output power (100 Hz) Figure 7: THD vs. frequency (1 W) 10 1 5 0.5 2 1 0.2 0.5 0.2 % 0.1 0.1 % 0.05 0.05 0.02 0.02 0.01 0.005 0.01 0.002 0.001 100m 0.005 200m 500m 1 2 5 10 20 50 90 W 12/27 20 50 100 200 500 1k Hz DocID16504 Rev 4 2k 5k 10k 20k TDA7498L Characterization curves Figure 9: Frequency response Figure 8: THD vs. frequency (100 mW) 1 +3 +2.5 0.5 +2 +1.5 +1 0.2 % d B r 0.1 A 0.05 +0.5 +0 -0.5 -1 -1.5 -2 0.02 -2.5 0.01 20 50 100 200 500 1k 2k 5k 10k -3 20 20k 50 100 200 500 Hz Figure 10: FFT performance (0 dBFS) A +0 -10 -10 -20 -20 -30 -30 -40 -40 5k 10k 20k -50 -60 d B r -70 -80 A -90 -60 -70 -80 -90 -100 -100 -110 -110 -120 -120 -130 -1 30 -140 -140 -150 20 2k Figure 11: FFT performance (-60 dBFS) +0 -50 d B r 1k Hz 50 100 200 500 1k 2k 5k 10k 20k Hz -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz DocID16504 Rev 4 13/27 Characterization curves 4.2.2 TDA7498L For RL = 8 Ω Figure 12: Output power vs. supply voltage Figure 13: THD vs. output power (1 kHz) 10 5 2 1 0.5 0.2 % 0.1 0.05 0.02 0.01 0.005 0.002 0.001 100m 200m 500m 1 2 5 10 20 50 90 W Figure 14: THD vs. output power (100 Hz) Figure 15: THD vs. frequency (1 W) 10 1 5 0.5 2 1 0.2 0.5 0.2 % 0.1 0.1 % 0.05 0.05 0.02 0.02 0.01 0.005 0.01 0.002 0.001 100m 0.005 200m 500m 1 2 5 10 20 50 90 W 14/27 20 50 100 200 500 1k Hz DocID16504 Rev 4 2k 5k 10k 20k TDA7498L Characterization curves Figure 17: Frequency response Figure 16: THD vs. frequency (100 mW) +3 1 +2.5 0.5 +2 +1.5 +1 0.2 % d B r 0.1 A 0.05 +0.5 +0 -0.5 -1 -1.5 -2 0.02 -2.5 0.01 20 50 100 200 500 1k 2k 5k 10k -3 20 20k 50 100 200 10k 20k Figure 19: FFT performance (-60 dB) +0 -10 -20 -20 -30 -30 -40 -40 -50 -50 -70 d B r -80 A -60 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 20 5k +0 -10 A 2k Hz Figure 18: FFT performance (0 dB) d B r 1k 500 Hz 50 100 200 500 1k 2k 5k 10k 20k Hz DocID16504 Rev 4 -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz 15/27 Application information 5 Application information 5.1 Application circuit TDA7498L Figure 20: Application circuit 16/27 DocID16504 Rev 4 TDA7498L 5.2 Application information Mode selection The three operating modes of the TDA7498L are set by the two inputs, STBY (pin 20) and MUTE (pin 21). • • Standby mode: all circuits are turned off, very low current consumption. Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty cycle. Play mode: the amplifiers are active. • The protection functions of the TDA7498L are enabled by pulling down the voltages of the STBY and MUTE inputs shown in Figure 21: "Standby and mute circuits". The input current of the corresponding pins must be limited to 200 µA. Table 7: Mode settings Mode STBY MUTE L (1) X (don’t care) Mute H (1) L Play H Standby H Notes: (1) Drive levels defined in Table 6: "Electrical specifications " Figure 21: Standby and mute circuits DocID16504 Rev 4 17/27 Application information TDA7498L Figure 22: Turn on/off sequence for minimizing speaker “pop” 5.3 Gain setting The gain of the TDA7498L is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin31). Internally, the gain is set by changing the feedback resistors of the amplifier. Table 8: Gain settings 18/27 GAIN0 GAIN1 Nominal gain, Gv (dB) L L 25.6 L H 31.6 H L 35.6 H H 37.6 DocID16504 Rev 4 TDA7498L 5.4 Application information Input resistance and capacitance The input impedance is set by an internal resistor Ri = 60 kΩ (typical). An input capacitor (Ci) is required to couple the AC input signal. The equivalent circuit and frequency response of the input components are shown in Figure 23: "Input circuit and frequency response". For Ci = 470 nF the high-pass filter cutoff frequency is below 20 Hz: fC = 1 / (2 * π * Ri * Ci) Figure 23: Input circuit and frequency response DocID16504 Rev 4 19/27 Application information 5.5 TDA7498L Internal and external clocks The clock of the class-D amplifier can be generated internally or can be driven by an external source. If two or more class-D amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. This can be implemented by using one TDA7498L as master clock, while the other devices are in slave mode, that is, externally clocked. The clock interconnect is via pin SYNCLK of each device. As explained below, SYNCLK is an output in master mode and an input in slave mode. 5.5.1 Master mode (internal clock) Using the internal oscillator, the output switching frequency, fSW , is controlled by the resistor, ROSC, connected to pin ROSC: 6 fSW = 10 / [(ROSC * 16 + 182) * 4] kHz where ROSC is in kΩ. In master mode, pin SYNCLK is used as a clock output pin whose frequency is: fSYNCLK = 2 * fSW For master mode to operate correctly then resistor ROSC must be less than 60 kΩ as given below in Table 9: "How to set up SYNCLK". 5.5.2 Slave mode (external clock) In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin SYNCLK to be internally configured as an input as given in Table 9: "How to set up SYNCLK". The output switching frequency of the slave devices is: fSW = fSYNCLK / 2 Table 9: How to set up SYNCLK Mode ROSC SYNCLK Master ROSC < 60 kΩ Output Slave Floating (not connected) Input Figure 24: Master and slave connection 20/27 DocID16504 Rev 4 TDA7498L 5.6 Application information Output low-pass filter To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The cutoff frequency should be larger than 22 kHz and much lower than the output switching frequency. It is necessary to choose the L and C component values depending on the loudspeaker impedance. Some typical values, which give a cutoff frequency of 27 kHz, are shown in Figure 25: "Typical LC filter for an 8 Ω speaker" and Figure 26: "Typical LC filter for a 6 Ω speaker" below. Figure 25: Typical LC filter for an 8 Ω speaker Figure 26: Typical LC filter for a 6 Ω speaker DocID16504 Rev 4 21/27 Application information 5.7 TDA7498L Protection functions The TDA7498L is fully protected against overvoltages, undervoltages, overcurrents and thermal overloads as explained here. Overvoltage protection (OVP) If the supply voltage exceeds the value for VOVP given in Table 6: "Electrical specifications ", the overvoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage falls back to within the operating range, the device restarts. Undervoltage protection (UVP) If the supply voltage drops below the value for VUVP given in Table 6: "Electrical specifications ", the undervoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage falls back to within the operating range, the device restarts. Overcurrent protection (OCP) If the output current exceeds the value for IOCP given in Table 6: "Electrical specifications ", the overcurrent protection is activated which forces the outputs to the high-impedance state. Periodically, the device attempts to restart. If the overcurrent condition is still present then the OCP remains active. The restart time, TOC, is determined by the RC components connected to pin STBY. Thermal protection (OTP) If the junction temperature, Tj, reaches 145 °C (nominally), the device goes to mute mode and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction temperature reaches the value for Tj given in Table 6: "Electrical specifications ", the device shuts down and the output is forced to the high-impedance state. When the device cools sufficiently, the device restarts. 5.8 Diagnostic output The output pin DIAG is an open drain transistor. When any protection is activated it switches to the high-impedance state. The pin can be connected to a power supply (< 36 V) by a pull-up resistor whose value is limited by the maximum sinking current (200 µA) of the pin. Figure 27: Behavior of pin DIAG for various protection conditions VDD TDA7498L R1 DIAG Protection logic VDD Overcurrent protection 22/27 Restart Restart OV, UV, OT protection DocID16504 Rev 4 TDA7498L 6 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 6.1 PowerSSO-36 EPU package information The device comes in a 36-pin PowerSSO package with exposed pad up (EPU). Figure 28: "PowerSSO-36 EPU package outline" shows the package outline and Table 10: "PowerSSO-36 EPU package mechanical data" gives the dimensions. DocID16504 Rev 4 23/27 Package information TDA7498L Figure 28: PowerSSO-36 EPU package outline 7618147_F 24/27 DocID16504 Rev 4 TDA7498L Package information Table 10: PowerSSO-36 EPU package mechanical data Dimensions in mm Dimensions in inches Symbol Min. Typ. Max. Min. Typ. Max. A 2.15 - 2.45 0.085 - 0.096 A2 2.15 - 2.35 0.085 - 0.093 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees L 0.55 - 0.85 0.022 - 0.033 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 4.90 - 7.10 0.193 - 0.280 DocID16504 Rev 4 25/27 Revision history 7 TDA7498L Revision history Table 11: Document revision history 26/27 Date Revision Changes 04-Dec-2009 1 Initial release. 02-Jul-2010 2 Removed datasheet preliminary status, updated Section "Features" list and Table 1: "Device summary" Updated minimum supply voltage and temperature range in Table 5: "Recommended operating conditions" Updated typical power output for 8 Ω to 32 V in Table 6: "Electrical specifications " 12-Sep-2011 3 Updated OUTNA in Table 2: "Pin description list"; minor textual updates 09-Sep-2015 4 Updated VCC_MAX in Table 3: "Absolute maximum ratings" and dimension L in Table 10: "PowerSSO-36 EPU package mechanical data" DocID16504 Rev 4 TDA7498L IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID16504 Rev 4 27/27