TDA7498MV 100-watt mono BTL class-D audio amplifier Features 100-W output power at THD = 10% with RL = 6 Ω and VCC = 36 V 80-W output power at THD = 10% with RL = 8 Ω and VCC = 34 V Wide-range single-supply operation (14 - 39 V) High efficiency (η = 90%) Four selectable, fixed gain settings of nominally 25.6 dB, 31.6 dB, 35.1 dB and 37.6 dB Differential inputs minimize common-mode noise Standby and mute features Short-circuit protection Thermal overload protection Externally synchronizable PowerSSO-36 with exposed pad up Description The TDA7498MV is a mono BTL class-D audio amplifier with single power supply designed for home systems and active speaker applications. It comes in a 36-pin PowerSSO package with exposed pad up (EPU) to facilitate mounting a separate heatsink. Table 1. Device summary Order code Temperature range Package Packaging TDA7498MV -40 to 85 °C PowerSSO-36 (EPU) Tube TDA7498MVTR -40 to 85 °C PowerSSO-36 (EPU) Tape and reel January 2011 Doc ID 16505 Rev 3 1/27 www.st.com 27 Contents TDA7498MV Contents 1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 4 5 2.1 Pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2.1 For RL = 6 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.2.2 For RL = 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.5 Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5.1 Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5.2 Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.6 Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.7 Protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.8 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/27 Doc ID 16505 Rev 3 TDA7498MV List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output power (THD = 10%) vs supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 THD vs output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 THD vs frequency (1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 THD vs frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FFT performance (0 dBFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 FFT performance (-60 dBFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output power (THD = 10%) vs supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 THD vs output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 THD vs frequency (1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 THD vs frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FFT performance (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 FFT performance (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Standby and mute circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Turn-on/off sequence for minimizing speaker “pop” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Typical LC filter for a 8-Ω speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Typical LC filter for a 6-Ω speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Behavior of pin DIAG for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PowerSSO-36 EPU outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Doc ID 16505 Rev 3 3/27 List of tables TDA7498MV List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. 4/27 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 How to set up SYNCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PowerSSO-36 EPU dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Doc ID 16505 Rev 3 TDA7498MV 1 Device block diagram Device block diagram Figure 1 shows the block diagram of the TDA7498MV. Figure 1. Internal block diagram Doc ID 16505 Rev 3 5/27 Pin description TDA7498MV 2 Pin description 2.1 Pin-out Figure 2. Pin connection (top view, PCB view) SUB_GND 1 SVCC N.C. 2 34 VREF N.C. 3 33 SGND2 N.C. 4 32 VDDS2 N.C. 5 31 GAIN1 N.C. 6 30 GAIN0 N.C. 7 29 SVR N.C. 8 N.C. 9 36 VSS 35 28 DIAG 6/27 27 SGND OUTN 10 26 VDDS OUTN 25 SYNCLK PVCC 12 24 ROSC PVCC 13 23 INN PGND 14 22 INP EP, exposed pad Connect to ground 11 PGND 15 OUTP 16 21 MUTE 20 STBY OUTP 17 19 VDDPW PGND 18 Doc ID 16505 Rev 3 TDA7498MV 2.2 Pin description Pin list Table 2. Pin description list Number Name Type Description 1 SUB_GND PWR Connect to the frame 2,3 N.C. - No internal connection 4,5 N.C. - No internal connection 6,7 N.C. - No internal connection 8,9 N.C. - No internal connection 10,11 OUTN O Negative PWM output for audio channel 12,13 PVCC PWR Power supply for audio channel 14,15 PGND PWR Power stage ground 16,17 OUTP O Positive PWM output for audio channel 18 PGND PWR Power stage ground 19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power stage 20 STBY I Standby mode control 21 MUTE I Mute mode control 22 INP I Positive differential input 23 INN I Negative differential input 24 ROSC O Master oscillator frequency-setting pin 25 SYNCLK I/O Clock in/out for external oscillator 26 VDDS O 3.3-V (nominal) regulator output referred to ground for signal blocks 27 SGND PWR Signal ground 28 DIAG O Open-drain diagnostic output 29 SVR O Supply voltage rejection 30 GAIN0 I Gain setting input 1 31 GAIN1 I Gain setting input 2 32 VDDS2 O Connect to VDDS (pin 26) 33 SGND2 PWR Connect to SGND (pin 27) 34 VREF O Half VDDS (nominal) referred to ground 35 SVCC PWR Signal power supply decoupling 36 VSS O 3.3-V (nominal) regulator output referred to power supply - EP - Exposed pad for heatsink, to be connected to ground Doc ID 16505 Rev 3 7/27 Electrical specifications TDA7498MV 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter VCC_MAX DC supply voltage for pins PVCCA, PVCCB V -0.3 to 3.6 V Tj_MAX Operating junction temperature 0 to 150 °C Top_MAX Operating temperature -40 to 85 °C Tstg Storage temperature -40 to 150 °C Stresses beyond those listed under “Absolute maximum ratings” make cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended operating condition” are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, power supply with nominal value rated inside recommended operating conditions, may experience some rising beyond the maximum operating condition for short time when no or very low current is sinked (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum rating is not exceeded. Thermal data Thermal data Symbol Parameter Rth j-case Thermal resistance, junction to case Min - Typ 2 Max 3 Unit °C/W Recommended operating conditions Table 5. Symbol 8/27 44 Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN0, GAIN1 Table 4. 3.3 Unit VL_MAX Warning: 3.2 Value Recommended operating conditions Parameter Min Typ Max Unit VCC Supply voltage for pins PVCCA, PVCCB 14 - 39 V Tamb Ambient operating temperature -20 - 85 °C Doc ID 16505 Rev 3 TDA7498MV 3.4 Electrical specifications Electrical specifications Unless otherwise stated, the results in Table 6 below are given for the conditions: VCC = 36 V, RL (load) = 6 Ω, ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 25.6 dB and Tamb = 25 °C. Table 6. Electrical specifications Symbol Parameter Condition Min Typ Max Unit Iq Total quiescent current No LC filter, no load - 40 60 mA IqSTBY Quiescent current in standby - - 1 10 µA Play mode -100 - 100 VOS Output offset voltage Mute mode -60 - 60 IOCP Overcurrent protection threshold RL = 0 Ω 5.5 7 - A TjS Junction temperature at thermal shutdown - - 150 - °C Ri Input resistance Differential input 48 60 - kΩ VOVP Overvoltage protection threshold - 42 43 - V VUVP Undervoltage protection threshold - - - 8 V High side - 0.2 - RdsON Power transistor on resistance Low side - 0.2 - THD = 10% - 100 - Po Output power THD = 1% - 78 - Po Output power RL = 8 Ω, THD = 10%, VCC = 36V - 80 - W PD Dissipated power Po = 100 W, THD = 10% - 10 - W η Efficiency Po = 100 W - 90 - % THD Total harmonic distortion Po = 1 W - 0.1 - % GAIN0 = L, GAIN1 = L 24.6 25.6 26.6 GAIN0 = L, GAIN1 = H 30.6 31.6 32.6 GAIN0 = H, GAIN1 = L 34.1 35.1 36.1 GAIN0 = H, GAIN1 = H 36.6 37.6 38.6 - -1 - 1 A Curve, GV = 20 dB - 15 - f = 22 Hz to 22 kHz - 25 50 GV mV W Closed-loop gain ∆GV Gain matching eN Total input noise Ω dB dB µV SVRR Supply voltage rejection ratio fr = 100 Hz, Vr = 0.5 Vpp, CSVR = 10 µF 70 - dB Tr, Tf Rise and fall times - - 50 - ns fSW Switching frequency Internal oscillator 290 310 330 kHz Doc ID 16505 Rev 3 9/27 Electrical specifications Table 6. Symbol TDA7498MV Electrical specifications (continued) Parameter fSWR Output switching frequency range VinH Digital input high (H) VinL Digital input low (L) Condition AMUTE 400 With external oscillator (2) 250 - 400 2.3 - - - - 0.8 2.9 - - - - 0.5 2.5 - - - - 0.8 - 70 - - V Pin STBY voltage low (L) V Pin MUTE voltage low (L) Mute attenuation VMUTE < 0.8 V 2. fSW = fSYNCLK / 2 with the external oscillator. Doc ID 16505 Rev 3 Unit kHz V 1. fSW = 106 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 kΩ (see Figure 18.). 10/27 Max - Pin MUTE voltage high (H) VMUTE Typ 250 With internal oscillator Pin STBY voltage high (H) VSTBY Min (1) dB TDA7498MV 4 Characterization curves Characterization curves Figure 18 on page 18 shows the test circuit with which the characterization curves, shown in the next sections, were measured. Figure 3 shows the PCB layout. 4.1 Test board Figure 3. Test board Top view Top copper Bottom view Bottom copper Doc ID 16505 Rev 3 11/27 Characterization curves 4.2 TDA7498MV Characterization curves Unless otherwise stated the measurements were made under the following conditions: VCC = 36 V, f = 1 kHz, GV = 25.6 dB, ROSC = 39 kΩ, COSC = 100 nF, Tamb = 25 °C. 4.2.1 For RL = 6 Ω Figure 4. Output power (THD = 10%) vs supply voltage 120 110 Output power (W) 100 90 80 70 60 50 40 30 20 10 +10 +12 +14 +16 +18 +20 +22 +24 +26 +28 +30 +32 +34 +36 Supply voltage (V) Figure 5. THD vs output power 10 5 THD+N (%) 2 1 0.5 0.2 f = 1 kHz 0.1 0.05 f = 100 Hz 0.02 0.01 0.005 100m 200m 500m 1 2 5 Output power (W) 12/27 Doc ID 16505 Rev 3 10 20 50 100 200 TDA7498MV Figure 6. Characterization curves THD vs frequency (1 W) 2 1 THD+N (%) 0.5 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 20k 2k 5k 10k 20k 10k 20k Frequency (Hz) Figure 7. THD vs frequency (100 mW) 2 1 THD+N (%) 0.5 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1k Frequency (Hz) Figure 8. Frequency response +3 +2.5 Ampl (dB) +2 +1.5 +1 +0.5 +0 -0.5 -1 -1.5 -2 -2.5 -3 10 20 50 100 200 500 1k 2k 5k Frequency (Hz) Doc ID 16505 Rev 3 13/27 Characterization curves Figure 9. TDA7498MV FFT performance (0 dBFS) +0 -10 -20 FFT (dB) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Figure 10. FFT performance (-60 dBFS) +0 -10 -20 FFT (dB) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k Frequency (Hz) 14/27 Doc ID 16505 Rev 3 2k 5k 10k 20k TDA7498MV 4.2.2 Characterization curves For RL = 8 Ω Figure 11. Output power (THD = 10%) vs supply voltage 120 110 Output power (W) 100 90 80 70 60 50 40 30 20 10 +10 +12 +14 +16 +18 +20 +22 +24 +26 +28 +30 +32 +34 +36 Supply voltage (V) Figure 12. THD vs output power 10 5 THD+N (%) 2 1 0.5 0.2 f = 1 kHz 0.1 0.05 0.02 f = 100 Hz 0.01 0.005 100m 200m 500m 1 2 5 10 20 50 100 200 Output power (W) Doc ID 16505 Rev 3 15/27 Characterization curves TDA7498MV Figure 13. THD vs frequency (1 W) 2 1 THD+N (%) 0.5 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 20k 2k 5k 10k 20k Frequency (Hz) Figure 14. THD vs frequency (100 mW) 2 1 THD+N (%) 0.5 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1k Frequency (Hz) Figure 15. Frequency response +3 +2.5 Ampl (dB) +2 +1.5 +1 +0.5 +0 -0.5 -1 -1.5 -2 -2.5 -3 10 20 50 100 200 500 Frequency (Hz) 16/27 Doc ID 16505 Rev 3 1k 2k 5k 10k 20k TDA7498MV Characterization curves Figure 16. FFT performance (0 dB) ))7G% N N N N N )UHTXHQF\+] Figure 17. FFT performance (-60 dB) +0 -10 FFT (dB) -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Doc ID 16505 Rev 3 17/27 Applications information 5.1 Applications circuit Applications information 18/27 5 Figure 18. Applications circuit 1 SUB_GND OUTP 16 22 INP OUTP 17 C3 1nF 23 INN PGND 14 PGND 15 C4 1nF 27 SGND VDDS 26 VDDS C1 1µF C2 1µF J9 C5 100nF 1 R1 28 Doc ID 16505 Rev 3 J7 For single-ended DIAG 100k R7 22R DIAG C8 24 39K J5 30 3V3 C26 1µF 680nF PVCC 13 VDDS ROSC C40 10 TDA7498MV GAIN0 31 GAIN1 J3 OUT-1 * 220nF 220nF 330pF 8R L3 * 22µH C23 NC NC 2 NC 7 NC 6 OUTPUT Load = 6 ohm R16 11 3 OUT-2 C41 C24 IC3 R3 100nF C30 PVCC OUTN 18 PGND 25 SYNCLK * C25 100nF 12 OUTN Frequency shift 8R 220nF C27 C6 100nF R15 * C28 22R 19 VDDPW input R9 Q1 KTC3875(S) 180K 3 R13 FS 1 47k 2 R14 100k * R6 220nF 2 INPUT L4 22µH 2200µF 50V 2 + 1 VCC GND J2 J6 35 SVCC C10 100nF 36 VSS 3V3 32 VDDS2 33 SGND2 VDDS FS J4 S2 MUTE 1 2 3 120k R2 33k R8 6.8k D1 18V 3V3 Power supply 4 NC 9 Load L1,L2 C26 C24,C28 NC 8 6 ohm 22 µH 680 nF 220 nF 34 8 ohm 22 µH 470 nF 220 nF 21 MUTE + + LC filter components C17 C15 2.2µF 20 STBY 16V SVR C7 2.2µF 16V 29 10µF 10V C16 10µF 10V TDA7498MV VCC CLASS-D AMPLIFIER TDA7498MV IN IC2 1 L4931CZ33 3 GND 2 C29 C9 2.2µF 100nF OUT 5 VREF R4 S1 STBY 1 2 3 NC NC TDA7498MV 5.2 Applications information Mode selection The three operating modes of the TDA7498MV are set by the two inputs, STBY (pin 20) and MUTE (pin 21). z Standby mode: all circuits are turned off, very low current consumption. z Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty cycle. z Play mode: the amplifiers are active. The protection functions of the TDA7498MV are realized by pulling down the voltages of the STBY and MUTE inputs shown in Figure 19. The input current of the corresponding pins must be limited to 200 µA. Table 7. Mode settings Mode STBY MUTE L (1) Standby Mute H Play H X (don’t care) (1) L H 1. Drive levels defined in Table 6: Electrical specifications on page 9 Figure 19. Standby and mute circuits Standby 3.3 V 0V STBY R2 30 kΩ C7 2.2 µF R4 30 kΩ C15 2.2 µF Mute MUTE 3.3 V 0V TDA7498MV Figure 20. Turn-on/off sequence for minimizing speaker “pop” VCC 0 t STBY 0 t MUTE 0 Input t 0 t Output 0 t Standby Mute Play Mute Standby Iq 0 t Doc ID 16505 Rev 3 19/27 Applications information 5.3 TDA7498MV Gain setting The gain of the TDA7498MV is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin31). Internally, the gain is set by changing the feedback resistors of the amplifier. Table 8. Gain settings GAIN0 5.4 GAIN1 Nominal gain, Gv (dB) L L 25.6 L H 31.6 H L 35.6 H H 37.6 Input resistance and capacitance The input impedance is set by an internal resistor Ri = 60 kΩ (typical). An input capacitor (Ci) is required to couple the AC input signal. The equivalent circuit and frequency response of the input components are shown in Figure 21. For Ci = 470 nF the high-pass filter cut-off frequency is below 20 Hz: fC = 1 / (2 * π * Ri * Ci) Figure 21. Input circuit and frequency response Rf Input signal 20/27 Ci Input pin Ri Doc ID 16505 Rev 3 TDA7498MV 5.5 Applications information Internal and external clocks The clock of the class-D amplifier can be generated internally or can be driven by an external source. If two or more class-D amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. This can be implemented by using one TDA7498MV as master clock, while the other devices are in slave mode, that is, externally clocked. The clock interconnect is via pin SYNCLK of each device. As explained below, SYNCLK is an output in master mode and an input in slave mode. 5.5.1 Master mode (internal clock) Using the internal oscillator, the output switching frequency, fSW, is controlled by the resistor, ROSC, connected to pin ROSC: fSW = 106 / ((ROSC * 16 + 182) * 4) kHz where ROSC is in kΩ. In master mode, pin SYNCLK is used as a clock output pin whose frequency is: fSYNCLK = 2 * fSW For master mode to operate correctly then resistor ROSC must be less than 60 kΩ as given below in Table 9. 5.5.2 Slave mode (external clock) In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin SYNCLK to be internally configured as an input as given in Table 9. The output switching frequency of the slave devices is: fSW = fSYNCLK / 2 Table 9. How to set up SYNCLK Mode ROSC SYNCLK Master ROSC < 60 kΩ Output Slave Floating (not connected) Input Figure 22. Master and slave connection Master Slave TDA7498MV ROSC SYNCLK Output Cosc 100 nF TDA7498MV SYNCLK ROSC Input Rosc 39 kΩ Doc ID 16505 Rev 3 21/27 Applications information 5.6 TDA7498MV Output low-pass filter To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The cut-off frequency should be larger than 22 kHz and much lower than the output switching frequency. It is necessary to choose the L and C component values depending on the loudspeaker impedance. Some typical values, which give a cut-off frequency of 27 kHz, are shown in Figure 23 and Figure 24 below. Figure 23. Typical LC filter for a 8-Ω speaker 07-?0 U( OHM N& P& N& N& OHM OHM N & N& U( 07-?. OHM Figure 24. Typical LC filter for a 6-Ω speaker 07-?0 U( OH M N & P& N & N& OH M OH M N& N & U( 07-?. 22/27 Doc ID 16505 Rev 3 OH M TDA7498MV 5.7 Applications information Protection function The TDA7498MV is fully protected against overvoltages, undervoltages, overcurrents and thermal overloads as explained here. Overvoltage protection (OVP) If the supply voltage exceeds the value for VOVP given in Table 6: Electrical specifications on page 9 the overvoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage falls back to within the operating range the device restarts. Undervoltage protection (UVP) If the supply voltage drops below the value for VUVP given in Table 6: Electrical specifications on page 9 the undervoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage recovers to within the operating range the device restarts. Overcurrent protection (OCP) If the output current exceeds the value for IOCP given in Table 6: Electrical specifications on page 9 the overcurrent protection is activated which forces the outputs to the high-impedance state. Periodically, the device attempts to restart. If the overcurrent condition is still present then the OCP remains active. The restart time, TOC, is determined by the R-C components connected to pin STBY. Thermal protection (OTP) If the junction temperature, Tj, reaches 145 °C (nominally), the device goes to mute mode and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction temperature reaches the value for Tj given in Table 6: Electrical specifications on page 9 the device shuts down and the output is forced to the high-impedance state. When the device cools sufficiently the device restarts. 5.8 Diagnostic output The output pin DIAG is an open drain transistor. When any protection is activated it switches to the high-impedance state. The pin can be connected to a power supply (< 39 V) by a pullup resistor whose value is limited by the maximum sinking current (200 µA) of the pin. Figure 25. Behavior of pin DIAG for various protection conditions VDD TDA7498MV R1 DIAG Protection logic VDD Restart Restart Overcurrent protection OV, UV, OT protection Doc ID 16505 Rev 3 23/27 Package mechanical data 6 TDA7498MV Package mechanical data The TDA7498MV comes in a 36-pin PowerSSO package with exposed pad up (EPU). Figure 26 shows the package outline and Table 10 gives the dimensions. Table 10. PowerSSO-36 EPU dimensions Dimensions in mm Dimensions in inches Symbol Min Typ Max Min Typ Max A 2.15 - 2.45 0.085 - 0.096 A2 2.15 - 2.35 0.085 - 0.093 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees - - 8 degrees L 0.60 - 1.00 0.024 - 0.039 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 4.90 - 7.10 0.193 - 0.280 In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 24/27 Doc ID 16505 Rev 3 TDA7498MV Figure 26. PowerSSO-36 EPU outline drawing h x 45° Doc ID 16505 Rev 3 Package mechanical data 25/27 Revision history 7 TDA7498MV Revision history Table 11. 26/27 Document revision history Date Revision Changes 30-Nov-2009 1 Initial release. 28-Jul-2010 2 Removed datasheet preliminary status, updated features list and updated device summary table on page 1 Added operating temperature range to Table 3 on page 8 Updated minimum supply voltage and temperature range in Table 5: Recommended operating conditions on page 8 Updated voltage for logical 1 on pin STBY in Table 6 on page 9 27-Jan-2011 3 Updated applications circuit in Figure 18 on page 18. Doc ID 16505 Rev 3 TDA7498MV Please Read Carefully: Information in this document is provided solely in connection with ST products. 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