TDA7498L 80 watt + 80 watt dual BTL class-D audio amplifier Features ■ 80 W + 80 W output power at THD = 10% with RL = 6 Ω and VCC = 32 V ■ 70 W + 70 W output power at THD = 10% with RL = 8 Ω and VCC = 34 V ■ Wide-range single-supply operation (14 - 36 V) ■ High efficiency (η = 90%) ■ Four selectable, fixed gain settings of nominally 25.6 dB, 31.6 dB, 35.1 dB and 37.6 dB ■ Differential inputs minimize common-mode noise ■ Standby and mute features ■ Short-circuit protection ■ Thermal overload protection ■ Externally synchronizable PowerSSO-36 with exposed pad up Description The TDA7498L is a dual BTL class-D audio amplifier with single power supply designed for home systems and active speaker applications. It comes in a 36-pin PowerSSO package with exposed pad up (EPU) to facilitate mounting a separate heatsink. Table 1. Device summary Order code Temperature range Package Packaging TDA7498L -40 to 85 °C PowerSSO-36 (EPU) Tube TDA7498LTR -40 to 85 °C PowerSSO-36 (EPU) Tape and reel September 2011 Doc ID 16504 Rev 3 1/27 www.st.com 27 Contents TDA7498L Contents 1 2 3 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Characterizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1 For RL = 6 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.2.2 For RL = 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5 Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.1 Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.2 Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6 Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 Protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2/27 Doc ID 16504 Rev 3 TDA7498L List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Internal block diagram (showing one channel only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connections (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test circuit for characterizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output power (THD = 10%) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 THD vs. frequency (1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 THD vs. frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 FFT performance (0 dBFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FFT performance (-60 dBFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output power (THD = 10%) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 THD vs. frequency (1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 THD vs. frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 FFT performance (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 FFT performance (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Applications circuit for 6- or 8-Ω speakers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Standby and mute circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Turn on/off sequence for minimizing speaker “pop” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Typical LC filter for a 8-Ω speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Typical LC filter for a 6-Ω speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Behavior of pin DIAG for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PowerSSO36 EPU outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Doc ID 16504 Rev 3 3/27 List of tables TDA7498L List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. 4/27 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 How to set up SYNCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PowerSSO-36 EPU dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Doc ID 16504 Rev 3 TDA7498L 1 Device block diagram Device block diagram Figure 1 shows the block diagram of one of the two identical channels of the TDA7498L. Figure 1. Internal block diagram (showing one channel only) Doc ID 16504 Rev 3 5/27 Pin description TDA7498L 2 Pin description 2.1 Pinout Figure 2. Pin connections (top view, PCB view) SUB_GND 1 SVCC OUTPB 2 34 VREF OUTPB 3 33 INNB PGNDB 4 32 INPB PGNDB 5 31 GAIN1 PVCCB 6 30 GAIN0 PVCCB 7 29 SVR OUTNB 8 28 DIAG OUTNB 9 27 SGND OUTNA 10 26 VDDS OUTNA 11 25 SYNCLK PVCCA 12 24 ROSC PVCCA 13 23 INNA PGNDA 14 36 VSS 35 22 INPA EP, exposed pad Connect to ground 21 MUTE OUTPA 16 OUTPA 17 20 STBY 19 VDDPW 6/27 PGNDA 15 Doc ID 16504 Rev 3 PGND 18 TDA7498L 2.2 Pin description Pin list Table 2. Pin description list Number Name Type Description 1 SUB_GND PWR Connect to the frame 2,3 OUTPB O Positive PWM for right channel 4,5 PGNDB PWR Power stage ground for right channel 6,7 PVCCB PWR Power supply for right channel 8,9 OUTNB O Negative PWM output for right channel 10,11 OUTNA O Negative PWM output for left channel 12,13 PVCCA PWR Power supply for left channel 14,15 PGNDA PWR Power stage ground for left channel 16,17 OUTPA O Positive PWM output for left channel 18 PGND PWR Power stage ground 19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power stage 20 STBY I Standby mode control 21 MUTE I Mute mode control 22 INPA I Positive differential input of left channel 23 INNA I Negative differential input of left channel 24 ROSC O Master oscillator frequency-setting pin 25 SYNCLK I/O Clock in/out for external oscillator 26 VDDS O 3.3-V (nominal) regulator output referred to ground for signal blocks 27 SGND PWR Signal ground 28 DIAG O Open-drain diagnostic output 29 SVR O Supply voltage rejection 30 GAIN0 I Gain setting input 1 31 GAIN1 I Gain setting input 2 32 INPB I Positive differential input of right channel 33 INNB I Negative differential input of right channel 34 VREF O Half VDDS (nominal) referred to ground 35 SVCC PWR Signal power supply decoupling 36 VSS O 3.3-V (nominal) regulator output referred to power supply - EP - Exposed pad for heatsink, to be connected to ground Doc ID 16504 Rev 3 7/27 Electrical specifications TDA7498L 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter VCC_MAX DC supply voltage for pins PVCCA, PVCCB V -0.3 to 3.6 V Tj_MAX Operating junction temperature 0 to 150 °C Tstg Storage temperature -40 to 150 °C Stresses beyond those listed under “Absolute maximum ratings” make cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended operating condition” are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, the power supply with the nominal value rated in the recommended operating conditions, may rise beyond the maximum operating condition for a short time when no or very low current is sunk (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum rating is not exceeded. Thermal data Thermal data Symbol Parameter Rth j-case Thermal resistance, junction to case Min - Typ 2 Max 3 Unit °C/W Recommended operating conditions Table 5. Symbol 8/27 44 Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN0, GAIN1 Table 4. 3.3 Unit VL_MAX Warning: 3.2 Value Recommended operating conditions Parameter Min Typ Max Unit VCC Supply voltage for pins PVCCA, PVCCB 14 - 36 V Tamb Ambient operating temperature -20 - 85 °C Doc ID 16504 Rev 3 TDA7498L 3.4 Electrical specifications Electrical specifications Unless otherwise stated, the results in Table 6 below are given for the conditions: VCC = 32 V, RL (load) = 6 Ω, ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 25.6 dB and Tamb = 25 °C. Table 6. Electrical specifications Symbol Parameter Condition Min Typ Max Unit Iq Total quiescent current No LC filter, no load - 40 60 mA IqSTBY Quiescent current in standby - - 1 10 µA Play mode -100 - 100 VOS Output offset voltage Mute mode -60 - 60 IOCP Overcurrent protection threshold RL = 0 Ω 5.0 6.0 - A TjS Junction temperature at thermal shutdown - - 150 - °C Ri Input resistance Differential input 48 60 - kΩ VOVP Overvoltage protection threshold - 42 43 - V VUVP Undervoltage protection threshold - - - 8 V High side - 0.2 - RdsON Power transistor on resistance Low side - 0.2 - THD = 10% - 80 - Po Output power THD = 1% - 65 - Po Output power RL = 8 Ω, THD = 10%, VCC = 32V - 65 - W PD Dissipated power Po = 80 W + 80 W, THD = 10% - 16 - W η Efficiency Po = 80 W + 80W - 90 - % THD Total harmonic distortion Po = 1 W - 0.1 - % GAIN0 = L, GAIN1 = L 24.6 25.6 26.6 GAIN0 = L, GAIN1 = H 30.6 31.6 32.6 GAIN0 = H, GAIN1 = L 34.1 35.1 36.1 GAIN0 = H, GAIN1 = H 36.6 37.6 38.6 GV mV Ω W Closed-loop gain dB ΔGV Gain matching - -1 - 1 dB CT Crosstalk f = 1 kHz, Po = 1 W 50 70 - dB 15 - Total input noise A Curve, GV = 20 dB - eN f = 22 Hz to 22 kHz - 25 50 µV SVRR Supply voltage rejection ratio fr = 100 Hz, Vr = 0.5 Vpp, CSVR = 10 µF 70 - dB Tr, Tf Rise and fall times - 50 - ns Doc ID 16504 Rev 3 - 9/27 Electrical specifications Table 6. TDA7498L Electrical specifications (continued) Symbol Parameter fSW Switching frequency fSWR Output switching frequency Range VinH Digital input high (H) VinL Digital input low (L) Condition Internal oscillator With external oscillator AMUTE (2) Typ 310 330 - 400 250 - 400 2.3 - - - - 0.8 2.7 - - Pin STBY voltage low (L) - - 0.5 2.5 - - - - 0.8 Mute attenuation VMUTE < 0.8 V - 70 - V V 1. fSW = 10 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 kΩ (see Figure 20.). 2. fSW = fSYNCLK / 2 with the external oscillator. Doc ID 16504 Rev 3 kHz V Pin MUTE voltage low (L) Unit kHz - 6 10/27 Max - Pin MUTE voltage high (H) VMUTE 290 With internal oscillator (1) 250 Pin STBY voltage high (H) VSTBY Min dB TDA7498L 4 Characterization curves Characterization curves Figure 20 on page 18 shows the test circuit with which the characterization curves, shown in the next sections, were measured. Figure 3 below shows the PCB layout. 4.1 PCB layout Figure 3. Test board Top view Top copper Bottom view Bottom copper Doc ID 16504 Rev 3 11/27 Characterization curves 4.2 TDA7498L Characterization curves Unless otherwise stated the measurements were made under the following conditions: VCC = 32 V, f = 1 kHz, GV = 25.6 dB, ROSC = 39 kΩ, COSC = 100 nF, Tamb = 25 °C 4.2.1 For RL = 6 Ω Figure 4. Output power vs. supply voltage Figure 5. THD vs. output power (1 kHz) 10 5 2 1 0.5 0.2 % 0.1 0.05 0.02 0.01 0.005 0.002 0.001 100m 200m 500m 1 2 5 W 12/27 Doc ID 16504 Rev 3 10 20 50 90 TDA7498L Characterization curves Figure 6. THD vs. output power (100 Hz) 10 5 2 1 0.5 0.2 % 0.1 0.05 0.02 0.01 0.005 0.002 0.001 100m 200m 500m 1 2 5 10 20 50 90 W Figure 7. THD vs. frequency (1 W) 1 0.5 0.2 0.1 % 0.05 0.02 0.01 0.005 20 50 100 200 500 1k 2k 5k 10k 20k 1k 2k 5k 10k 20k Hz Figure 8. THD vs. frequency (100 mW) 1 0.5 0.2 % 0.1 0.05 0.02 0.01 20 50 100 200 500 Hz Doc ID 16504 Rev 3 13/27 Characterization curves Figure 9. TDA7498L Frequency response +3 +2.5 +2 +1.5 +1 d B r A +0.5 +0 -0.5 -1 -1.5 -2 -2.5 -3 20 50 100 200 500 1k 2k 5k 10k 20k 1k 2k 5k 10k 20k Hz Figure 10. FFT performance (0 dBFS) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 Hz Figure 11. FFT performance (-60 dBFS) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k Hz 14/27 Doc ID 16504 Rev 3 2k 5k 10k 20k TDA7498L 4.2.2 Characterization curves For RL = 8 Ω Figure 12. Output power vs. supply voltage Figure 13. THD vs. output power (1 kHz) 10 5 2 1 0.5 0.2 % 0.1 0.05 0.02 0.01 0.005 0.002 0.001 100m 200m 500m 1 2 5 10 20 50 90 W Doc ID 16504 Rev 3 15/27 Characterization curves TDA7498L Figure 14. THD vs. output power (100 Hz) 10 5 2 1 0.5 0.2 % 0.1 0.05 0.02 0.01 0.005 0.002 0.001 100m 200m 500m 1 2 5 10 1k 2k 1k 2k 20 50 90 5k 10k 20k 5k 10k 20k W Figure 15. THD vs. frequency (1 W) 1 0.5 0.2 0.1 % 0.05 0.02 0.01 0.005 20 50 100 200 500 Hz Figure 16. THD vs. frequency (100 mW) 1 0.5 0.2 % 0.1 0.05 0.02 0.01 20 50 100 200 500 Hz 16/27 Doc ID 16504 Rev 3 TDA7498L Characterization curves Figure 17. Frequency response +3 +2.5 +2 +1.5 +1 d B r A +0.5 +0 -0.5 -1 -1.5 -2 -2.5 -3 20 50 100 200 500 1k 2k 5k 10k 20k 1k 2k 5k 10k 20k 1k 2k 5k 10k 20k Hz Figure 18. FFT performance (0 dBFS) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 Hz Figure 19. FFT performance (-60 dBFS) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 Hz Doc ID 16504 Rev 3 17/27 Applications information TDA7498L 5 Applications information 5.1 Applications circuit Figure 20. Applications circuit 1 C1 1uF 1nF SGND 1nF SGND J1 100nF SGND L- 4 L+ 1 R- 2 23 INNA PGNDA 14 R6 PGNDA 15 22R 27 R1 DIAG J7 Single-Ended 22R C6 3 FREQUENCY SHIFT Q1 C8 SYNC 1 R3 2 39K 100nF R13 68k ROSC SGND J5 30 GAIN0 VDDS C11 1uF SGND S2 MUTE 1uF S1 STBY SGND 120k + 33k + R2 2 SGND IC2 R8 IN L4931CZ33 3 C29 1 2.2uF 2 GND C9 SGND VCC 6.8k D1 100nF 18V SGND SGND SGND SGND SGND 3V3 POWER SUPPLY 5.2 1nF INPB INNB C14 R4 2 SGND OUT 32 33 C13 C12 1 3 220nF C27 SGND 1nF 330pF 21 MUTE C15 2.2uF 20 STBY 16V C7 2.2uF 16V 2200uF C23+ 50V OUTPB L1 3 OUTPB 2 PVCCB 7 PVCCB 6 R5 L- 220nF R- R16 R+ 8R 22uH * 1 C41 L3 * J3 Load=6 ohm L+ * PVCCA 13 1 VCC 2 GND 2 3 4 J2 22uH * C18 22R 220nF R17 8R C42 100nF 100nF 36 VSS 3V3 SGND 680nF C24 SVCC C10 Input 1 3 1uF C19 35 SGND FS 100nF J6 For J4 TDA7498L 31 GAIN1 J8 Single-Ended 8R C40 OUTPUT PVCCA 12 IC1 25 SYNCLK 24 FS R9 120K R14 47k SGND SGND FS C26 OUTNA 11 18 PGND * C30 OUTNA 10 SGND 220nF C25 19 VDDPW 100nF 3V3 DIAG Input R+ R15 * C28 220nF 100k R7 For 28 * 22uH SGND VDDS26 VDDS C5 3 OUTPA 16 OUTPA 17 C4 1uF L4 INPA C3 C2 INPUT SUB_GND 22 PGNDB 5 PGNDB 4 OUTNB 9 OUTNB 8 VREF 34 SVR 29 C31 C20 1uF 680nF * * C17 220nF R18 SGND 22uH 10uF 10V C16 SGND TDA7498L CLASS-D AMPLIFIER 8R L2 * C43 C22 220nF C21 330pF 220nF 10uF 10V LC FILTER COMPONENT Load L1,L2,L3,L4 C20,C26 C18,C22,C24,C28 6 ohm 22 uH 680 nF 220 nF 8 ohm 22 uH 470 nF 220 nF Mode selection The three operating modes of the TDA7498L are set by the two inputs, STBY (pin 20) and MUTE (pin 21). 18/27 ● Standby mode: all circuits are turned off, very low current consumption. ● Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty cycle. ● Play mode: the amplifiers are active. Doc ID 16504 Rev 3 TDA7498L Applications information The protection functions of the TDA7498L are enabled by pulling down the voltages of the STBY and MUTE inputs shown in Figure 21. The input current of the corresponding pins must be limited to 200 µA. Table 7. Mode settings Mode STBY MUTE (1) X (don’t care) Standby L Mute H (1) L Play H H 1. Drive levels defined in Table 6: Electrical specifications on page 9 Figure 21. Standby and mute circuits Standby 3.3 V 0V STBY R2 30 kΩ C7 2.2 µF R4 30 kΩ C15 2.2 µF Mute MUTE 3.3 V 0V TDA7498L Figure 22. Turn on/off sequence for minimizing speaker “pop” Doc ID 16504 Rev 3 19/27 Applications information 5.3 TDA7498L Gain setting The gain of the TDA7498L is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin 31). Internally, the gain is set by changing the feedback resistors of the amplifier. Table 8. Gain settings GAIN0 5.4 GAIN1 Nominal gain, Gv (dB) L L 25.6 L H 31.6 H L 35.6 H H 37.6 Input resistance and capacitance The input impedance is set by an internal resistor Ri = 60 kΩ (typical). An input capacitor (Ci) is required to couple the AC input signal. The equivalent circuit and frequency response of the input components are shown in Figure 23. For Ci = 470 nF the high-pass filter cutoff frequency is below 20 Hz: fC = 1 / (2 * π * Ri * Ci) Figure 23. Input circuit and frequency response Rf Input signal 20/27 Ci Input pin Ri Doc ID 16504 Rev 3 TDA7498L 5.5 Applications information Internal and external clocks The clock of the class-D amplifier can be generated internally or can be driven by an external source. If two or more class-D amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. This can be implemented by using one TDA7498L as master clock, while the other devices are in slave mode, that is, externally clocked. The clock interconnect is via pin SYNCLK of each device. As explained below, SYNCLK is an output in master mode and an input in slave mode. 5.5.1 Master mode (internal clock) Using the internal oscillator, the output switching frequency, fSW, is controlled by the resistor, ROSC, connected to pin ROSC: fSW = 106 / ((ROSC * 16 + 182) * 4) kHz where ROSC is in kΩ. In master mode, pin SYNCLK is used as a clock output pin whose frequency is: fSYNCLK = 2 * fSW For master mode to operate correctly then resistor ROSC must be less than 60 kΩ as given below in Table 9. 5.5.2 Slave mode (external clock) In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin SYNCLK to be internally configured as an input as given in Table 9. The output switching frequency of the slave devices is: fSW = fSYNCLK / 2 Table 9. How to set up SYNCLK Mode ROSC SYNCLK Master ROSC < 60 kΩ Output Slave Floating (not connected) Input Figure 24. Master and slave connection Master Slave TDA7498L ROSC TDA7498L SYNCLK Output Cosc 100 nF SYNCLK ROSC Input Rosc 39 kΩ Doc ID 16504 Rev 3 21/27 Applications information 5.6 TDA7498L Output low-pass filter To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The cutoff frequency should be larger than 22 kHz and much lower than the output switching frequency. It is necessary to choose the L and C component values depending on the loudspeaker impedance. Some typical values, which give a cutoff frequency of 27 kHz, are shown in Figure 25 and Figure 26 below. Figure 25. Typical LC filter for a 8-Ω speaker 07-?0 U( OHM N& P& N& N& OHM OHM N & N& U( 07-?. OHM Figure 26. Typical LC filter for a 6-Ω speaker 07-?0 U( OH M N & P& N & N& OH M OH M N& N & U( 07-?. 22/27 Doc ID 16504 Rev 3 OH M TDA7498L 5.7 Applications information Protection functions The TDA7498L is fully protected against overvoltages, undervoltages, overcurrents and thermal overloads as explained here. Overvoltage protection (OVP) If the supply voltage exceeds the value for VOVP given in Table 6: Electrical specifications on page 9 the overvoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage falls back to within the operating range, the device restarts. Undervoltage protection (UVP) If the supply voltage drops below the value for VUVP given in Table 6: Electrical specifications on page 9 the undervoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage recovers to within the operating range, the device restarts. Overcurrent protection (OCP) If the output current exceeds the value for IOCP given in Table 6: Electrical specifications on page 9 the overcurrent protection is activated which forces the outputs to the high-impedance state. Periodically, the device attempts to restart. If the overcurrent condition is still present then the OCP remains active. The restart time, TOC, is determined by the R-C components connected to pin STBY. Thermal protection (OTP) If the junction temperature, Tj, reaches 145 °C (nominally), the device goes to mute mode and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction temperature reaches the value for Tj given in Table 6: Electrical specifications on page 9 the device shuts down and the output is forced to the high-impedance state. When the device cools sufficiently, the device restarts. 5.8 Diagnostic output The output pin DIAG is an open-drain transistor. When any protection is activated it switches to the high-impedance state. The pin can be connected to a power supply (< 36 V) by a pullup resistor whose value is limited by the maximum sinking current (200 µA) of the pin. Figure 27. Behavior of pin DIAG for various protection conditions VDD TDA7498L R1 DIAG Protection logic VDD Restart Restart Overcurrent protection OV, UV, OT protection Doc ID 16504 Rev 3 23/27 Package mechanical data 6 TDA7498L Package mechanical data The TDA7498L comes in a 36-pin PowerSSO package with exposed pad up. Figure 28 shows the package outline and Table 10 gives the dimensions. Table 10. PowerSSO-36 EPU dimensions Dimensions in mm Dimensions in inches Symbol Min Typ Max Min Typ Max A 2.15 - 2.45 0.085 - 0.096 A2 2.15 - 2.35 0.085 - 0.093 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees - - 8 degrees L 0.60 - 1.00 0.024 - 0.039 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 4.90 - 7.10 0.193 - 0.280 In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 24/27 Doc ID 16504 Rev 3 TDA7498L Figure 28. PowerSSO-36 EPU outline drawing h x 45° Doc ID 16504 Rev 3 Package mechanical data 25/27 Revision history 7 TDA7498L Revision history Table 11. 26/27 Document revision history Date Revision Changes 04-Dec-2009 1 Initial release. 02-Jul-2010 2 Removed datasheet preliminary status, updated features list and updated Device summary table on page 1 Updated minimum supply voltage and temperature range in Table 5: Recommended operating conditions on page 8 Updated typical power output for 8 Ω at 32 V in Table 6: Electrical specifications on page 9 12-Sep-2011 3 Updated OUTNA in Table 2: Pin description list; minor textual updates Doc ID 16504 Rev 3 TDA7498L Please Read Carefully: Information in this document is provided solely in connection with ST products. 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