STM32F031x4 STM32F031x6
ARM®-based 32-bit MCU with up to 32 Kbyte Flash, timers,
ADC and communication interfaces, 2.0 - 3.6 V
Datasheet - production data
Features
Core: ARM® 32-bit Cortex®-M0 CPU,
frequency up to 48 MHz
LQFP32 7x7 mm UFQFPN32 5x5 mm WLCSP25
LQFP48 7x7 mm UFQFPN28 4x4 mm (2.1x2.1 mm)
Memories
– 16 to 32 Kbytes of Flash memory
– 4 Kbytes of SRAM with HW parity
CRC calculation unit
Reset and power management
– Digital and I/Os supply: 2.0 to 3.6 V
– Analog supply: VDDA = from VDD to 3.6 V
– Power-on/Power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low power modes: Sleep, Stop and
Standby
– VBAT supply for RTC and backup registers
Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x6 PLL option
– Internal 40 kHz RC oscillator
Up to 39 fast I/Os
– All mappable on external interrupt vectors
– Up to 25 I/Os with 5 V tolerant capability
TSSOP20
– 1 x 16-bit timer, with IC/OC and OCN,
deadtime generation, emergency stop and
modulator gate for IR control
– 1 x 16-bit timer with 1 IC/OC
– Independent and system watchdog timers
– SysTick timer: 24-bit downcounter
Calendar RTC with alarm and periodic wakeup
from Stop/Standby
Communication interfaces
– 1 x I2C interface; supporting Fast Mode
Plus (1 Mbit/s) with 20 mA current sink,
SMBus/PMBus, and wakeup from Stop
mode
– 1 x USART supporting master synchronous
SPI and modem control; one with ISO7816
interface, LIN, IrDA capability auto baud
rate detection and wakeup feature
– 1 x SPI (18 Mbit/s) with 4 to 16
programmable bit frames, with I2S interface
multiplexed
5-channel DMA controller
Serial wire debug (SWD)
1 × 12-bit, 1.0 µs ADC (up to 10 channels)
– Conversion range: 0 to 3.6V
– Separate analog supply from 2.4 up to
3.6 V
Extended temperature range: -40 to +105°C
®
All packages ECOPACK 2
Up to 9 timers
– 1 x 16-bit 7-channel advanced-control timer
for 6 channels PWM output, with deadtime
generation and emergency stop
– 1 x 32-bit and 1 x 16-bit timer, with up to 4
IC/OC, usable for IR control decoding
– 1 x 16-bit timer, with 2 IC/OC, 1 OCN,
deadtime generation and emergency stop
August 2015
This is information on a product in full production.
96-bit unique ID
Table 1. Device summary
Reference
STM32F031x4
Part number
STM32F031C4, STM32F031F4,
STM32F031G4, STM32F031K4
STM32F031C6, STM32F031E6,
STM32F031x6 STM32F031F6, STM32F031G6,
STM32F031K6
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Contents
STM32F031x4 STM32F031x6
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
ARM®-Cortex®-M0 core with embedded Flash and SRAM . . . . . . . . . . . 12
3.2
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13
3.5
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.2
Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.10
3.11
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3.5.1
3.9.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
3.9.2
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 16
Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.3
VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.1
Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.2
General-purpose timers (TIM2..3, TIM14, 16, 17) . . . . . . . . . . . . . . . . . 19
3.11.3
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.4
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.5
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 20
3.13
Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14
Universal synchronous/asynchronous receiver transmitters (USART) . . 22
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3.15
Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 23
3.16
Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43
6.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 43
6.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3.6
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.7
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.8
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.9
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.10
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.12
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.16
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.17
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.18
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.19
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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6.3.20
7
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.1
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.2
LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.3
UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.4
UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.5
WLCSP25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.6
WLCSP25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.7
TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.8
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.8.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.8.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 107
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F031x4/x6 family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . 10
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STM32F031x4/x6 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STM32F031x4/x6 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM32F031x4/x6 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 32
Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 33
STM32F031x4/x6 peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . 35
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 43
Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Typical and maximum current consumption from the VDD supply at VDD = 3.6 V . . . . . . . 46
Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . 47
Typical and maximum current consumption in Stop and Standby modes . . . . . . . . . . . . 48
Typical and maximum current consumption from the VBAT supply. . . . . . . . . . . . . . . . . . . 49
Typical current consumption, code executing from Flash,
running from HSE 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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List of tables
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
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I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
WLCSP25 - 25-ball, 2.423 x 2.325 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
WLCSP25 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 101
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
DocID025743 Rev 3
STM32F031x4 STM32F031x6
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LQFP48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LQFP32 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
UFQFPN32 32-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
UFQFPN28 28-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
WLCSP25 25-ball package ballout (bump side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TSSOP20 20-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM32F031x4/x6 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 62
HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
I2S slave timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
I2S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 87
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 91
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
UFQFPN28 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
DocID025743 Rev 3
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8
List of figures
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
8/113
STM32F031x4 STM32F031x6
WLCSP25 - 25-ball, 2.423 x 2.325 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
WLCSP25 - 25-ball, 2.133 x 2.070 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
WLCSP25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
DocID025743 Rev 3
STM32F031x4 STM32F031x6
1
Introduction
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F031x4/x6 microcontrollers.
This document should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the ARM® Cortex®-M0 core, please refer to the Cortex®-M0 Technical
Reference Manual, available from the www.arm.com website.
DocID025743 Rev 3
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23
Description
2
STM32F031x4 STM32F031x6
Description
The STM32F031x4/x6 microcontrollers incorporate the high-performance ARM® Cortex®M0 32-bit RISC core operating at a 48 MHz maximum frequency, high-speed embedded
memories (up to 32 Kbytes of Flash memory and 4 Kbytes of SRAM), and an extensive
range of enhanced peripherals and I/Os. All devices offer standard communication
interfaces (one I2C, one SPI/ I2S and one USART), one 12-bit ADC, five 16-bit timers, one
32-bit timer and an advanced-control PWM timer.
The STM32F031x4/x6 microcontrollers operate in the -40 to +85 °C and -40 to +105 °C
temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of powersaving modes allows the design of low-power applications.
The STM32F031x4/x6 microcontrollers include devices in six different packages ranging
from 20 pins to 48 pins with a die form also available upon request. Depending on the
device chosen, different sets of peripherals are included. The description below provides an
overview of the complete range of STM32F031x4/x6 peripherals proposed.
These features make the STM32F031x4/x6 microcontrollers suitable for a wide range of
applications such as application control and user interfaces, hand-held equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
Table 2. STM32F031x4/x6 family device features and peripheral counts
Peripheral
Flash (Kbyte)
STM32F031Fx STM32F031Ex STM32F031Gx
16
32
32
16
32
SRAM (Kbyte)
Advanced
control
1 (16-bit)
General
purpose
4 (16-bit)
1 (32-bit)
SPI [I2S](1)
1
USART
1
GPIOs
1
(9 ext. + 3 int.)
15
20
23
25 (on LQFP32)
27 (on UFQFPN32)
39
2.0 to 3.6 V
Ambient operating temperature: -40°C to 85°C / -40°C to 105°C
Junction temperature: -40°C to 105°C / -40°C to 125°C
TSSOP20
WLCSP25
UFQFPN28
1. The SPI interface can be used either in SPI mode or in I2S audio mode.
10/113
32
48 MHz
Operating voltage
Packages
16
1
(10 ext. + 3 int.)
Max. CPU frequency
Operating temperature
32
1 [1]
I2C
12-bit ADC
(number of channels)
16
STM32F031Cx
4
Timers
Comm.
interfaces
STM32F031Kx
DocID025743 Rev 3
LQFP32
UFQFPN32
LQFP48
STM32F031x4 STM32F031x6
Description
Figure 1. Block diagram
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11/113
23
Functional overview
STM32F031x4 STM32F031x6
3
Functional overview
3.1
ARM®-Cortex®-M0 core with embedded Flash and SRAM
The ARM® Cortex®-M0 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM® Cortex®-M0 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F0xx family has an embedded ARM core and is therefore compatible with all
ARM tools and software.
Figure 1 shows the general block diagram of the device family.
3.2
Memories
The device has the following features:
4 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
The non-volatile memory is divided into two arrays:
–
16 to 32 Kbytes of embedded Flash memory for programs and data
–
Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
–
Level 0: no readout protection
–
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
®
Level 2: chip readout protection, debug features (Cortex -M0 serial wire) and
boot in RAM selection disabled
–
3.3
Boot modes
At startup, the boot pin and boot selector option bit are used to select one of the three boot
options:
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART on pins PA14/PA15 or PA9/PA10.
12/113
DocID025743 Rev 3
STM32F031x4 STM32F031x6
3.4
Functional overview
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a CRC-32 (Ethernet) polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
3.5
Power management
3.5.1
Power supply schemes
VDD = VDDIO1 = 2.0 to 3.6 V: external power supply for I/Os (VDDIO1) and the internal
regulator. It is provided externally through VDD pins.
VDDA = from VDD to 3.6 V: external analog power supply for ADC, Reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). It is
provided externally through VDDA pin. The VDDA voltage level must be always greater
or equal to the VDD voltage level and must be established first.
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 12: Power supply scheme.
3.5.2
Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.5.3
Voltage regulator
The regulator has two operating modes and it is always enabled after reset.
Main (MR) is used in normal operating mode (Run).
Low power (LPR) can be used in Stop mode where the power demand is reduced.
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23
Functional overview
STM32F031x4 STM32F031x6
In Standby mode, it is put in power down mode. In this mode, the regulator output is in high
impedance and the kernel circuitry is powered down, inducing zero consumption (but the
contents of the registers and SRAM are lost).
3.5.4
Low-power modes
The STM32F031x4/x6 microcontrollers support three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC, I2C1 or USART1.
The peripherals listed above can be configured to enable the HSI RC oscillator for
processing incoming data. If this is used when the voltage regulator is put in low power
mode, the regulator is first switched to normal mode before the clock is provided to the
given peripheral.
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the RTC
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pins, or an RTC event occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
3.6
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
14/113
DocID025743 Rev 3
STM32F031x4 STM32F031x6
Functional overview
Figure 2. Clock tree
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DocID025743 Rev 3
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23
Functional overview
3.7
STM32F031x4 STM32F031x6
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.8
Direct memory access controller (DMA)
The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPI, I2S, I2C, USART, all TIMx timers (except
TIM14) and ADC.
3.9
Interrupts and events
3.9.1
Nested vectored interrupt controller (NVIC)
The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to
®
32 maskable interrupt channels (not including the 16 interrupt lines of Cortex -M0) and 4
priority levels.
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.9.2
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 39
GPIOs can be connected to the 16 external interrupt lines.
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DocID025743 Rev 3
STM32F031x4 STM32F031x6
3.10
Functional overview
Analog to digital converter (ADC)
The 12-bit analog to digital converter has up to 16 external and 3 internal (temperature
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1
Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 3. Temperature sensor calibration values
Calibration value name
3.10.2
Description
Memory address
TS_CAL1
TS ADC raw data acquired at a
temperature of 30 °C (5 °C),
VDDA= 3.3 V (10 mV)
TS_CAL2
TS ADC raw data acquired at a
temperature of 110 °C (5 °C), 0x1FFF F7C2 - 0x1FFF F7C3
VDDA= 3.3 V (10 mV)
0x1FFF F7B8 - 0x1FFF F7B9
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and comparators. VREFINT is internally connected to the ADC_IN17 input channel. The
precise voltage of VREFINT is individually measured for each part by ST during production
test and stored in the system memory area. It is accessible in read-only mode.
Table 4. Internal voltage reference calibration values
Calibration value name
VREFINT_CAL
Description
Memory address
Raw data acquired at a
temperature of 30 °C (5 °C), 0x1FFF F7BA - 0x1FFF F7BB
VDDA= 3.3 V (10 mV)
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23
Functional overview
3.10.3
STM32F031x4 STM32F031x6
VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC_IN18. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 2. As a consequence, the converted digital value is half the VBAT voltage.
3.11
Timers and watchdogs
The STM32F031x4/x6 devices include up to five general-purpose timers and an advanced
control timer.
Table 5 compares the features of the different timers.
Table 5. Timer feature comparison
Timer
type
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA request
generation
Advanced
control
TIM1
16-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Yes
4
3
TIM2
32-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Yes
4
No
TIM3
16-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Yes
4
No
TIM14
16-bit
Up
Any integer
between 1
and 65536
No
1
No
TIM16,
TIM17
16-bit
Up
Any integer
between 1
and 65536
Yes
1
1
General
purpose
3.11.1
Capture/compare Complementary
channels
outputs
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
Input capture
Output compare
PWM generation (edge or center-aligned modes)
One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
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STM32F031x4 STM32F031x6
Functional overview
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.11.2
General-purpose timers (TIM2..3, TIM14, 16, 17)
There are six synchronizable general-purpose timers embedded in the STM32F031x4/x6
devices (see Table 5 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
TIM2, TIM3
STM32F031x4/x6 devices feature two synchronizable 4-channel general-purpose timers.
TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based
on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advancedcontrol timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM16 and TIM17
Both timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
They each have a single channel for input capture/output compare, PWM or one-pulse
mode output.
TIM16 and TIM17 have a complementary output with dead-time generation and
independent DMA request generation.
Their counters can be frozen in debug mode.
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23
Functional overview
3.11.3
STM32F031x4 STM32F031x6
Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.11.4
System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
3.11.5
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
3.12
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source (HCLK or HCLK/8)
Real-time clock (RTC) and backup registers
The RTC and the five backup registers are supplied through a switch that takes power either
on VDD supply when present or through the VBAT pin. The backup registers are five 32-bit
registers used to store 20 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
20/113
Calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
Automatic correction for 28, 29 (leap year), 30, and 31 day of the month.
Programmable alarm with wake up from Stop and Standby mode capability.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize the RTC with a master clock.
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
Two anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
DocID025743 Rev 3
STM32F031x4 STM32F031x6
Functional overview
The RTC clock sources can be:
3.13
A 32.768 kHz external crystal
A resonator or oscillator
The internal low-power RC oscillator (typical frequency of 40 kHz)
The high-speed external clock divided by 32
Inter-integrated circuit interfaces (I2C)
The I2C interface (I2C1) can operate in multimaster or slave modes. It can support Standard
mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode Plus (up to 1 Mbit/s)
with 20 mA output drive.
It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two
addresses, one with configurable mask). It also includes programmable analog and digital
noise filters.
Table 6. Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
50 ns
Programmable length from 1 to 15
I2C peripheral clocks
Benefits
Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks
Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled.
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C interface can be served by the DMA controller.
Table 7. STM32F031x4/x6 I2C implementation
I2C features(1)
I2C1
7-bit addressing mode
X
10-bit addressing mode
X
Standard mode (up to 100 kbit/s)
X
Fast mode (up to 400 kbit/s)
X
Fast Mode Plus with output drive I/Os (up to 1 Mbit/s)
X
Independent clock
X
SMBus
X
Wakeup from STOP
X
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Functional overview
STM32F031x4 STM32F031x6
1. X = supported.
3.14
Universal synchronous/asynchronous receiver transmitters
(USART)
The device embeds one universal synchronous/asynchronous receiver transmitter
(USART1), which communicate at speeds of up to 6 Mbit/s.
It provides hardware management of the CTS, RTS and RS485 DE signals, multiprocessor
communication mode, master synchronous communication and single-wire half-duplex
communication mode. USART1 supports also SmartCard communication (ISO 7816), IrDA
SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and has a clock
domain independent from the CPU clock, allowing to wake up the MCU from Stop mode.
The USART interface can be served by the DMA controller.
Table 8. STM32F031x4/x6 USART implementation
USART modes/features(1)
Hardware flow control for modem
X
Continuous communication using DMA
X
Multiprocessor communication
X
Synchronous mode
X
Smartcard mode
X
Single-wire half-duplex communication
X
IrDA SIR ENDEC block
X
LIN mode
X
Dual clock domain and wakeup from Stop mode
X
Receiver timeout interrupt
X
Modbus communication
X
Auto baud rate detection
X
Driver Enable
X
1. X = supported.
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USART1
DocID025743 Rev 3
STM32F031x4 STM32F031x6
3.15
Functional overview
Serial peripheral interface (SPI)/Inter-integrated sound
interfaces (I2S)
The SPI is able to communicate up to 18 Mbit/s in slave and master modes in full-duplex
and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
One standard I2S interface (multiplexed with SPI1) supporting four different audio standards
can operate as master or slave at half-duplex communication mode. It can be configured to
transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a
specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit
programmable linear prescaler. When operating in master mode, it can output a clock for an
external audio component at 256 times the sampling frequency.
Table 9. STM32F031x4/x6 SPI/I2S implementation
SPI features(1)
SPI
Hardware CRC calculation
X
Rx/Tx FIFO
X
NSS pulse mode
X
I2S mode
X
TI mode
X
1. X = supported.
3.16
Serial wire debug port (SW-DP)
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
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Pinouts and pin description
4
STM32F031x4 STM32F031x6
Pinouts and pin description
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DocID025743 Rev 3
STM32F031x4 STM32F031x6
Pinouts and pin description
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33
Pinouts and pin description
STM32F031x4 STM32F031x6
Figure 7. WLCSP25 25-ball package ballout (bump side)
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26/113
DocID025743 Rev 3
STM32F031x4 STM32F031x6
Pinouts and pin description
Table 10. Legend/abbreviations used in the pinout table
Name
Abbreviation
Pin name
Definition
Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
FTf
5 V tolerant I/O, FM+ capable
TTa
3.3 V tolerant I/O directly connected to ADC
TC
Standard 3.3V I/O
B
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Pin type
I/O structure
Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Notes
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions
Additional
Functions directly selected/enabled through peripheral registers
functions
Table 11. Pin definitions
Pin number
UFQFPN32
UFQFPN28
WLCSP25
TSSOP20
-
-
-
-
-
I/O structure
LQFP32
1
Pin name
(function after
reset)
Pin type
LQFP48
Pin functions
Notes
VBAT
S
-
-
Alternate functions
Additional
functions
Backup power supply
2
-
-
-
-
-
PC13
I/O
TC
(1)(2)
-
RTC_TAMP1,
RTC_TS,
RTC_OUT,
WKUP2
3
-
-
-
-
-
PC14-OSC32_IN
(PC14)
I/O
TC
(1)(2)
-
OSC32_IN
4
-
-
-
-
-
PC15OSC32_OUT
(PC15)
I/O
TC
(1)(2)
-
OSC32_OUT
5
2
2
2
A5
2
PF0-OSC_IN
(PF0)
I/O
FT
-
-
OSC_IN
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33
Pinouts and pin description
STM32F031x4 STM32F031x6
Table 11. Pin definitions (continued)
Pin number
LQFP48
LQFP32
UFQFPN32
UFQFPN28
WLCSP25
TSSOP20
Pin type
I/O structure
Pin functions
Notes
6
3
3
3
B5
3
PF1-OSC_OUT
(PF1)
I/O
FT
-
7
4
4
4
C5
4
NRST
I/O
RST
-
Device reset input / internal reset output
(active low)
8
-
0
-
E1
-
VSSA
S
-
Analog ground
9
5
5
5
D5
5
VDDA
S
-
Analog power supply
10
6
6
6
B4
6
PA0
I/O
TTa
-
TIM2_CH1_ETR,
USART1_CTS
ADC_IN0,
RTC_TAMP2,
WKUP1
11
7
7
7
C4
7
PA1
I/O
TTa
-
TIM2_CH2,
EVENTOUT,
USART1_RTS
ADC_IN1
12
8
8
8
D4
8
PA2
I/O
TTa
-
TIM2_CH3,
USART1_TX
ADC_IN2
13
9
9
9
E5
9
PA3
I/O
TTa
-
TIM2_CH4,
USART1_RX
ADC_IN3
-
SPI1_NSS,
I2S1_WS,
TIM14_CH1,
USART1_CK
ADC_IN4
-
SPI1_SCK,
I2S1_CK,
TIM2_CH1_ETR
ADC_IN5
-
SPI1_MISO,
I2S1_MCK,
TIM3_CH1,
TIM1_BKIN,
TIM16_CH1,
EVENTOUT
ADC_IN6
-
SPI1_MOSI,
I2S1_SD,
TIM3_CH2,
TIM14_CH1,
TIM1_CH1N,
TIM17_CH1,
EVENTOUT
ADC_IN7
14
15
16
17
10
11
12
13
28/113
10
11
12
13
10
11
12
13
B3
C3
D3
E4
10
11
12
13
Pin name
(function after
reset)
PA4
PA5
PA6
PA7
I/O
I/O
I/O
I/O
TTa
TTa
TTa
TTa
DocID025743 Rev 3
Alternate functions
Additional
functions
-
OSC_OUT
STM32F031x4 STM32F031x6
Pinouts and pin description
Table 11. Pin definitions (continued)
Pin number
LQFP48
LQFP32
UFQFPN32
UFQFPN28
WLCSP25
TSSOP20
Pin type
I/O structure
Pin functions
Notes
18
14
14
14
E3
-
PB0
I/O
TTa
-
TIM3_CH3,
TIM1_CH2N,
EVENTOUT
ADC_IN8
19
15
15
15
E2
14
PB1
I/O
TTa
-
TIM3_CH4,
TIM14_CH1,
TIM1_CH3N
ADC_IN9
20
-
16
-
-
-
PB2
I/O
FT
(3)
21
-
-
-
-
-
PB10
I/O
FTf
-
TIM2_CH3,
I2C1_SCL
-
22
-
-
-
-
-
PB11
I/O
FTf
-
TIM2_CH4,
EVENTOUT,
I2C1_SDA
-
23
16
0
16
E1
15
VSS
S
-
-
Ground
24
17
17
17
D1
16
VDD
S
-
-
Digital power supply
Pin name
(function after
reset)
Alternate functions
Additional
functions
25
-
-
-
-
-
PB12
I/O
FT
-
TIM1_BKIN,
EVENTOUT,
SPI1_NSS
26
-
-
-
-
-
PB13
I/O
FT
-
TIM1_CH1N,
SPI1_SCK
-
27
-
-
-
-
-
PB14
I/O
FT
-
TIM1_CH2N,
SPI1_MISO
-
28
-
-
-
-
-
PB15
I/O
FT
-
TIM1_CH3N,
SPI1_MOSI
RTC_REFIN
-
-
29
18
18
18
D2
-
PA8
I/O
FT
-
USART1_CK,
TIM1_CH1,
EVENTOUT,
MCO
30
19
19
19
C1
17
PA9
I/O
FTf
-
USART1_TX,
TIM1_CH2,
I2C1_SCL
-
-
USART1_RX,
TIM1_CH3,
TIM17_BKIN,
I2C1_SDA
-
31
20
20
20
B1
18
PA10
I/O
FTf
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33
Pinouts and pin description
STM32F031x4 STM32F031x6
Table 11. Pin definitions (continued)
Pin number
LQFP48
LQFP32
UFQFPN32
UFQFPN28
WLCSP25
TSSOP20
Pin type
I/O structure
Pin functions
Notes
32
21
21
-
-
-
PA11
I/O
FT
-
USART1_CTS,
TIM1_CH4,
EVENTOUT
-
33
22
22
-
-
-
PA12
I/O
FT
-
USART1_RTS,
TIM1_ETR,
EVENTOUT
-
34
23
23
21
A1
19
PA13
(SWDIO)
I/O
FT
(4)
IR_OUT,
SWDIO
-
35
-
-
-
-
-
PF6
I/O
FTf
-
I2C1_SCL
-
36
-
-
-
-
-
PF7
I/O
FTf
-
I2C1_SDA
-
37
24
24
22
A2
20
PA14
(SWCLK)
I/O
FT
(4)
USART1_TX,
SWCLK
-
-
SPI1_NSS,
I2S1_WS,
TIM2_CH_ETR,
EVENTOUT,
USART1_RX
-
-
SPI1_SCK,
I2S1_CK,
TIM2_CH2,
EVENTOUT
-
-
SPI1_MISO,
I2S1_MCK,
TIM3_CH1,
EVENTOUT
-
-
SPI1_MOSI,
I2S1_SD,
I2C1_SMBA,
TIM16_BKIN,
TIM3_CH2
-
-
-
38
39
40
41
25
26
27
28
25
26
27
28
23
24
25
26
-
-
-
C2
-
-
-
-
Pin name
(function after
reset)
PA15
PB3
PB4
PB5
I/O
I/O
I/O
I/O
FT
FT
FT
FT
Alternate functions
Additional
functions
42
29
29
27
B2
-
PB6
I/O
FTf
-
I2C1_SCL,
USART1_TX,
TIM16_CH1N
43
30
30
28
A3
-
PB7
I/O
FTf
-
I2C1_SDA,
USART1_RX,
TIM17_CH1N
30/113
DocID025743 Rev 3
STM32F031x4 STM32F031x6
Pinouts and pin description
Table 11. Pin definitions (continued)
Pin number
LQFP48
LQFP32
UFQFPN32
UFQFPN28
WLCSP25
TSSOP20
Pin type
I/O structure
Pin functions
Notes
44
31
31
1
A4
1
BOOT0
I
B
-
45
-
32
-
-
-
PB8
I/O
FTf
(3)
I2C1_SCL,
TIM16_CH1
-
I2C1_SDA,
IR_OUT,
TIM17_CH1,
EVENTOUT
-
Pin name
(function after
reset)
Alternate functions
Additional
functions
Boot memory selection
46
-
-
-
-
-
PB9
I/O
FTf
-
47
32
0
-
E1
-
VSS
S
-
-
Ground
48
1
1
-
-
-
VDD
S
-
-
Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content
of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the RTC
domain and RTC register descriptions in the reference manual.
3. On the LQFP32 package, PB2 and PB8 should be treated as unconnected pins (even when they are not available on the
package, they are not forced to a defined level by hardware).
4. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO pin
and the internal pull-down on the SWCLK pin are activated.
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33
DocID025743 Rev 3
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
PA0
-
USART1_CTS
TIM2_CH1_
ETR
-
-
-
-
-
PA1
EVENTOUT
USART1_RTS
TIM2_CH2
-
-
-
-
-
PA2
-
USART1_TX
TIM2_CH3
-
-
-
-
-
PA3
-
USART1_RX
TIM2_CH4
-
-
-
-
-
PA4
SPI1_NSS,
I2S1_WS
USART1_CK
-
-
TIM14_CH1
-
-
-
PA5
SPI1_SCK,
I2S1_CK
-
TIM2_CH1_
ETR
-
-
-
-
-
PA6
SPI1_MISO,
I2S1_MCK
TIM3_CH1
TIM1_BKIN
-
-
TIM16_CH1
EVENTOUT
-
PA7
SPI1_MOSI,
I2S1_SD
TIM3_CH2
TIM1_CH1N
-
TIM14_CH1
TIM17_CH1
EVENTOUT
-
PA8
MCO
USART1_CK
TIM1_CH1
EVENTOUT
-
-
-
-
PA9
-
USART1_TX
TIM1_CH2
-
I2C1_SCL
-
-
-
PA10
TIM17_BKIN
USART1_RX
TIM1_CH3
-
I2C1_SDA
-
-
-
PA11
EVENTOUT
USART1_CTS
TIM1_CH4
-
-
-
-
-
PA12
EVENTOUT
USART1_RTS
TIM1_ETR
-
-
-
-
-
PA13
SWDIO
IR_OUT
-
-
-
-
-
-
PA14
SWCLK
USART1_TX
-
-
-
-
-
-
PA15
SPI1_NSS,
I2S1_WS
USART1_RX
TIM2_CH1_
ETR
EVENTOUT
-
-
-
-
STM32F031x4 STM32F031x6
Pin name
Pinouts and pin description
32/113
Table 12. Alternate functions selected through GPIOA_AFR registers for port A
DocID025743 Rev 3
Pin name
AF0
AF1
AF2
AF3
PB0
EVENTOUT
TIM3_CH3
TIM1_CH2N
-
PB1
TIM14_CH1
TIM3_CH4
TIM1_CH3N
-
PB2
-
-
-
-
PB3
SPI1_SCK, I2S1_CK
EVENTOUT
TIM2_CH2
-
PB4
SPI1_MISO, I2S1_MCK
TIM3_CH1
EVENTOUT
-
PB5
SPI1_MOSI, I2S1_SD
TIM3_CH2
TIM16_BKIN
I2C1_SMBA
PB6
USART1_TX
I2C1_SCL
TIM16_CH1N
-
PB7
USART1_RX
I2C1_SDA
TIM17_CH1N
-
PB8
-
I2C1_SCL
TIM16_CH1
-
PB9
IR_OUT
I2C1_SDA
TIM17_CH1
EVENTOUT
PB10
-
I2C1_SCL
TIM2_CH3
-
PB11
EVENTOUT
I2C1_SDA
TIM2_CH4
-
PB12
SPI1_NSS
EVENTOUT
TIM1_BKIN
-
PB13
SPI1_SCK
-
TIM1_CH1N
-
PB14
SPI1_MISO
-
TIM1_CH2N
-
PB15
SPI1_MOSI
-
TIM1_CH3N
-
STM32F031x4 STM32F031x6
Table 13. Alternate functions selected through GPIOB_AFR registers for port B
Pinouts and pin description
33/113
Memory mapping
5
STM32F031x4 STM32F031x6
Memory mapping
Figure 9. STM32F031x4/x6 memory map
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34/113
DocID025743 Rev 3
STM32F031x4 STM32F031x6
Memory mapping
Table 14. STM32F031x4/x6 peripheral register boundary addresses
Bus
AHB2
Boundary address
Size
Peripheral
0x4800 1800 - 0x5FFF FFFF
~384 MB
Reserved
0x4800 1400 - 0x4800 17FF
1KB
GPIOF
0x4800 0C00 - 0x4800 13FF
2KB
Reserved
0x4800 0800 - 0x4800 0BFF
1KB
GPIOC
0x4800 0400 - 0x4800 07FF
1KB
GPIOB
0x4800 0000 - 0x4800 03FF
1KB
GPIOA
0x4002 4400 - 0x47FF FFFF
~128 MB
Reserved
0x4002 3400 - 0x4002 3FFF
3 KB
Reserved
0x4002 3000 - 0x4002 33FF
1 KB
CRC
0x4002 2400 - 0x4002 2FFF
3 KB
Reserved
0x4002 2000 - 0x4002 23FF
1 KB
FLASH Interface
0x4002 1400 - 0x4002 1FFF
3 KB
Reserved
0x4002 1000 - 0x4002 13FF
1 KB
RCC
0x4002 0400 - 0x4002 0FFF
3 KB
Reserved
0x4002 0000 - 0x4002 03FF
1 KB
DMA
0x4001 8000 - 0x4001 FFFF
32 KB
Reserved
0x4001 5C00 - 0x4001 7FFF
9KB
Reserved
0x4001 5800 - 0x4001 5BFF
1KB
DBGMCU
0x4001 4C00 - 0x4001 57FF
3KB
Reserved
0x4001 4800 - 0x4001 4BFF
1KB
TIM17
0x4001 4400 - 0x4001 47FF
1KB
TIM16
0x4001 3C00 - 0x4001 43FF
2KB
Reserved
0x4001 3800 - 0x4001 3BFF
1KB
USART1
0x4001 3400 - 0x4001 37FF
1KB
Reserved
0x4001 3000 - 0x4001 33FF
1KB
SPI1/I2S1
0x4001 2C00 - 0x4001 2FFF
1KB
TIM1
0x4001 2800 - 0x4001 2BFF
1KB
Reserved
0x4001 2400 - 0x4001 27FF
1KB
ADC
0x4001 0800 - 0x4001 23FF
7KB
Reserved
0x4001 0400 - 0x4001 07FF
1KB
EXTI
0x4001 0000 - 0x4001 03FF
1KB
SYSCFG
0x4000 8000 - 0x4000 FFFF
32 KB
Reserved
AHB1
APB
DocID025743 Rev 3
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36
Memory mapping
STM32F031x4 STM32F031x6
Table 14. STM32F031x4/x6 peripheral register boundary addresses (continued)
Bus
APB
36/113
Boundary address
Size
Peripheral
0x4000 7400 - 0x4000 7FFF
3KB
Reserved
0x4000 7000 - 0x4000 73FF
1KB
PWR
0x4000 5800 - 0x4000 6FFF
6KB
Reserved
0x4000 5400 - 0x4000 57FF
1KB
I2C1
0x4000 3400 - 0x4000 53FF
8KB
Reserved
0x4000 3000 - 0x4000 33FF
1KB
IWDG
0x4000 2C00 - 0x4000 2FFF
1KB
WWDG
0x4000 2800 - 0x4000 2BFF
1KB
RTC
0x4000 2400 - 0x4000 27FF
1KB
Reserved
0x4000 2000 - 0x4000 23FF
1KB
TIM14
0x4000 0800 - 0x4000 1FFF
6KB
Reserved
0x4000 0400 - 0x4000 07FF
1KB
TIM3
0x4000 0000 - 0x4000 03FF
1KB
TIM2
DocID025743 Rev 3
STM32F031x4 STM32F031x6
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3.3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 10. Pin loading conditions
Figure 11. Pin input voltage
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DocID025743 Rev 3
069
37/113
86
Electrical characteristics
6.1.6
STM32F031x4 STM32F031x6
Power supply scheme
Figure 12. Power supply scheme
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38/113
Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
DocID025743 Rev 3
STM32F031x4 STM32F031x6
6.1.7
Electrical characteristics
Current consumption measurement
Figure 13. Current consumption measurement scheme
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DocID025743 Rev 3
39/113
86
Electrical characteristics
6.2
STM32F031x4 STM32F031x6
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 15: Voltage characteristics,
Table 16: Current characteristics and Table 17: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 15. Voltage characteristics(1)
Symbol
Ratings
Min
Max
Unit
VDD–VSS
External main supply voltage
-0.3
4.0
V
VDDA–VSS
External analog supply voltage
-0.3
4.0
V
VDD–VDDA
Allowed voltage difference for VDD > VDDA
-
0.4
V
VBAT–VSS
External backup supply voltage
-0.3
4.0
VIN(2)
Input voltage on FT and FTf pins
VSS 0.3
VDDIOx +
Input voltage on TTa pins
VSS 0.3
4.0
V
0
9.0
V
VSS 0.3
4.0
V
Variations between different VDD power pins
-
50
mV
Variations between all the different ground
pins
-
50
mV
BOOT0
Input voltage on any other pin
|VDDx|
|VSSx VSS|
VESD(HBM)
V
Electrostatic discharge voltage
(human body model)
4.0(3)
V
see Section 6.3.12: Electrical
sensitivity characteristics
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 16: Current characteristics for the maximum
allowed injected current values.
3. Valid only if the internal pull-up/pull-down resistors are disabled. If internal pull-up or pull-down resistor is
enabled, the maximum limit is 4 V.
40/113
DocID025743 Rev 3
STM32F031x4 STM32F031x6
Electrical characteristics
Table 16. Current characteristics
Symbol
Ratings
Max.
IVDD
Total current into sum of all VDD power lines (source)(1)
120
IVSS
(1)
-120
Total current out of sum of all VSS ground lines (sink)
IVDD(PIN)
Maximum current into each VDD power pin (source)
(1)
100
IVSS(PIN)
Maximum current out of each VSS ground pin (sink)(1)
-100
Output current sunk by any I/O and control pin
IIO(PIN)
IIO(PIN)
25
Output current source by any I/O and control pin
Total output current sunk by sum of all I/Os and control pins
-25
(2)
80
Total output current sourced by sum of all I/Os and control pins(2)
-80
IINJ(PIN)
Injected current on TC and RST pin
Injected current on TTa pins
IINJ(PIN)
mA
-5/+0(4)
Injected current on B, FT and FTf pins
(3)
Unit
±5
(5)
±5
Total injected current (sum of all I/O and control pins)(6)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 15: Voltage characteristics for the maximum allowed input voltage values.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the
device. See note (2) below Table 52: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 17. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
DocID025743 Rev 3
Value
Unit
–65 to +150
°C
150
°C
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86
Electrical characteristics
STM32F031x4 STM32F031x6
6.3
Operating conditions
6.3.1
General operating conditions
Table 18. General operating conditions
Symbol
Parameter
Conditions
Min
Max
fHCLK
Internal AHB clock frequency
-
0
48
fPCLK
Internal APB clock frequency
-
0
48
VDD
Standard operating voltage
-
2.0
3.6
VDD
3.6
2.4
3.6
1.65
3.6
TC and RST I/O
–0.3
VDDIOx+0.3
TTa I/O
–0.3
VDDA+0.3(1)
FT and FTf I/O
–0.3
5.5(1)
BOOT0
0
5.5
LQFP48
-
364
UFQFPN32
-
526
LQFP32
-
357
UFQFPN28
-
169
WLCSP25
-
267
TSSOP20
-
182
–40
85
–40
105
MHz
Analog operating voltage
(ADC not used)
VDDA
VBAT
VIN
PD
Unit
Must have a potential equal
to or higher than VDD
Analog operating voltage
(ADC used)
Backup operating voltage
-
V
I/O input voltage
Power dissipation at TA = 85 °C
for suffix 6 or TA = 105 °C for
suffix 7(2)
V
V
V
mW
Ambient temperature for the
suffix 6 version
Maximum power dissipation
Ambient temperature for the
suffix 7 version
Maximum power dissipation
–40
105
Low power dissipation(3)
–40
125
Suffix 6 version
–40
105
Suffix 7 version
–40
125
Low power dissipation
(3)
°C
TA
TJ
°C
Junction temperature range
°C
1. For operation with a voltage higher than VDDIOx + 0.3 V, the internal pull-up resistor must be disabled.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. See Section 7.8: Thermal characteristics.
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.8:
Thermal characteristics).
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DocID025743 Rev 3
STM32F031x4 STM32F031x6
6.3.2
Electrical characteristics
Operating conditions at power-up / power-down
The parameters given in Table 19 are derived from tests performed under the ambient
temperature condition summarized in Table 18.
Table 19. Operating conditions at power-up / power-down
Symbol
Parameter
Min
Max
0
VDD fall time rate
20
VDDA rise time rate
0
20
VDD rise time rate
tVDD
tVDDA
6.3.3
Conditions
-
-
VDDA fall time rate
Unit
µs/V
Embedded reset and power control block characteristics
The parameters given in Table 20 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 18: General operating
conditions.
Table 20. Embedded reset and power control block characteristics
Symbol
Parameter
VPOR/PDR(1)
VPDRhyst
tRSTTEMPO
(4)
Power on/power down
reset threshold
Conditions
Min
Typ
Max
Unit
Falling edge(2)
1.80
1.88
1.96(3)
V
1.84(3)
1.92
2.00
V
-
40
-
mV
1.50
2.50
4.50
ms
Rising edge
PDR hysteresis
Reset temporization
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Data based on characterization results, not tested in production.
4. Guaranteed by design, not tested in production.
Table 21. Programmable voltage detector characteristics
Symbol
Parameter
VPVD0
PVD threshold 0
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
Conditions
Min
Typ
Max
Unit
Rising edge
2.1
2.18
2.26
V
Falling edge
2
2.08
2.16
V
Rising edge
2.19
2.28
2.37
V
Falling edge
2.09
2.18
2.27
V
Rising edge
2.28
2.38
2.48
V
Falling edge
2.18
2.28
2.38
V
Rising edge
2.38
2.48
2.58
V
Falling edge
2.28
2.38
2.48
V
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86
Electrical characteristics
STM32F031x4 STM32F031x6
Table 21. Programmable voltage detector characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rising edge
2.47
2.58
2.69
V
Falling edge
2.37
2.48
2.59
V
Rising edge
2.57
2.68
2.79
V
Falling edge
2.47
2.58
2.69
V
Rising edge
2.66
2.78
2.9
V
Falling edge
2.56
2.68
2.8
V
Rising edge
2.76
2.88
3
V
Falling edge
2.66
2.78
2.9
V
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
VPVD7
PVD threshold 7
VPVDhyst(1)
PVD hysteresis
-
100
-
mV
PVD current consumption
-
0.15
0.26(1)
µA
IDD(PVD)
1. Guaranteed by design, not tested in production.
6.3.4
Embedded reference voltage
The parameters given in Table 22 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 18: General operating
conditions.
Table 22. Embedded internal reference voltage
Symbol
Parameter
VREFINT
Internal reference voltage
tSTART
Conditions
Min
Typ
Max
Unit
–40 °C < TA < +105 °C
1.16
1.2
1.25
V
V
–40 °C < TA < +85 °C
1.16
1.2
1.24(1)
ADC_IN17 buffer startup
time
-
-
-
10(2)
µs
tS_vrefint
ADC sampling time when
reading the internal
reference voltage
-
4(2)
-
-
µs
VREFINT
Internal reference voltage
spread over the
temperature range
VDDA = 3 V
-
-
10(2)
mV
-
- 100(2)
-
100(2) ppm/°C
TCoeff
Temperature coefficient
1. Data based on characterization results, not tested in production.
2. Guaranteed by design, not tested in production.
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STM32F031x4 STM32F031x6
6.3.5
Electrical characteristics
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 13: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted to the fHCLK frequency:
–
0 wait state and Prefetch OFF from 0 to 24 MHz
–
1 wait state and Prefetch ON above 24 MHz
When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 23Table 23 to Table 27 are derived from tests performed
under ambient temperature and supply voltage conditions summarized in Table 18: General
operating conditions.
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86
Electrical characteristics
STM32F031x4 STM32F031x6
Table 23. Typical and maximum current consumption from the VDD supply at VDD = 3.6 V
All peripherals enabled
Symbol Parameter Conditions
Max @ TA(1)
fHCLK
Max @ TA(1)
Typ
HSE
bypass,
PLL on
Supply
current in
Run mode,
code
executing
from Flash
HSE
bypass,
PLL off
HSI clock,
PLL on
HSI clock,
PLL off
IDD
HSE
bypass,
PLL on
Supply
current in
Run mode,
code
executing
from RAM
HSE
bypass,
PLL off
HSI clock,
PLL on
HSI clock,
PLL off
HSE
bypass,
PLL on
IDD
Supply
current in
Sleep
mode,
code
executing
from Flash
or RAM
HSE
bypass,
PLL off
HSI clock,
PLL on
HSI clock,
PLL off
All peripherals disabled
Unit
Typ
25 °C
85 °C
105 °C
25 °C
85 °C
105 °C
48 MHz 18.4
20.0
20.1
20.4
11.4
12.5
12.5
12.6
32 MHz 12.4
13.2
13.2
13.8
7.9
8.3
8.5
8.6
24 MHz
9.9
10.7
10.7
11.0
6.2
6.8
7.0
7.0
8 MHz
3.3
3.6
3.8
3.9
2.2
2.6
2.6
2.6
1 MHz
0.8
1.1
1.1
1.1
0.7
0.9
0.9
0.9
48 MHz 18.9
20.9
21.1
21.5
11.7
12.3
12.9
13.1
32 MHz 12.8
13.7
14.2
14.8
8.0
8.7
9.1
9.1
24 MHz
9.7
10.4
11.2
11.3
6.1
6.5
6.7
6.9
8 MHz
3.5
4.0
4.0
4.1
2.4
2.6
2.7
2.7
48 MHz 17.3 19.7(2)
19.8
20.0(2)
10.3 11.2(2)
11.3
11.7(2)
32 MHz 11.2
12.5
12.7
12.7
6.7
7.3
7.6
7.6
24 MHz
8.9
10.0
10.1
10.2
5.1
5.5
5.8
5.9
8 MHz
2.8
3.1
3.3
3.4
1.7
2.0
2.1
2.1
1 MHz
0.3
0.6
0.6
1.3
0.2
0.5
0.8
0.9
48 MHz 17.4
19.7
20.0
20.2
10.4
11.2
11.3
11.8
32 MHz 11.8
12.8
13.1
13.3
6.8
7.4
7.7
7.9
24 MHz
9.0
10.0
10.1
10.2
5.2
5.7
6.0
6.0
8 MHz
3.0
3.2
3.5
3.6
1.8
2.0
2.2
2.2
48 MHz 10.7 11.7(2)
11.9
12.5(2)
2.4
2.6(2)
2.7
2.9(2)
32 MHz
7.1
7.8
8.1
8.2
1.6
1.7
1.9
1.9
24 MHz
5.5
6.3
6.4
6.4
1.3
1.4
1.5
1.5
8 MHz
1.8
2.0
2.0
2.1
0.4
0.4
0.5
0.5
1 MHz
0.2
0.5
0.5
0.5
0.1
0.1
0.1
0.1
48 MHz 10.8
11.9
12.1
12.6
2.4
2.7
2.7
2.9
32 MHz
7.3
8.0
8.4
8.5
1.7
1.9
1.9
2.0
24 MHz
5.5
6.2
6.5
6.5
1.3
1.5
1.5
1.6
8 MHz
1.9
2.2
2.3
2.4
0.5
0.5
0.5
0.6
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA).
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mA
mA
STM32F031x4 STM32F031x6
Electrical characteristics
Table 24. Typical and maximum current consumption from the VDDA supply
VDDA = 2.4 V
Symbol Parameter
Conditions
(1)
VDDA = 3.6 V
Max @ TA(2)
fHCLK
Max @ TA(2)
25 °C
IDDA
Supply
current in
Run or
Sleep
mode,
code
executing
from Flash
or RAM
HSE
bypass,
PLL on
HSE
bypass,
PLL off
HSI clock,
PLL on
HSI clock,
PLL off
Unit
Typ
Typ
85 °C 105 °C
25 °C
85 °C 105 °C
48 MHz
150
170(3)
178
182(3)
164
183(3)
195
198(3)
32 MHz
104
121
126
128
113
129
135
138
24 MHz
82
96
100
103
88
102
106
108
8 MHz
2.0
2.7
3.1
3.3
3.5
3.8
4.1
4.4
1 MHz
2.0
2.7
3.1
3.3
3.5
3.8
4.1
4.4
48 MHz
220
240
248
252
244
263
275
278
32 MHz
174
191
196
198
193
209
215
218
24 MHz
152
167
173
174
168
183
190
192
8 MHz
72
79
82
83
83.5
91
94
95
µA
1. Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled, being
in Run or Sleep mode or executing from Flash or RAM. Furthermore, when the PLL is off, IDDA is independent from the
frequency.
2. Data based on characterization results, not tested in production unless otherwise specified.
3. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA).
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86
Electrical characteristics
STM32F031x4 STM32F031x6
Table 25. Typical and maximum current consumption in Stop and Standby modes
Max(1)
Typ @VDD (VDD = VDDA)
Parameter
Supply
current
in Stop
mode
IDD
Supply
current
in
Standby
mode
Supply
current
in Stop
mode
Supply
current
in
Standby
mode
Conditions
2.0 V 2.4 V
Regulator in run
mode, all oscillators
OFF
TA =
TA = TA =
25 °C 85 °C 105 °C
15.25 15.45
15.7
16
18(2)
38
55(2)
Regulator in lowpower mode, all
oscillators OFF
3.15
3.25
3.35
3.45
3.7
4
5.5(2)
22
41(2)
LSI ON and IWDG
ON
0.8
0.95
1.05
1.2
1.35
1.5
-
-
-
LSI OFF and IWDG
OFF
0.65
0.75
0.85
0.95
1.1
1.3
2(2)
2.5
3(2)
Regulator in run
mode, all
oscillators OFF
1.85
2
2.15
2.3
2.45
2.6
3.5(2)
3.5
4.5(2)
Regulator in lowpower mode, all 1.85
oscillators OFF
2
2.15
2.3
2.45
2.6
3.5(2)
3.5
4.5(2)
VDDA monitoring OFF
Supply
current
in
Standby
mode
3.0 V 3.3 V 3.6 V
15.1
IDDA
Supply
current
in Stop
mode
2.7 V
15
VDDA monitoring ON
Symbol
µA
LSI ON and
IWDG ON
2.25
2.5
2.65
2.85
3.05
3.3
-
-
-
LSI OFF and
IWDG OFF
1.75
1.9
2
2.15
2.3
2.5
3.5(2)
3.5
4.5(2)
Regulator in run
mode, all
oscillators OFF
1.11
1.15
1.18
1.22
1.27
1.35
-
-
-
Regulator in lowpower mode, all
oscillators OFF
1.11
1.15
1.18
1.22
1.27
1.35
-
-
-
LSI ON and
IWDG ON
1.5
1.58
1.65
1.78
1.91
2.04
-
-
-
LSI OFF and
IWDG OFF
1
1.02
1.05
1.05
1.15
1.22
-
-
-
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA).
48/113
Unit
DocID025743 Rev 3
STM32F031x4 STM32F031x6
Electrical characteristics
Table 26. Typical and maximum current consumption from the VBAT supply
Max(1)
RTC
domain
IDD_VBAT
supply
current
LSE & RTC ON; “Xtal
mode”: lower driving
capability;
LSEDRV[1:0] = '00'
= 3.6 V
= 3.3 V
= 2.7 V
Conditions
= 2.4 V
Parameter
= 1.8 V
Symbol
= 1.65 V
Typ @ VBAT
0.47 0.49 0.59 0.65 0.80 0.91
TA =
25 °C
1.0
TA =
TA =
85 °C 105 °C
1.3
Unit
1.7
µA
LSE & RTC ON; “Xtal
mode” higher driving
capability;
LSEDRV[1:0] = '11'
0.76 0.79 0.88 0.98 1.13 1.21
1.3
1.6
2.1
1. Data based on characterization results, not tested in production.
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86
Electrical characteristics
STM32F031x4 STM32F031x6
Typical current consumption
The MCU is placed under the following conditions:
VDD = VDDA = 3.3 V
All I/O pins are in analog input configuration
The Flash access time is adjusted to fHCLK frequency:
–
0 wait state and Prefetch OFF from 0 to 24 MHz
–
1 wait state and Prefetch ON above 24 MHz
When the peripherals are enabled, fPCLK = fHCLK
PLL is used for frequencies greater than 8 MHz
AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
Table 27. Typical current consumption, code executing from Flash,
running from HSE 8 MHz crystal
Typical run mode
Symbol
IDD
IDDA
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Parameter
Current
from VDD
supply
Current
from VDDA
supply
fHCLK
Typical Sleep mode
unit
Peripheral
Peripheral
Peripheral
Peripheral
s enabled
s enabled
s disabled
s disabled
48MHz
20.2
12.3
11.1
2.9
36 MHz
15.3
9.5
8.4
2.4
32 MHz
13.6
8.6
7.5
2.2
24 MHz
10.5
6.7
5.9
1.8
16 MHz
7.2
4.7
4.1
1.4
8 MHz
3.8
2.7
2.3
0.9
4 MHz
2.4
1.8
1.7
0.9
2 MHz
1.6
1.3
1.2
0.8
1 MHz
1.2
1.1
1.0
0.8
500 kHz
1.0
1.0
0.9
0.8
mA
48MHz
155
36 MHz
117
32 MHz
105
24 MHz
83
16 MHz
60
8 MHz
2.2
4 MHz
2.2
2 MHz
2.2
1 MHz
2.2
500 kHz
2.2
uA
DocID025743 Rev 3
STM32F031x4 STM32F031x6
Electrical characteristics
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 46: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 29: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
I SW = V DDIOx f SW C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT + CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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Electrical characteristics
STM32F031x4 STM32F031x6
Table 28. Switching output I/O current consumption
Symbol
Parameter
Conditions(1)
VDDIOx = 3.3 V
C =CINT
VDDIOx = 3.3 V
CEXT = 0 pF
C = CINT + CEXT+ CS
VDDIOx = 3.3 V
CEXT = 10 pF
C = CINT + CEXT+ CS
ISW
I/O current
consumption
VDDIOx = 3.3 V
CEXT = 22 pF
C = CINT + CEXT+ CS
VDDIOx = 3.3 V
CEXT = 33 pF
C = CINT + CEXT+ CS
VDDIOx = 3.3 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
VDDIOx = 2.4 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
1. CS = 7 pF (estimated value).
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I/O toggling
frequency (fSW)
Typ
4 MHz
0.07
8 MHz
0.15
16 MHz
0.31
24 MHz
0.53
48 MHz
0.92
4 MHz
0.18
8 MHz
0.37
16 MHz
0.76
24 MHz
1.39
48 MHz
2.188
4 MHz
0.32
8 MHz
0.64
16 MHz
1.25
24 MHz
2.23
48 MHz
4.442
4 MHz
0.49
8 MHz
0.94
16 MHz
2.38
24 MHz
3.99
4 MHz
0.64
8 MHz
1.25
16 MHz
3.24
24 MHz
5.02
4 MHz
0.81
8 MHz
1.7
16 MHz
3.67
4 MHz
0.66
8 MHz
1.43
16 MHz
2.45
24 MHz
4.97
Unit
mA
STM32F031x4 STM32F031x6
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 29. The MCU is placed
under the following conditions:
All I/O pins are in analog mode
All peripherals are disabled unless otherwise mentioned
The given value is calculated by measuring the current consumption
–
with all peripherals clocked off
–
with only one peripheral clocked on
Ambient operating temperature and supply voltage conditions summarized in Table 15:
Voltage characteristics
The power consumption of the digital part of the on-chip peripherals is given in
Table 29. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 29. Peripheral current consumption
Peripheral
Typical consumption at 25 °C
BusMatrix(1)
3.8
DMA1
6.3
SRAM
0.7
Flash interface
15.2
CRC
1.61
GPIOA
9.4
GPIOB
11.6
GPIOC
1.9
GPIOF
0.8
All AHB peripherals
47.5
AHB
Unit
µA/MHz
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Electrical characteristics
STM32F031x4 STM32F031x6
Table 29. Peripheral current consumption (continued)
Peripheral
APB-Bridge
Typical consumption at 25 °C
(2)
2.6
SYSCFG
ADC
1.7
(3)
4.2
TIM1
17.1
SPI1
9.6
USART1
17.4
TIM16
8.2
TIM17
8.0
DBG (MCU Debug Support)
0.5
TIM2
17.4
TIM3
12.8
TIM14
6.0
WWDG
1.5
I2C1
5.1
PWR
1.2
APB
µA/MHz
All APB peripherals
1.
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Unit
110.9
The BusMatrix automatically is active when at least one master is ON (CPU or DMA1).
2.
The APBx Bridge is automatically active when at least one peripheral is ON on the same Bus.
3.
The power consumption of the analog part (IDDA) of peripherals such as ADC is not included. Refer to the
tables of characteristics in the subsequent sections.
DocID025743 Rev 3
STM32F031x4 STM32F031x6
6.3.6
Electrical characteristics
Wakeup time from low-power mode
The wakeup times given in Table 30 are the latency between the event and the execution of
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.
During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.
The wakeup source from Standby mode is the WKUP1 pin (PA0).
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in Table 18: General operating conditions..
Table 30. Low-power mode wakeup timings
Typ @VDD = VDDA
Symbol
Parameter
Conditions
Max Unit
= 2.0 V = 2.4 V = 2.7 V
tWUSTOP
Wakeup from Stop
mode
=3V
= 3.3 V
Regulator in run
mode
3.2
3.1
2.9
2.9
2.8
5
Regulator in low
power mode
7.0
5.8
5.2
4.9
4.6
9
60.4
55.6
53.5
52
51
-
µs
tWUSTANDBY
tWUSLEEP
Wakeup from
Standby mode
-
Wakeup from Sleep
mode
-
4 SYSCLK cycles
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Electrical characteristics
6.3.7
STM32F031x4 STM32F031x6
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 14: High-speed external clock
source AC timing diagram.
Table 31. High-speed external user clock characteristics
Parameter(1)
Symbol
Min
Typ
Max
Unit
-
8
32
MHz
fHSE_ext
User external clock source frequency
VHSEH
OSC_IN input pin high level voltage
0.7 VDDIOx
-
VDDIOx
VHSEL
OSC_IN input pin low level voltage
VSS
-
0.3 VDDIOx
15
-
-
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
tr(HSE)
tf(HSE)
OSC_IN rise or fall time
V
ns
-
-
20
1. Guaranteed by design, not tested in production.
Figure 14. High-speed external clock source AC timing diagram
WZ+6(+
9+6(+
9+6(/
WU+6(
WI+6(
WZ+6(/
W
7+6(
069
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STM32F031x4 STM32F031x6
Electrical characteristics
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 15.
Table 32. Low-speed external user clock characteristics
Parameter(1)
Symbol
fLSE_ext User external clock source frequency
Min
Typ
Max
Unit
-
32.768
1000
kHz
VLSEH
OSC32_IN input pin high level voltage
0.7 VDDIOx
-
VDDIOx
VLSEL
OSC32_IN input pin low level voltage
VSS
-
0.3 VDDIOx
450
-
-
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
tr(LSE)
tf(LSE)
V
ns
OSC32_IN rise or fall time
-
-
50
1. Guaranteed by design, not tested in production.
Figure 15. Low-speed external clock source AC timing diagram
WZ/6(+
9/6(+
9/6(/
WU/6(
WI/6(
WZ/6(/
W
7/6(
069
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86
Electrical characteristics
STM32F031x4 STM32F031x6
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 33. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 33. HSE oscillator characteristics
Symbol
fOSC_IN
RF
Conditions(1)
Min(2)
Typ
Max(2)
Unit
Oscillator frequency
-
4
8
32
MHz
Feedback resistor
-
-
200
-
k
Parameter
(3)
During startup
IDD
gm
tSU(HSE)(4)
HSE current consumption
Oscillator transconductance
Startup time
-
8.5
VDD = 3.3 V,
Rm = 30 ,
CL = 10 pF@8 MHz
-
0.4
-
VDD = 3.3 V,
Rm = 45 ,
CL = 10 pF@8 MHz
-
0.5
-
VDD = 3.3 V,
Rm = 30 ,
CL = 5 pF@32 MHz
-
0.8
-
VDD = 3.3 V,
Rm = 30 ,
CL = 10 pF@32 MHz
-
1
-
VDD = 3.3 V,
Rm = 30 ,
CL = 20 pF@32 MHz
-
1.5
-
Startup
10
-
-
mA/V
VDD is stabilized
-
2
-
ms
mA
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note:
58/113
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
DocID025743 Rev 3
STM32F031x4 STM32F031x6
Electrical characteristics
Figure 16. Typical application with an 8 MHz crystal
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26&B,1
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5(;7 I+6(
5)
%LDV
FRQWUROOHG
JDLQ
26&B287
069
1. REXT value depends on the crystal characteristics.
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Electrical characteristics
STM32F031x4 STM32F031x6
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 34. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 34. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
IDD
gm
Parameter
Conditions(1)
Min(2)
Typ
Max(2) Unit
LSEDRV[1:0]=00
lower driving capability
-
0.5
0.9
LSEDRV[1:0]= 01
medium low driving capability
-
-
1
LSE current consumption
Oscillator
transconductance
tSU(LSE)(3) Startup time
µA
LSEDRV[1:0] = 10
medium high driving capability
-
-
1.3
LSEDRV[1:0]=11
higher driving capability
-
-
1.6
LSEDRV[1:0]=00
lower driving capability
5
-
-
LSEDRV[1:0]= 01
medium low driving capability
8
-
µA/V
LSEDRV[1:0] = 10
medium high driving capability
15
-
-
LSEDRV[1:0]=11
higher driving capability
25
-
-
VDDIOx is stabilized
-
2
-
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note:
60/113
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
DocID025743 Rev 3
s
STM32F031x4 STM32F031x6
Electrical characteristics
Figure 17. Typical application with a 32.768 kHz crystal
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FDSDFLWRUV
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26&B,1
I+6(
'ULYH
SURJUDPPDEOH
DPSOLILHU
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&/
069
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
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86
Electrical characteristics
6.3.8
STM32F031x4 STM32F031x6
Internal clock source characteristics
The parameters given in Table 35 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 18: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI) RC oscillator
Table 35. HSI oscillator characteristics(1)
Symbol
Parameter
fHSI
TRIM
DuCy(HSI)
Conditions
Min
Typ
Max
Unit
Frequency
-
-
8
-
MHz
HSI user trimming step
-
-
-
1(2)
%
-
45(2)
%
-
55(2)
TA = -40 to 105°C
-2.8(3)
-
3.8(3)
TA = -10 to 85°C
-1.9(3)
-
2.3(3)
TA = 0 to 85°C
-1.9(3)
-
2(3)
TA = 0 to 70°C
-1.3(3)
-
2(3)
TA = 0 to 55°C
-1(3)
-
2(3)
TA = 25°C
-1(4)
-
1(4)
HSI oscillator startup time
-
1(2)
-
2(2)
µs
HSI oscillator power
consumption
-
-
80
100(2)
µA
Duty cycle
Accuracy of the HSI
oscillator
ACCHSI
tsu(HSI)
IDDA(HSI)
%
1. VDDA = 3.3 V, TA = -40 to 105°C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
4. Factory calibrated, parts not soldered.
Figure 18. HSI oscillator accuracy characterization results for soldered parts
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069
62/113
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Electrical characteristics
High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)
Table 36. HSI14 oscillator characteristics(1)
Symbol
fHSI14
TRIM
Parameter
Conditions
Min
Typ
-
-
14
Frequency
HSI14 user-trimming step
DuCy(HSI14) Duty cycle
-
-
-
(2)
45
Accuracy of the HSI14
oscillator (factory calibrated)
TA = –10 to 85 °C
TA = 25 °C
tsu(HSI14)
IDDA(HSI14)
-
MHz
(2)
-
%
1
55
(2)
%
(3)
%
(3)
-
5.1
–3.2(3)
-
3.1(3)
%
–2.5
-
2.3
(3)
%
–1
(3)
TA = 0 to 70 °C
Unit
-
TA = –40 to 105 °C –4.2
ACCHSI14
Max
HSI14 oscillator startup time
-
1(2)
HSI14 oscillator power
consumption
-
-
-
1
%
-
2(2)
µs
100
150(2)
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Figure 19. HSI14 oscillator accuracy characterization results
-!8
-).
4; #=
!
-36
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Electrical characteristics
STM32F031x4 STM32F031x6
Low-speed internal (LSI) RC oscillator
Table 37. LSI oscillator characteristics(1)
Symbol
fLSI
tsu(LSI)
Parameter
Min
Typ
Max
Unit
30
40
50
kHz
LSI oscillator startup time
-
-
85
µs
LSI oscillator power consumption
-
0.75
1.2
µA
Frequency
(2)
IDDA(LSI)(2)
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
6.3.9
PLL characteristics
The parameters given in Table 38 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 18: General operating
conditions.
Table 38. PLL characteristics
Value
Symbol
Parameter
Typ
Max
1(2)
8.0
24(2)
MHz
PLL input clock duty cycle
(2)
40
-
60(2)
%
PLL multiplier output clock
16(2)
-
48
MHz
PLL lock time
-
-
200(2)
µs
Cycle-to-cycle jitter
-
-
300(2)
ps
PLL input clock(1)
fPLL_IN
fPLL_OUT
tLOCK
JitterPLL
Unit
Min
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT.
2. Guaranteed by design, not tested in production.
64/113
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STM32F031x4 STM32F031x6
6.3.10
Electrical characteristics
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 39. Flash memory characteristics
Min
Typ
Max(1)
Unit
16-bit programming time TA–40 to +105 °C
40
53.5
60
µs
Page (1 KB) erase time
TA –40 to +105 °C
20
-
40
ms
tME
Mass erase time
TA –40 to +105 °C
20
-
40
ms
Write mode
-
-
10
mA
IDD
Supply current
Erase mode
-
-
12
mA
Symbol
tprog
tERASE
Parameter
Conditions
1. Guaranteed by design, not tested in production.
Table 40. Flash memory endurance and data retention
Symbol
NEND
Parameter
Endurance
Conditions
TA = –40 to +105 °C
1 kcycle
tRET
Data retention
(2)
at TA = 85 °C
1 kcycle(2) at TA = 105 °C
(2)
10 kcycle
at TA = 55 °C
Min(1)
Unit
10
kcycle
30
10
Year
20
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
6.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 41. They are based on the EMS levels and classes
defined in application note AN1709.
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Electrical characteristics
STM32F031x4 STM32F031x6
Table 41. EMS characteristics
Symbol
Parameter
Level/
Class
Conditions
VFESD
VDD 3.3 V, LQFP48, TA +25 °C,
Voltage limits to be applied on any I/O pin
fHCLK 48 MHz,
to induce a functional disturbance
conforming to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD3.3 V, LQFP48, TA +25°C,
fHCLK 48 MHz,
conforming to IEC 61000-4-4
4B
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 42. EMI characteristics
Symbol Parameter
SEMI
66/113
Conditions
Monitored
frequency band
0.1 to 30 MHz
VDD 3.6 V, TA 25 °C,
30 to 130 MHz
LQFP48 package
Peak level
compliant with
130 MHz to 1 GHz
IEC 61967-2
EMI Level
DocID025743 Rev 3
Max vs. [fHSE/fHCLK]
Unit
8/48 MHz
-11
21
dBµV
21
4
-
STM32F031x4 STM32F031x6
6.3.12
Electrical characteristics
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 43. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Packages
Class
Maximum
value(1)
Unit
VESD(HBM)
Electrostatic discharge voltage TA +25 °C, conforming
(human body model)
to JESD22-A114
All
2
2000
V
VESD(CDM)
Electrostatic discharge voltage TA +25 °C, conforming
(charge device model)
to ANSI/ESD STM5.3.1
All
C4
500
V
1. Data based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 44. Electrical sensitivities
Symbol
LU
6.3.13
Parameter
Static latch-up class
Conditions
TA +105 °C conforming to JESD78A
Class
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
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Electrical characteristics
STM32F031x4 STM32F031x6
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 45.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 45. I/O current injection susceptibility
Functional
susceptibility
Symbol
Description
Unit
Negative Positive
injection injection
IINJ
6.3.14
Injected current on BOOT0
–0
NA
Injected current on all FT and FTf pins
–5
NA
Injected current on all TTa, TC and RESET pins
–5
+5
mA
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under the conditions summarized in Table 18: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant (except BOOT0).
Table 46. I/O static characteristics
Symbol
VIL
VIH
Parameter
Low level input
voltage
High level input
voltage
Conditions
Min
Typ
Max
TC and TTa I/O
-
-
0.3 VDDIOx+0.07(1)
FT and FTf I/O
-
-
0.475 VDDIOx–0.2(1)
BOOT0
-
-
0.3 VDDIOx–0.3(1)
All I/Os except
BOOT0 pin
-
-
0.3 VDDIOx
TC and TTa I/O
0.445 VDDIOx+0.398(1)
-
-
FT and FTf I/O
0.5 VDDIOx+0.2(1)
-
-
+0.95(1)
-
-
-
-
BOOT0
All I/Os except
BOOT0 pin
68/113
0.2 VDDIOx
0.7 VDDIOx
DocID025743 Rev 3
Unit
V
V
STM32F031x4 STM32F031x6
Electrical characteristics
Table 46. I/O static characteristics (continued)
Symbol
Vhys
Ilkg
RPU
Parameter
Schmitt trigger
hysteresis
Input leakage
current(2)
Weak pull-up
equivalent resistor
(4)
RPD
Weak pull-down
equivalent
resistor(4)
CIO
I/O pin capacitance
Conditions
Min
Typ
(1)
Max
Unit
TC and TTa I/O
-
200
-
FT and FTf I/O
-
100(1)
-
BOOT0
-
(1)
300
-
TC, FT and FTf I/O
TTa in digital mode
VSS VIN VDDIOx
-
-
0.1
TTa in digital mode
VDDIOx VIN VDDA
-
-
1
TTa in analog mode
VSS VIN VDDA
-
-
0.2
FT and FTf I/O (3)
VDDIOx VIN 5 V
-
-
10
VIN VSS
25
40
55
k
VIN VDDIOx
25
40
55
k
-
5
-
pF
-
mV
µA
1. Data based on design simulation only. Not tested in production.
2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 45:
I/O current injection susceptibility.
3. To sustain a voltage higher than VDDIOx + 0.3 V, the internal pull-up/pull-down resistors must be disabled.
4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
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Electrical characteristics
STM32F031x4 STM32F031x6
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 20 for standard I/Os, and in Figure 21 for
5 V tolerant I/Os. The following curves are design simulation results, not tested in
production.
Figure 20. TC and TTa I/O input characteristics
3
VIN (V)
2.5
TESTED RANGE
TTL standard requirement
2
1.5
UNDEFINED INPUT RANGE
1
TTL standard requirement
0.5
TESTED RANGE
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VDDIOx
(V)
MS32130V3
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Electrical characteristics
Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics
3
VIN (V)
2.5
TESTED RANGE
TTL standard requirement
2
1.5
1
TTL standard requirement
0.5
TESTED RANGE
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VDDIOx (V)
MS32131V3
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Electrical characteristics
STM32F031x4 STM32F031x6
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 15: Voltage characteristics).
The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see
Table 15: Voltage characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 18: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or
TC unless otherwise specified).
Table 47. Output voltage characteristics(1)
Symbol
Parameter
VOL
Output low level voltage for an I/O pin
VOH
Output high level voltage for an I/O pin
VOL
Output low level voltage for an I/O pin
VOH
Output high level voltage for an I/O pin
VOL(3)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOL(3)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOLFm+(3)
Output low level voltage for an FTf I/O pin in
Fm+ mode
Conditions
Min
Max
CMOS port(2)
|IIO| = 8 mA
VDDIOx 2.7 V
-
0.4
VDDIOx–0.4
-
-
0.4
2.4
-
-
1.3
VDDIOx–1.3
-
-
0.4
VDDIOx–0.4
-
|IIO| = 20 mA
VDDIOx 2.7 V
-
0.4
V
|IIO| = 10 mA
-
0.4
V
TTL port(2)
|IIO| = 8 mA
VDDIOx 2.7 V
|IIO| = 20 mA
VDDIOx 2.7 V
|IIO| = 6 mA
Unit
V
V
V
V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 15:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Data based on characterization results. Not tested in production.
72/113
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Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 22 and
Table 48, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 18: General
operating conditions.
Table 48. I/O AC characteristics(1)(2)
OSPEEDRy
[1:0]
value(1)
Symbol
Parameter
Conditions
Min
Max
Unit
-
2
MHz
-
125
-
125
-
10
-
25
-
25
CL = 30 pF, VDDIOx 2.7 V
-
50
CL = 50 pF, VDDIOx 2.7 V
-
30
CL = 50 pF, VDDIOx 2.7 V
-
20
CL = 30 pF, VDDIOx 2.7 V
-
5
CL = 50 pF, VDDIOx 2.7 V
-
8
CL = 50 pF, VDDIOx 2.7 V
-
12
CL = 30 pF, VDDIOx 2.7 V
-
5
CL = 50 pF, VDDIOx 2.7 V
-
8
CL = 50 pF, VDDIOx 2.7 V
-
12
-
2
-
12
-
34
10
-
fmax(IO)out Maximum frequency(3)
x0
tf(IO)out
Output fall time
tr(IO)out
Output rise time
CL = 50 pF
fmax(IO)out Maximum frequency(3)
01
tf(IO)out
Output fall time
tr(IO)out
Output rise time
fmax(IO)out Maximum
11
tf(IO)out
tr(IO)out
Fm+
configuration
(4)
frequency(3)
Output fall time
Output rise time
fmax(IO)out Maximum
CL = 50 pF
frequency(3)
tf(IO)out
Output fall time
tr(IO)out
Output rise time
tEXTIpw
Pulse width of external
signals detected by
the EXTI controller
CL = 50 pF
ns
MHz
ns
MHz
ns
MHz
ns
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference
manual for a description of GPIO Port configuration register.
2. Guaranteed by design, not tested in production.
3. The maximum frequency is defined in Figure 22.
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference
manual RM0091 for a detailed description of Fm+ I/O configuration.
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Figure 22. I/O AC characteristics definition
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6.3.15
NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 18: General operating conditions.
Table 49. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)
NRST input low level voltage
-
-
-
0.3 VDD+0.07(1)
VIH(NRST)
NRST input high level voltage
-
0.445 VDD+0.398(1)
-
-
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
-
-
200
-
mV
V
RPU
Weak pull-up equivalent
resistor(2)
VIN VSS
25
40
55
k
VF(NRST)
NRST input filtered pulse
-
-
-
100(1)
ns
2.7 < VDD < 3.6
300(3)
-
-
2.0 < VDD < 3.6
(3)
-
-
VNF(NRST) NRST input not filtered pulse
500
ns
1. Data based on design simulation only. Not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
3. Data based on design simulation only. Not tested in production.
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Figure 23. Recommended NRST pin protection
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1. The external capacitor protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 49: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
6.3.16
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 50 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 18: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
Table 50. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Analog supply voltage for
ADC ON
-
2.4
-
3.6
V
VDD = VDDA = 3.3 V
-
0.9
-
mA
IDDA (ADC)
Current consumption of
the ADC(1)
fADC
ADC clock frequency
-
0.6
-
14
MHz
fS(2)
Sampling rate
-
0.05
-
1
MHz
fADC = 14 MHz
-
-
823
kHz
-
-
-
17
1/fADC
fTRIG(2)
External trigger frequency
VAIN
Conversion voltage range
-
0
-
VDDA
V
RAIN(2)
External input impedance
See Equation 1 and
Table 51 for details
-
-
50
k
RADC(2)
Sampling switch
resistance
-
-
-
1
k
CADC(2)
Internal sample and hold
capacitor
-
-
-
8
pF
tCAL(2)
Calibration time
fADC = 14 MHz
5.9
µs
-
83
1/fADC
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Electrical characteristics
STM32F031x4 STM32F031x6
Table 50. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
1.5 ADC
cycles + 2
fPCLK cycles
-
1.5 ADC
cycles + 3
fPCLK cycles
ADC clock = PCLK/2
-
4.5
-
fPCLK
cycle
ADC clock = PCLK/4
-
8.5
-
fPCLK
cycle
ADC clock = HSI14
WLATENCY(2)
tlatr
(2)
ADC_DR register write
latency
fADC = fPCLK/2 = 14 MHz
0.196
µs
fADC = fPCLK/2
5.5
1/fPCLK
0.219
µs
10.5
1/fPCLK
Trigger conversion latency fADC = fPCLK/4 = 12 MHz
fADC = fPCLK/4
JitterADC
fADC = fHSI14 = 14 MHz
0.188
-
0.259
µs
fADC = fHSI14
-
1
-
1/fHSI14
fADC = 14 MHz
0.107
-
17.1
µs
-
1.5
-
239.5
1/fADC
-
-
-
1
Conver
sion
cycle
fADC = 14 MHz
1
-
18
µs
ADC jitter on trigger
conversion
tS(2)
Sampling time
tSTAB(2)
Power-up time
tCONV(2)
Total conversion time
(including sampling time)
Unit
-
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA
on IDD should be taken into account.
2. Guaranteed by design, not tested in production.
Equation 1: RAIN max formula
TS
- – R ADC
R AIN ------------------------------------------------------------N+2
f ADC C ADC ln 2
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 51. RAIN max for fADC = 14 MHz
76/113
Ts (cycles)
tS (µs)
RAIN max (k)(1)
1.5
0.11
0.4
7.5
0.54
5.9
13.5
0.96
11.4
28.5
2.04
25.2
41.5
2.96
37.2
DocID025743 Rev 3
STM32F031x4 STM32F031x6
Electrical characteristics
Table 51. RAIN max for fADC = 14 MHz (continued)
Ts (cycles)
tS (µs)
RAIN max (k)(1)
55.5
3.96
50
71.5
5.11
NA
239.5
17.1
NA
1. Guaranteed by design, not tested in production.
Table 52. ADC accuracy(1)(2)(3)
Symbol
Parameter
Test conditions
Typ
Max(4)
±1.3
±2
±1
±1.5
±0.5
±1.5
±0.7
±1
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
±0.8
±1.5
ET
Total unadjusted error
±3.3
±4
EO
Offset error
±1.9
±2.8
EG
Gain error
±2.8
±3
ED
Differential linearity error
±0.7
±1.3
EL
Integral linearity error
±1.2
±1.7
ET
Total unadjusted error
±3.3
±4
±1.9
±2.8
±2.8
±3
±0.7
±1.3
±1.2
±1.7
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 k
VDDA = 3 V to 3.6 V
TA = 25 °C
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 k
VDDA = 2.7 V to 3.6 V
TA = 40 to 105 °C
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 k
VDDA = 2.4 V to 3.6 V
TA = 25 °C
Unit
LSB
LSB
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
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Figure 24. ADC accuracy characteristics
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Figure 25. Typical connection diagram using the ADC
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1. Refer to Table 50: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 12: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
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6.3.17
Electrical characteristics
Temperature sensor characteristics
Table 53. TS characteristics
Symbol
Parameter
TL(1)
Avg_Slope
VSENSE linearity with temperature
(1)
V30
Average slope
Voltage at 30 °C (5 °C)
(2)
Min
Typ
Max
Unit
-
1
2
°C
4.0
4.3
4.6
mV/°C
1.34
1.43
1.52
V
tSTART(1)
ADC_IN16 buffer startup time
-
-
10
µs
tS_temp(1)
ADC sampling time when reading the
temperature
4
-
-
µs
1. Guaranteed by design, not tested in production.
2. Measured at VDDA = 3.3 V 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byteRefer to Table 3:
Temperature sensor calibration values.
6.3.18
VBAT monitoring characteristics
Table 54. VBAT monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
k
R
Resistor bridge for VBAT
-
2 x 50
-
Q
Ratio on VBAT measurement
-
2
-
Error on Q
–1
-
+1
%
ADC sampling time when reading the VBAT
4
-
-
µs
Er(1)
tS_vbat(1)
1. Guaranteed by design, not tested in production.
6.3.19
Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 55. TIMx characteristics
Symbol
Parameter
tres(TIM)
Timer resolution time
fEXT
Timer external clock
frequency on CH1 to
CH4
ResTIM
tCOUNTER
Conditions
Min
Max
Unit
-
1
-
tTIMxCLK
fTIMxCLK = 48 MHz
20.8
-
ns
0
fTIMxCLK/2
MHz
fTIMxCLK = 48 MHz
0
24
MHz
TIMx (except TIM2)
-
16
TIM2
-
32
-
1
65536
tTIMxCLK
fTIMxCLK = 48 MHz
0.0208
1365
µs
-
Timer resolution
bit
16-bit counter clock
period
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Electrical characteristics
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Table 55. TIMx characteristics (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
tMAX_COUNT
Maximum possible count
with 32-bit counter
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 48 MHz
-
89.48
s
Table 56. IWDG min/max timeout period at 40 kHz (LSI)(1)
Prescaler divider
PR[2:0] bits
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
/4
0
0.1
409.6
/8
1
0.2
819.2
/16
2
0.4
1638.4
/32
3
0.8
3276.8
/64
4
1.6
6553.6
/128
5
3.2
13107.2
/256
6 or 7
6.4
26214.4
Unit
ms
1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Table 57. WWDG min/max timeout value at 48 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
1
0
0.0853
5.4613
2
1
0.1706
10.9226
4
2
0.3413
21.8453
8
3
0.6826
43.6906
Unit
ms
6.3.20
Communication interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
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Electrical characteristics
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 58. I2C analog filter characteristics(1)
Symbol
Parameter
Min
Max
Unit
tAF
Maximum pulse width of spikes that
are suppressed by the analog filter
50(2)
260(3)
ns
1. Guaranteed by design, not tested in production.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
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SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 59 for SPI or in Table 60 for I2S
are derived from tests performed under the ambient temperature, fPCLKx frequency and
supply voltage conditions summarized in Table 18: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 59. SPI characteristics(1)
Symbol
fSCK
1/tc(SCK)
Parameter
Conditions
Min
Max
Master mode
-
18
Slave mode
-
18
-
6
SPI clock frequency
MHz
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 15 pF
tsu(NSS)
NSS setup time
Slave mode
4Tpclk
-
th(NSS)
NSS hold time
Slave mode
2Tpclk + 10
-
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
Tpclk/2 -2
Tpclk/2 + 1
Master mode
4
-
Slave mode
5
-
Master mode
4
-
Slave mode
5
-
Data output access time
Slave mode, fPCLK = 20 MHz
0
3Tpclk
Data output disable time
Slave mode
0
18
tv(SO)
Data output valid time
Slave mode (after enable edge)
-
22.5
tv(MO)
Data output valid time
Master mode (after enable edge)
-
6
Slave mode (after enable edge)
11.5
-
Master mode (after enable edge)
2
-
Slave mode
25
75
tw(SCKH)
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
tdis(SO)
(3)
th(SO)
Data input hold time
ns
Data output hold time
th(MO)
DuCy(SCK)
ns
Data input setup time
th(SI)
ta(SO)(2)
Unit
SPI slave input clock
duty cycle
%
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
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Electrical characteristics
Figure 26. SPI timing diagram - slave mode and CPHA = 0
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1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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Electrical characteristics
STM32F031x4 STM32F031x6
Figure 28. SPI timing diagram - master mode
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1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
Table 60. I2S characteristics(1)
Symbol
fCK
1/tc(CK)
Parameter
I2S
clock frequency
tr(CK)
I2S clock rise time
tf(CK)
I2S clock fall time
Conditions
Min
Max
1.597
1.601
Slave mode
0
6.5
Capacitive load CL = 15 pF
-
10
-
12
306
-
312
-
Master mode (data: 16 bits, Audio
frequency = 48 kHz)
Master fPCLK= 16 MHz, audio
frequency = 48 kHz
MHz
tw(CKH)
I2S clock high time
tw(CKL)
I2S clock low time
tv(WS)
WS valid time
Master mode
2
-
th(WS)
WS hold time
Master mode
2
-
tsu(WS)
WS setup time
Slave mode
7
-
th(WS)
WS hold time
Slave mode
0
-
I2S slave input clock duty
cycle
Slave mode
25
75
DuCy(SCK)
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Unit
ns
%
STM32F031x4 STM32F031x6
Electrical characteristics
Table 60. I2S characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Max
tsu(SD_MR)
Data input setup time
Master receiver
6
-
tsu(SD_SR)
Data input setup time
Slave receiver
2
-
Master receiver
4
-
Slave receiver
0.5
-
-
20
13
-
-
4
0
-
th(SD_MR)
th(SD_SR)
tv(SD_ST)
(2)
(2)
(2)
Unit
Data input hold time
ns
Data output valid time
th(SD_ST)
Data output hold time
tv(SD_MT)(2)
Data output valid time
th(SD_MT)
Data output hold time
Slave transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Master transmitter (after enable edge)
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK = 8 MHz, then TPCLK = 1/fPLCLK = 125 ns.
Figure 29. I2S slave timing diagram (Philips protocol)
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1. Measurement points are done at CMOS levels: 0.3 × VDDIOx and 0.7 × VDDIOx.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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Electrical characteristics
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Figure 30. I2S master timing diagram (Philips protocol)
TF#+
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1. Data based on characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
LQFP48 package information
Figure 31. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline
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7.1
E
"?-%?6
1. Drawing is not to scale.
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Package information
STM32F031x4 STM32F031x6
Table 61. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.500
-
-
0.2165
-
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.500
-
-
0.2165
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
88/113
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STM32F031x4 STM32F031x6
Package information
Figure 32. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint
AID
1. Dimensions are expressed in millimeters.
DocID025743 Rev 3
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Package information
STM32F031x4 STM32F031x6
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 33. LQFP48 marking example (package top view)
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
90/113
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LQFP32 package information
Figure 34. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline
C
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E
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1. Drawing is not to scale.
DocID025743 Rev 3
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109
Package information
STM32F031x4 STM32F031x6
Table 62. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.300
0.370
0.450
0.0118
0.0146
0.0177
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.600
-
-
0.2205
-
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.600
-
-
0.2205
-
e
-
0.800
-
-
0.0315
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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STM32F031x4 STM32F031x6
Package information
Figure 35. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
recommended footprint
6?&0?6
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 36. LQFP32 marking example (package top view)
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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Package information
7.3
STM32F031x4 STM32F031x6
UFQFPN32 package information
Figure 37. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline
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$
H
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$
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E
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1. Drawing is not to scale.
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STM32F031x4 STM32F031x6
Package information
Table 63. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.500
0.550
0.600
0.0197
0.0217
0.0236
A1
0.000
0.020
0.050
0.0000
0.0008
0.0020
A3
-
0.152
-
-
0.0060
-
b
0.180
0.230
0.280
0.0071
0.0091
0.0110
D
4.900
5.000
5.100
0.1929
0.1969
0.2008
D1
3.400
3.500
3.600
0.1339
0.1378
0.1417
D2
3.400
3.500
3.600
0.1339
0.1378
0.1417
E
4.900
5.000
5.100
0.1929
0.1969
0.2008
E1
3.400
3.500
3.600
0.1339
0.1378
0.1417
E2
3.400
3.500
3.600
0.1339
0.1378
0.1417
e
-
0.500
-
-
0.0197
-
L
0.300
0.400
0.500
0.0118
0.0157
0.0197
ddd
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 38. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package recommended footprint
$%B)3B9
1. Dimensions are expressed in millimeters.
DocID025743 Rev 3
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109
Package information
STM32F031x4 STM32F031x6
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 39. UFQFPN32 marking example (package top view)
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
96/113
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7.4
Package information
UFQFPN28 package information
Figure 40. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
'HWDLO<
'
(
'
'
(
'HWDLO=
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1. Drawing is not to scale.
Table 64. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data(1)
millimeters
inches
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.500
0.550
0.600
0.0197
0.0217
0.0236
A1
-
0.000
0.050
-
0.0000
0.0020
D
3.900
4.000
4.100
0.1535
0.1575
0.1614
D1
2.900
3.000
3.100
0.1142
0.1181
0.1220
E
3.900
4.000
4.100
0.1535
0.1575
0.1614
E1
2.900
3.000
3.100
0.1142
0.1181
0.1220
L
0.300
0.400
0.500
0.0118
0.0157
0.0197
L1
0.250
0.350
0.450
0.0098
0.0138
0.0177
T
-
0.152
-
-
0.0060
-
b
0.200
0.250
0.300
0.0079
0.0098
0.0118
e
-
0.500
-
-
0.0197
-
DocID025743 Rev 3
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109
Package information
STM32F031x4 STM32F031x6
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 41. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint
1. Dimensions are expressed in millimeters.
98/113
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STM32F031x4 STM32F031x6
Package information
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 42. UFQFPN28 marking example (package top view)
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID025743 Rev 3
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109
Package information
STM32F031x4 STM32F031x6
7.5
WLCSP25 package information
7.6
WLCSP25 package information
Figure 43. WLCSP25 - 25-ball, 2.423 x 2.325 mm, 0.4 mm pitch wafer level chip scale
package outline
H
EEE =
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:/&63B$1B0(B9
1. Drawing is not to scale.
Table 65. WLCSP25 - 25-ball, 2.423 x 2.325 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.525
0.555
0.585
0.0207
0.0219
0.0230
A1
-
0.175
-
-
0.0069
-
A2
-
0.380
-
-
0.0150
-
(2)
-
0.025
-
-
0.0010
-
b(3) (4)
0.220
0.250
0.280
0.0087
0.0098
0.0110
D
2.388
2.423
2.458
0.0940
0.0954
0.0968
E
2.29
2.325
2.36
0.0902
0.0915
0.0929
e
-
0.400
-
-
0.0157
-
e1
-
1.600
-
-
0.0630
-
A3
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STM32F031x4 STM32F031x6
Package information
Table 65. WLCSP25 - 25-ball, 2.423 x 2.325 mm, 0.4 mm pitch wafer level chip scale
package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
e2
-
1.600
-
-
0.0630
-
F
-
0.4115
-
-
0.0162
-
G
-
0.3625
-
-
0.0143
-
aaa
-
0.100
-
-
0.0039
-
bbb
-
0.100
-
-
0.0039
-
ccc
-
0.100
-
-
0.0039
-
ddd
-
0.050
-
-
0.0020
-
eee
-
0.050
-
-
0.0020
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
4. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
Figure 44. WLCSP25 - 25-ball, 2.133 x 2.070 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint
'SDG
'VP
:/&63B$1B)3B9
Table 66. WLCSP25 recommended PCB design rules (0.4 mm pitch)
Dimension
Recommended values
Pitch
0.4 mm
Dpad
0.225 mm
Dsm
0.290 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening
0.250 mm
Stencil thickness
0.100 mm
DocID025743 Rev 3
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109
Package information
STM32F031x4 STM32F031x6
Device marking
‘The following figure gives an example of topside marking orientation versus ball A1
identifier location.
Figure 45. WLCSP25 marking example (package top view)
'RW
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88
3
069
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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7.7
Package information
TSSOP20 package information
Figure 46.TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline
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C
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1. Drawing is not to scale.
Table 67. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
1.200
-
-
0.0472
A1
0.050
-
0.150
0.0020
-
0.0059
A2
0.800
1.000
1.050
0.0315
0.0394
0.0413
b
0.190
-
0.300
0.0075
-
0.0118
c
0.090
-
0.200
0.0035
-
0.0079
(2)
6.400
6.500
6.600
0.2520
0.2559
0.2598
E
6.200
6.400
6.600
0.2441
0.2520
0.2598
E1(3)
4.300
4.400
4.500
0.1693
0.1732
0.1772
e
-
0.650
-
-
0.0256
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
D
DocID025743 Rev 3
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109
Package information
STM32F031x4 STM32F031x6
Table 67. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data (continued)
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
k
0°
-
8°
0°
-
8°
aaa
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25mm per side.
Figure 47. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint
1. Dimensions are expressed in millimeters.
104/113
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Package information
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 48. TSSOP20 marking example (package top view)
6WDQGDUG67ORJR
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88
069
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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109
Package information
7.8
STM32F031x4 STM32F031x6
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 18: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x JA)
Where:
TA max is the maximum ambient temperature in °C,
JA is the package junction-to-ambient thermal resistance, in C/W,
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = (VOL × IOL) + ((VDDIOx – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 68. Package thermal characteristics
Symbol
JA
7.8.1
Parameter
Value
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm
55
Thermal resistance junction-ambient
UFQFPN32 - 5 × 5 mm
38
Thermal resistance junction-ambient
LQFP32 - 7 × 7 mm
56
Unit
°C/W
Thermal resistance junction-ambient
UFQFPN28 - 4 × 4 mm
118
Thermal resistance junction-ambient
WLCSP25 - 2.13 x 2.07 mm
74
Thermal resistance junction-ambient
TSSOP20
110
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
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STM32F031x4 STM32F031x6
7.8.2
Package information
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Part numbering.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F031x4/x6 at maximum dissipation, it is
useful to calculate the exact power consumption and junction temperature to determine
which temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 80 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in Table 68 TJmax is calculated as follows:
–
For LQFP48, 55 °C/W
TJmax = 80 °C + (55°C/W × 447 mW) = 80 °C + 24.585 °C = 104.585 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Table 18:
General operating conditions.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Part numbering).
Note:
With this given PDmax we can find the TAmax allowed for a given device temperature range (order code suffix
6 or 7).
Suffix 6: TAmax = TJmax - (55°C/W × 447 mW) = 105-24.585 = 80.415 °C
Suffix 7: TAmax = TJmax - (55°C/W × 447 mW) = 125-24.585 = 100.415 °C
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
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Package information
STM32F031x4 STM32F031x6
Assuming the following application conditions:
Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
Using the values obtained in Table 68 TJmax is calculated as follows:
–
For LQFP48, 55 °C/W
TJmax = 100 °C + (55 °C/W × 134 mW) = 100 °C + 7.37 °C = 107.37 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Part numbering) unless we reduce the power dissipation in order to be able to
use suffix 6 parts.
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8
Part numbering
Part numbering
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
Table 69. Ordering information scheme
Example:
STM32
F
031 G
6
T
6
x
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
031 = STM32F031xx
Pin count
F = 20 pins
E = 25 pins
G = 28 pins
K = 32 pins
C = 48 pins
Code size
4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory
Package
P = TSSOP
U = UFQFPN
T = LQFP
Y = WLCSP
Temperature range
6 = –40 °C to +85 °C
7 = –40 °C to +105 °C
Options
xxx = programmed parts
TR = tape and reel
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Revision history
Table 70. Document revision history
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Date
Revision
13-Jan-2014
1
Changes
Initial release.
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Revision history
Table 70. Document revision history (continued)
Date
11-Jul-2014
Revision
Changes
2
Changed the document status to Datasheet - production
data.
Updated the following:
– Table: STM32F038x4/6 family device features and
peripheral counts,
– Figure: Clock tree,
– Figure: Power supply scheme,
– Table: Peripheral current consumption.
Replaced Table Typical current consumption in Run
mode, code with data processing running from Flash
and Table Typical current consumption in Sleep mode,
code running from Flash or RAM with Table: Typical
current consumption, code executing from Flash,
running from HSE 8 MHz crystal.
Added the LQFP32 package: updates in Section:
Description, Section: Pinouts and pin description and
Section: Package information.
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Table 70. Document revision history (continued)
Date
28-Aug-2015
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Revision
Changes
3
Updated:
– Figure 9: STM32F031x4/x6 memory map,
– AF1 alternate functions for PA0, PA1, PA2, PA3 and
PA4 in Table 12: Alternate functions selected through
GPIOA_AFR registers for port A,
– the footnote for VIN max value in Table 15: Voltage
characteristics,
– the footnote for max VIN in Table 18: General
operating conditions
– Table 22: Embedded internal reference voltage with
the addition of tSTART parameter,
– tSTAB characteristics in Table 50: ADC characteristics,
– Table 53: TS characteristics: removed the min. value
for tSTART parameter,
– the typical value for R parameter in Table 54: VBAT
monitoring characteristics,
– the structure of Section 7: Package information.
Added:
– Figure 33: LQFP48 marking example (package top
view),
– Figure 36: LQFP32 marking example (package top
view),
– Figure 39: UFQFPN32 marking example (package top
view),
– Figure 42: UFQFPN28 marking example (package top
view),
– Figure 48: TSSOP20 marking example (package top
view).
Added WLCSP25 package, updates in the following:
– Table 1: Device summary,
– Section 2: Description,
– Table 2: STM32F031x4/x6 family device features and
peripheral counts,
– Section 4: Pinouts and pin description: addition of
Figure 7: WLCSP25 25-ball package ballout (bump
side) and update of Table 11: Pin definitions,
– Table 18: General operating conditions,
– Section 7: Package information with the addition of
Section 7.5: WLCSP25 package information,
– Table 68: Package thermal characteristics.
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