VND5E160AJ-E - STMicroelectronics

VND5E160AJ-E
Double channel high side driver with analog current sense
for automotive applications
Features
Max transient supply voltage
VCC
41 V
Operating voltage range
VCC
4.5 to 28V
Max On-state resistance (per ch.)
RON
160 m
Current limitation (typ.)
ILIMH
10 A
Off state supply current
IS
2 µA(1)
PowerSSO-12
– Reverse battery protected (see Application
schematic)
– Electrostatic discharge protection
1. Typical value with all loads connected.
■
General
– Inrush current active management by
power limitation
– Very low stand-by current
– 3.0 V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
european directive
– Very low current sense leakage
■ Diagnostic functions
– Proportional load current sense
– High current sense precision for wide
currents range
– Current sense disable
– Off state openload detection
– Output short to VCC detection
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
■ Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Over-temperature shutdown with
autorestart (thermal shutdown)
September 2013
Application
■
All types of resistive, inductive and capacitive
loads
■
Suitable as LED driver
Description
The VND5E160AJ-E is a single channel high-side
driver manufactured in the ST proprietary
VIPower M0-5 technology and housed in the tiny
PowerSSO-12 package. The VND5E160AJ-E is
designed to drive 12V automotive grounded loads
delivering protection, diagnostics and easy 3V
and 5V CMOS compatible interface with any
microcontroller.
The device integrates advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, over-temperature shut-off with
auto-restart and over-voltage active clamp. A
dedicated analog current sense pin is associated
with every output channel in order to provide
Ehnanced diagnostic functions including fast
detection of overload and short-circuit to ground
through power limitation indication, overtemperature indication, short-circuit to Vcc
diagnosis and ON & OFF state open load
detection. The current sensing and diagnostic
feedback of the whole device can be disabled by
pulling the CS_DIS pin high to allow sharing of
the external sense resistor with other similar
devices.
Rev 3
1/37
www.st.com
37
Contents
VND5E160AJ-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 24
3.1.1
Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 24
3.1.2
Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 25
3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4
Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.1
3.5
4
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 28
Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1
5
Short to VCC and OFF state open load detection . . . . . . . . . . . . . . . . . 27
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/37
VND5E160AJ-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC=13V, Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current sense (8V<VCC<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Openload detection (8V<VCC<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3/37
List of figures
VND5E160AJ-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
4/37
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Openload Off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Delay response time between rising edge of ouput current and rising edge of current sense
(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Iout/ Isense vs. Iout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Overload or Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Intermittent Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
OFF-State Open Load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Short to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TJ evolution in Overload or Short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
On state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
On state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Maximum turn-Off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 28
PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). . . . . . . . 29
PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 30
Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 30
PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
VND5E160AJ-E
Block diagram and pin description
Figure 1.
Block diagram
VCC
Signal Clamp
Undervoltage
IN1
Control & Diagnostic 1
Power
Clamp
DRIVER
IN2
VON
Limitation
Over
temp.
CH 1
Current
Limitation
OFF State
Open load
CS_
DIS
VSENSEH
CS1
CONTROL & DIAGNOSTIC
Channels 2
1
Block diagram and pin description
CH 2
Current
Sense
OUT2
CS2
OUT1
OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)
LOGIC
GND
Table 1.
Pin function
Name
VCC
OUTPUTn
GND
INPUTn
Function
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external
diode/resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls
output switch state.
CURRENT SENSEn Analog current sense pin, delivers a current proportional to the load current.
CS_DIS
Active high CMOS compatible pin, to disable the current sense pin.
5/37
Block diagram and pin description
Figure 2.
VND5E160AJ-E
Configuration diagram (top view)
TAB = Vcc
GND
INPUT2
INPUT1
CURRENT SENSE1
CURRENT SENSE2
CS_DIS
1
2
3
4
5
6
12
11
10
9
8
7
N.C.
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
N.C.
PowerSSO-12
Table 2.
6/37
Suggested connections for unused and not connected pins
Connection / pin
Current sense
N.C.
Output
Input
CS_DIS
Floating
Not allowed
X
X
X
X
To ground
Through 1k
resistor
X
Through 22k Through 10k Through 10k
resistor
resistor
resistor
VND5E160AJ-E
2
Electrical specifications
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VCC
VCC
VFn
ICSD
OUTPUT1
CS_DIS
VCSD
CURRENT
SENSE1
IIN1
INPUT1
VIN1
IIN2
VIN2
OUTPUT2
IOUT1
VOUT1
ISENSE1
VSENSE1
IOUT2
VOUT2
INPUT2
CURRENT
SENSE2
GND
ISENSE2
VSENSE2
IGND
Note:
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage
41
V
-VCC
Reverse DC supply voltage
0.3
V
- IGND
DC reverse ground pin current
200
mA
Internally limited
A
6
A
DC input current
-1 to 10
mA
DC current sense disable input current
-1 to 10
mA
200
mA
VCC-41
+VCC
V
V
IOUT
- IOUT
IIN
ICSD
DC output current
Reverse DC output current
-ICSENSE DC reverse CS pin current
VCSENSE Current sense maximum voltage
7/37
Electrical specifications
Table 3.
Absolute maximum ratings (continued)
Symbol
Parameter
Value
Unit
EMAX
Maximum switching energy (single pulse)
(L=12mH; RL=0; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.) )
34
mJ
VESD
Electrostatic discharge (Human Body Model: R=1.5K
C=100pF)
- INPUT
- CURRENT SENSE
- CS_DIS
- OUTPUT
- VCC
4000
2000
4000
5000
5000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
Max. value
Unit
8
°C/W
See Figure 36
°C/W
Tj
Tstg
2.2
VND5E160AJ-E
Thermal data
Table 4.
Symbol
Thermal data
Parameter
Rthj-case Thermal resistance junction-case (With one channel ON)
Rthj-amb
8/37
Thermal resistance junction-ambient
VND5E160AJ-E
2.3
Electrical specifications
Electrical characteristics
Values specified in this section are for 8V<VCC<28V; -40°C<Tj<150°C, unless otherwise
stated.
Table 5.
Power section
Symbol
Parameter
VCC
Operating supply voltage
VUSD
VUSDhyst
Test conditions
Min. Typ. Max. Unit
4.5
13
28
V
Undervoltage shutdown
3.5
4.5
V
Undervoltage shutdown
hysteresis
0.5
On state resistance (1)
IOUT= 1A; Tj= 25°C
IOUT= 1A; Tj= 150°C
IOUT= 1A; VCC= 5V; Tj= 25°C
Vclamp
Clamp voltage
IS= 20 mA
IS
Supply current
Off State; VCC= 13V; Tj= 25°C;
VIN=VOUT=VSENSE=VCSD=0V
On State; VCC=13V; VIN=5V; IOUT=0A
IL(off1)
Off state output
current (1)
VIN=VOUT=0V; VCC=13V; Tj=25°C
VIN=VOUT=0V; VCC=13V; Tj=125°C
Output - VCC diode
voltage (1)
-IOUT= 0.6A; Tj=150°C
RON
VF
41
0
0
V
160
320
210
m
m
m
46
52
V
2(2)
3
5(2)
6
µA
mA
0.01
3
5
µA
0.7
V
1. For each channel.
2. PowerMOS leakage included.
Table 6.
Symbol
Switching (VCC=13V, Tj=25°C)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(on)
Turn- On delay time
RL= 13 (see Figure 6.)
10
µs
td(off)
Turn- Off delay time
RL= 13 (see Figure 6.)
15
µs
(dVOUT/dt)on
Turn- On voltage
slope
RL= 13
See
Figure 26.
V/µs
(dVOUT/dt)off
Turn- Off voltage
slope
RL= 13
See
Figure 28.
V/µs
WON
Switching energy
losses during twon
RL= 13 (see Figure 6.)
0.03
mJ
WOFF
Switching energy
losses during twoff
RL= 13 (see Figure 6.)
0.02
mJ
9/37
Electrical specifications
Table 7.
Symbol
VND5E160AJ-E
Logic inputs
Parameter
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Test conditions
Min.
VIN= 0.9V
ICSDL
Low level CS_DIS current
VCSDH
CS_DIS high level voltage
ICSDH
High level CS_DIS current
7
V
V
0.9
V
-0.7
1
µA
2.1
V
10
7
V
V
-0.7
Protections and diagnostics (1)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
7
10
14
14
A
A
IlimL
Short circuit current
during thermal cycling
VCC= 13V;
TR<Tj<TTSD
TTSD
Shutdown temperature
TR
Reset temperature
TRS
Thermal reset of STATUS
150
Output voltage drop
limitation
175
A
200
TRS + 1 TRS + 5
135
Thermal hysteresis
(TTSD-TR)
Turn-Off output voltage
clamp
2.5
7
IOUT= 1A; VIN= 0; L= 20mH VCC-41 VCC-46 VCC-52
IOUT= 0.03A;
Tj= -40°C...150°C
(see Figure 8.)
°C
°C
°C
25
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
10/37
µA
V
5.5
ICSD= 1mA
ICSD= -1mA
µA
V
0.25
VCC= 13V
5V<VCC<28V
VON
V
VCSD= 2.1V
DC short circuit current
VDEMAG
2.1
VCSD= 0.9V
IlimH
THYST
V
µA
5.5
VCSD(hyst) CS_DIS hysteresis voltage
Symbol
0.9
10
IIN= 1mA
IIN= -1mA
CS_DIS low level voltage
Table 8.
Unit
0.25
Input clamp voltage
CS_DIS clamp voltage
Max.
1
VIN= 2.1V
VCSDL
VCSCL
Typ.
°C
V
mV
VND5E160AJ-E
Electrical specifications
Table 9.
Symbol
K0
K1
dK1/K1
(1)
K2
dK2/K2(1)
K3
dK3/K3(1)
ISENSE0
IOL
VSENSE
Current sense (8V<VCC<18V)
Parameter
Min. Typ. Max. Unit
IOUT/ISENSE
IOUT= 0.025A; VSENSE= 0.5V; VCSD=0V;
270
Tj= -40°C...150°C
IOUT/ISENSE
IOUT= 0.35A; VSENSE=0.5V; VCSD=0V;
Tj= -40°C...150°C
IOUT=0.35A; VSENSE=0.5V; VCSD=0V;
Tj= 25°C...150°C
IOUT= 0.35A; VSENSE= 0.5V;
Current sense ratio
VCSD=0V;
drift
TJ= -40 °C to 150 °C
IOUT/ISENSE
IOUT= 0.5A; VSENSE= 4V; VCSD= 0V;
Tj= -40°C...150°C
IOUT= 0.5A; VSENSE= 4V; VCSD= 0V;
Tj= 25°C...150°C
IOUT= 0.5 A; VSENSE= 4 V;
Current sense ratio
VCSD= 0V;
drift
TJ= -40 °C to 150 °C
IOUT/ISENSE
IOUT= 1.5A; VSENSE=4V; VCSD=0V;
Tj= -40°C...150°C
IOUT=1.5A; VSENSE=4V; VCSD=0V;
Tj= 25°C...150°C
IOUT= 1.5 A; VSENSE= 4 V;
Current sense ratio
VCSD=0V;
drift
TJ= -40 °C to 150 °C
Analog sense
leakage current
520
730
345
470
610
370
470
540
-13
460
550
390
460
510
-8
8
400
430
470
410
430
460
%
%
-4
4
%
IOUT=0A; VSENSE=0V;
VCSD=5V; VIN=0V; Tj=-40°C...150°C
VCSD=0V; VIN=5V; Tj=-40°C...150°C
0
0
1
2
µA
µA
IOUT=0.6A; VSENSE=0V;
VCSD=5V; VIN=5V; Tj= -40°C...150°C
0
1
µA
5
mA
VIN = 5V, 8V<VCC<18V
ISENSE= 5 µA
1
Max analog
senseoutput
voltage
IOUT=1.5A; VCSD=0V;
5
Analog sense
output current in
fault condition
13
370
Openload ON state
current detection
threshold
Analog sense
VSENSEH(2) output voltage in
fault condition
ISENSEH(2)
Test conditions
V
VCC=13V; RSENSE= 3.9K
8
V
VCC=13V; VSENSE= 5V;
9
mA
11/37
Electrical specifications
Table 9.
Symbol
VND5E160AJ-E
Current sense (8V<VCC<18V) (continued)
Parameter
Test conditions
Min. Typ. Max. Unit
tDSENSE1H
Delay response
time from falling
edge of CS_DIS
pin
VSENSE<4V, 0.08A<Iout<1.5A
ISENSE=90% of ISENSE max
(see Figure 4.)
40
100
µs
tDSENSE1L
Delay response
time from rising
edge of CS_DIS
pin
VSENSE<4V, 0.08A<Iout<1.5A
ISENSE=10% of ISENSE max
(see Figure 4.)
5
20
µs
tDSENSE2H
Delay response
time from rising
edge of INPUT pin
VSENSE<4V, 0.08A<Iout<1.5A
ISENSE=90% of ISENSE max
(see Figure 4.)
30
150
µs
Delay response
time between rising
edge of output
tDSENSE2H
current and rising
edge of current
sense
VSENSE < 4V,
ISENSE = 90% of ISENSEMAX,
IOUT = 90% of IOUTMAX
IOUTMAX= 1.5A (see Figure 7)
Delay response
time from falling
edge of INPUT pin
VSENSE<4V, 0.08A<Iout<1.5A
ISENSE=10% of ISENSE max
(see Figure 4.)
tDSENSE2L
110
80
µ
s
250
µs
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation, overtemperature and open load OFF state detection.
Table 10.
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
2
See
Figure 5
4
V
Openload Off state
voltage detection
threshold
VIN = 0 V
tDSTKON
Output short circuit to
VCC detection delay at
turn Off
See Figure 5
180
1200
µs
IL(off2)r
Off state output current
at VOUT = 4V
VIN=0V; VSENSE=0V
VOUT rising from 0V to 4V
-120
0
µA
IL(off2)f
Off state output current
at VOUT = 2V
VIN=0V; VSENSE=VSENSEH
VOUT falling from VCC to 2V
-50
90
µA
td_vol
Delay response from
output rising edge to
VSENSE rising edge in
open-load
VOUT= 4 V; VIN= 0V
VSENSE= 90% of VSENSEH
20
µs
VOL
12/37
Openload detection (8V<VCC<18V)
VND5E160AJ-E
Electrical specifications
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
tDSENSE2H
Figure 5.
tDSENSE1L
tDSENSE1H
tDSENSE2L
Openload Off-state delay timing
OUTPUT STUCK TO VCC
VIN
VOUT > VOL
VSENSEH
VCS
tDSTKON
Figure 6.
Switching characteristics
VOUT
tWoff
tWon
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
tr
10%
tf
t
INPUT
td(on)
td(off)
t
13/37
Electrical specifications
Figure 7.
VND5E160AJ-E
Delay response time between rising edge of ouput current and rising
edge of current sense (CS enabled)
VIN
tDSENSE2H
t
IOUT
IOUTMAX
90% IOUTMAX
t
ISENSE
ISENSEMAX
90% ISENSEMAX
t
Figure 8.
Output voltage drop limitation
Vcc-Vout
Tj=150oC
Tj=25oC
Tj=-40oC
Von
Iout
Von/Ron(T)
14/37
VND5E160AJ-E
Electrical specifications
Figure 9.
Iout/ Isense vs. Iout
Iout / Isense
700
650
600
max Tj = -40 °C to 150 °C
max Tj = 25 °C to 150 °C
550
500
typical value
450
min Tj = 25 °C to 150 °C
400
350
min Tj = -40 °C to 150 °C
300
250
200
0,35
0,58
0,81
1,04
1,27
1,5
IOUT (A)
Figure 10. Maximum current sense ratio drift vs load current
dk/k(%)
15
10
5
0
-5
-10
-15
0,35
0,58
0,81
1,04
1,27
1,5
IOUT (A)
Note:
Parameter guaranteed by design; it is not tested.
15/37
Electrical specifications
Table 11.
VND5E160AJ-E
Truth table
Input
Output
Sense (VCSD=0V)(1)
Normal operation
L
H
L
H
0
Nominal
Overtemperature
L
H
L
L
0
VSENSEH
Undervoltage
L
H
L
L
0
0
H
X
(no power limitation)
Cycling
(power limitation)
Nominal
Conditions
Overload
H
VSENSEH
Short circuit to GND
(Power limitation)
L
H
L
L
0
VSENSEH
Open load OFF State
(with external pull up)
L
H
VSENSEH
Short circuit to VCC
(external pull up
disconnected)
L
H
H
H
VSENSEH
< Nominal
Negative output voltage
clamp
L
L
0
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
16/37
VND5E160AJ-E
Electrical specifications
Table 12.
ISO 7637-2:
2004(E)
Test pulse
Electrical transient requirements
Test levels(1)
III
IV
1
-75V
-100V
2a
+37V
3a
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
Impedance
Min.
Max.
5000 pulses
0.5s
5s
2 ms, 10
+50V
5000 pulses
0.2s
5s
50µs, 2
-100V
-150V
1h
90ms
100ms
0.1µs, 50
3b
+75V
+100V
1h
90ms
100ms
0.1µs, 50
4
-6V
-7V
1 pulse
100ms, 0.01
+65V
+87V
1 pulse
400ms, 2
5b
(2)
ISO 7637-2:
2004E
Test pulse
III
VI
1
C
C
2a
C
C
3a
C
C
3b
C
C
4
C
C
5b(2)
C
C
Class
Test level results
Contents
C
All functions of the device performed as designed after exposure to disturbance.
E
One or more functions of the device did not perform as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
17/37
Electrical specifications
2.4
VND5E160AJ-E
Waveforms
Figure 11. Normal operation
Normal operation
INPUT
Nominal load
Nominal load
IOUT
VSENSE
VCS_DIS
Figure 12. Overload or Short to GND
Overload or Short to GND
INPUT
ILimH >
Power Limitation
Thermal cycling
ILimL >
IOUT
VSENSE
VCS_DIS
18/37
VND5E160AJ-E
Electrical specifications
Figure 13. Intermittent Overload
Intermittent Overload
INPUT
Overload
ILimH >
ILimL >
Nominal load
IOUT
VSENSEH>
VSENSE
VCS_DIS
Figure 14. OFF-State Open Load with external circuitry
OFF-State Open Load
with external circutry
INPUT
VOUT > VOL
VOUT
VOL
IOUT
VSENSEH >
tDSTK(on)
VSENSE
VCS_DIS
19/37
Electrical specifications
VND5E160AJ-E
Figure 15. Short to VCC
Short to VCC
Resistive
Short to VCC
Hard
Short to VCC
VOUT > VOL
VOL
VOUT
IOUT
tDSTK(on)
tDSTK(on)
VCS_DIS
Figure 16. TJ evolution in Overload or Short to GND
TJ evolution in
Overload or Short to GND
INPUT
Self-limitation of fast thermal transients
TTSD
THYST
TR
TJ_START
TJ
ILimH >
Power Limitation
< ILimL
IOUT
20/37
VND5E160AJ-E
2.5
Electrical specifications
Electrical characteristics curves
Figure 17. Off state output current
Figure 18. High level input current
Iloff (nA)
Iih (µA)
300
5
4,5
250
Vin=2.1V
Off State
Vcc=13V
Vin=Vout=0V
200
4
3,5
3
150
2,5
2
100
1,5
1
50
0,5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
100
125
150
175
150
175
Tc (°C)
Figure 19. Input clamp voltage
Figure 20. Input low level
Vicl (V)
Vil (V)
7
2
6,8
1,8
lin=1mA
6,6
1,6
6,4
1,4
6,2
1,2
6
1
5,8
0,8
5,6
0,6
5,4
0,4
5,2
0,2
5
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
Tc (°C)
Figure 21. Input high level
Figure 22. Input hysteresis voltage
Vih (V)
Vihyst (V)
1
4
0,9
3,5
0,8
3
0,7
2,5
0,6
0,5
2
0,4
1,5
0,3
1
0,2
0,5
0,1
0
0
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
100
125
Tc (°C)
21/37
Electrical specifications
VND5E160AJ-E
Figure 23. On state resistance vs. Tcase
Figure 24. On state resistance vs. VCC
Ron (mOhm)
Ron (mOhm)
300
300
Iout= 1A
Vcc=13V
250
Tc=150°C
250
Tc=125°C
200
200
150
150
Tc=25°C
100
100
50
Tc=-40°C
50
-50
-25
0
25
50
75
100
125
150
175
0
5
10
15
Tc (°C)
20
25
30
35
40
150
175
150
175
Vcc (V)
Figure 25. Undervoltage shutdown
Figure 26. Turn-On voltage slope
Vusd (V)
(dVout/dt )On (V/ms)
16
1000
900
14
Vcc=13V
RI=13 Ohm
800
12
700
10
600
500
8
400
6
300
4
200
2
100
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
Tc (°C)
Figure 27. ILIMH vs. Tcase
Figure 28. Turn-Off voltage slope
Ilimh (A)
(dVout/dt )Off (V/ms)
20
1400
1300
Vcc=13V
Vcc=13V
RI= 13 Ohm
1200
15
1100
1000
10
900
800
5
700
600
0
500
-50
-25
0
25
50
Tc (°C)
22/37
75
100
125
150
-50
-25
0
25
50
75
Tc (°C)
100
125
VND5E160AJ-E
Electrical specifications
Figure 29. CS_DIS high level voltage
Figure 30. CS_DIS clamp voltage
Vcsdh (V)
Vcsdcl(V)
10
4
9
3,5
8
Iin = 1 mA
3
7
2,5
6
5
2
4
1,5
3
1
2
0,5
1
0
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Figure 31. CS_DIS low level voltage
Vcsdl (V)
3
2,5
2
1,5
1
0,5
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
23/37
Application information
3
VND5E160AJ-E
Application information
Figure 32. Application schematic
+5V
VCC
Rprot
CS_DIS
Dld
CU
Rprot
INPUT
OUTPUT
Rprot
CURRENT SENSE
GND
RSENSE
CEXT
VGND
RGND
DGND
Note:
Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1
Solution 1 : resistor in the ground line (RGND only)
This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1.
RGND  600mV / (IS(on)max)
2.
RGND VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum On-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are On in the case of several
high side drivers sharing the same RGND.
24/37
VND5E160AJ-E
Application information
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2 : diode (DGND) in the ground line
A resistor (RGND=1kshould be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3
MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os:
-VCCpeak/Ilatchup  Rprot  (VOHC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak = - 100V and Ilatchup  20mA; VOHµC  4.5V
5k  Rprot  180k
Recommended values: Rprot =10k, CEXT=10nF.
25/37
Application information
3.4
VND5E160AJ-E
Current sense and diagnostic
The current sense pin performs a double function (see Figure 33: Current sense and
diagnostic):
●
Current mirror of the load current in normal operation, delivering a current
proportional to the load one according to a know ratio KX.
The current ISENSE can be easily converted to a voltage VSENSE by means of an
external resistor RSENSE. Linearity between IOUT and VSENSE is ensured up to 5V
minimum (see parameter VSENSE in Table 9: Current sense (8V<VCC<18V)). The
current sense accuracy depends on the output current (refer to current sense electrical
characteristics Table 9: Current sense (8V<VCC<18V)).
●
Diagnostic flag in fault conditions, delivering a fixed voltage VSENSEH up to a
maximum current ISENSEH in case of the following fault conditions (refer to Truth table):
–
Power limitation activation
–
Over-temperature
–
Short to VCC in OFF state
–
Open load in OFF state with additional external components.
A logic level high on CS_DIS pin sets at the same time all the current sense pins of the
device in a high impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of
sense resistance and ADC line among different devices.
Figure 33. Current sense and diagnostic
VPU
VBAT
VCC
Main MOSn
41V
PU_CMD
Overtemperature
IOUT/KX
RPU
+
OL OFF
ISENSEH
VOL
Pwr_Lim
CS_DIS
OUTn
ILoff2r
ILoff2f
INPUTn
VSENSEH
CURRENT
SENSEn
RPROT
To uC ADC
26/37
RSENSE
GND
Load
RPD
VSENSE
VND5E160AJ-E
3.4.1
Application information
Short to VCC and OFF state open load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off state. Small or no current is delivered by the current sense
during the on state depending on the nature of the short circuit.
OFF state open load with external circuitry
Detection of an open load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable VPU to be switched off during the module stand-by mode in order to avoid the
overall stand-by current consumption to increase in normal conditions, i.e. when load is
connected.
An external pull down resistor RPD connected between output and GND is mandatory to
avoid misdetection in case of floating outputs in off state (see Figure 33: Current sense and
diagnostic).
RPD must be selected in order to ensure VOUT < VOLmin unless pulled up by the external
circuitry:
VOUT
Pull  up _ OFF
 RPD  I L ( off 2) f  VOL min  2V
RPD 22Kis recommended.
For proper open load detection in off state, the external pull-up resistor must be selected
according to the following formula:
VOUT
Pull  up _ ON

RPD  VPU  RPU  RPD  I L ( off 2) r
RPU  RPD
 VOL max  4V
For the values of VOLmin ,VOLmax, IL(off2)r and IL(off2)f see Table 10: Openload detection
(8V<VCC<18V).
27/37
Application information
3.5
VND5E160AJ-E
Maximum demagnetization energy (VCC = 13.5V)
Figure 34. Maximum turn-Off current versus inductance (for each channel)
100
10
A
B
C
I (A)
1
0,1
0,1
1
L (mH)
10
100
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL = 0 
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
28/37
VND5E160AJ-E
Package and PC board thermal data
4
Package and PC board thermal data
4.1
PowerSSO-12 thermal data
Figure 35. PowerSSO-12 PC board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 36. Rthj-amb vs. PCB copper area in open box free air condition (one channel ON)
RTHj_amb( ° C/ W)
70
65
60
55
50
45
40
0
2
4
6
8
10
PCB Cu heat sink area ( cm^ 2)
29/37
Package and PC board thermal data
VND5E160AJ-E
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one
channel ON)
ZTH ( ° C/ W)
100
Footprint
2 cm2
8 cm2
10
1
0,001
0,01
0,1
1
Time ( s)
10
100
1000
Equation 1: pulse calculation formula
Z
TH
= R
TH
+Z
THtp
1 – 
where  = tP/T
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12 (a)
a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
30/37
VND5E160AJ-E
Table 13.
Package and PC board thermal data
Thermal parameters
Area/island (cm2)
Footprint
R1= R7 (°C/W)
1.2
R2= R8 (°C/W)
6
R3 (°C/W)
3
R4 (°C/W)
2
8
8
8
7
R5 (°C/W)
22
15
10
R6 (°C/W)
26
20
15
C1= C7 (W.s/°C)
0.0008
C2= C8 (W.s/°C)
0.0016
C3 (W.s/°C)
0.0166
C4 (W.s/°C)
0.2
0.1
0.1
C5 (W.s/°C)
0.27
0.8
1
C6 (W.s/°C)
3
6
9
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Package and packing information
5
Package and packing information
5.1
ECOPACK® packages
VND5E160AJ-E
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
Package mechanical data
Figure 39. PowerSSO-12 package dimensions
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VND5E160AJ-E
Package and packing information
PowerSSO-12 mechanical data
Table 14.
Millimeters
Symbol
Min.
Typ.
Max.
A
1.250
1.620
A1
0.000
0.100
A2
1.100
1.650
B
0.230
0.410
C
0.190
0.250
D
4.800
5.000
E
3.800
4.000
e
0.800
H
5.800
6.200
h
0.250
0.500
L
0.400
1.270
k
0°
8°
X
2.200
2.800
Y
2.900
3.500
ddd
0.100
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Package and packing information
5.3
VND5E160AJ-E
Packing information
Figure 40. PowerSSO-12 tube shipment (no suffix)
B
C
A
Base Q.ty
100
Bulk Q.ty
2000
Tube length (± 0.5)
532
A
1.85
B
6.75
C (± 0.1)
0.6
All dimensions are in mm.
Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
End
All dimensions are in mm.
Start
Top
cover
tape
No components Components
500mm min
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
34/37
No components
VND5E160AJ-E
6
Order codes
Order codes
Table 15.
Device summary
Order codes
Package
PowerSSO-12
Tube
Tape and reel
VND5E160AJ-E
VND5E160AJTR-E
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Revision history
7
VND5E160AJ-E
Revision history
Table 16.
36/37
Document revision history
Date
Revision
Changes
13-Sep-2004
1
Initial release.
14-Mar-2008
2
Document reformatted and restructured.
Updated Figure 2: Configuration diagram (top view) : pins 7-12 left
unconnected (N.C) .
Updated Table 9: Current sense (8V<VCC<18V):
– added k, dk/k, tDSENSE1H, tDSENSE1L, tDSENSE2H, tDSENSE2H,
tDSENSE2L values
Updated Table 10: Openload detection (8V<VCC<18V):
– added IL(off2)r, IL(off2)f and td_vol parameters
Added Figure 7: Delay response time between rising edge of ouput
current and rising edge of current sense (CS enabled).
Added Figure 9: Iout/ Isense vs. Iout.
Added Figure 10: Maximum current sense ratio drift vs load current.
Table 12: Electrical transient requirements : updated test level values
III and IV for test pulse 5b and notes.
Added Section 2.4: Waveforms.
Added Section 2.5: Electrical characteristics curves.
Updated Section 3: Application information:
– added Section 3.4: Current sense and diagnostic
Updated Section 4.1: PowerSSO-12 thermal data:
– changed Figure 36: Rthj-amb vs. PCB copper area in open box
free air condition (one channel ON).
– added Figure 37: PowerSSO-12 thermal impedance junction
ambient single pulse (one channel ON).
– Figure 38: Thermal fitting model of a double channel HSD in
PowerSSO-12 : added note.
– updated Table 13: Thermal parameters:
R3 value changed from 7 to 3 °C/W.
R4 values changed from 10 /10 /9 to 8 /8 /7 °C/W.
C3 value changed from 0.05 to 0.0166 W.s/°C.
24-Sep-2013
3
Updated disclaimer.
VND5E160AJ-E
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