VNQ5E160MK-E Quad channel high-side driver with analog current sense for automotive application Datasheet - production data – Protection against loss of ground and loss of VCC – Over temperature shutdown with autorestart (thermal shutdown) – Reverse battery protected – Electrostatic discharge protection – Inrush current active management by power limitation 0OWER33/ ("1($'5 Features Max supply voltage VCC 41V Operating voltage range VCC 4.5 to 28 V Max on-state resistance (per ch.) RON 160 mΩ Current limitation (typ) ILIMH 10 A Off-state supply current IS 2 µA(1) 1. Typical value with all loads connected. • General – Very low standby current – 3.0 V CMOS-compatible inputs – Optimized electromagnetic emissions – Very low electromagnetic susceptibility – Compliant with European directive 2002/95/EC – Very low current sense leakage • Diagnostic functions – Proportional load current sense – High current sense precision for wide currents range – Current sense disable – Thermal shutdown indication – Overload and short to ground (power limitation) indication • Protection – Undervoltage shutdown – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients November 2013 This is information on a product in full production. Application • All types of resistive, inductive and capacitive loads • Suitable as LED driver Description The VNQ5E160MK-E is a double channel highside driver manufactured using ST proprietary VIPower® M0-5 technology and housed in PowerSSO-24 package. The device is designed to drive 12 V automotive grounded loads, and to provide protection and diagnostics. It also implement a 3 V and 5 V CMOS-compatible interface for use with any microcontroller. The device integrates advanced protective functions such as load current limitation, inrush and overload active management by power limitation, overtemperature shut-off with auto-restart and over voltage active clamp. A dedicated analog current sense pin is associated with every output channel providing enhanced diagnostic functions including fast detection of overload and short-circuit to ground through power limitation indication and over temperature indication. The current sensing and diagnostic feedback of the whole device can be disabled by pulling the CS_DIS pin high to share the external sense resistor with similar devices. DocID018850 Rev 2 1/34 www.st.com Contents VNQ5E160MK-E Contents 1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 4 3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 22 3.1.2 Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 23 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5 Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 25 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1 5 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2/34 DocID018850 Rev 2 VNQ5E160MK-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC = 13 V; Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Current sense (8 V < VCC < 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DocID018850 Rev 2 3/34 3 List of figures VNQ5E160MK-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. 4/34 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IOUT/ ISENSE vs IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum current sense ratio drift vs load current(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TJ evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 25 PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . . 26 PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON). . . . . 27 Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 27 PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DocID018850 Rev 2 VNQ5E160MK-E Block diagram and pin configuration Figure 1. Block diagram 9&& 6LJQDO&ODPS 8QGHUYROWDJH ,1 &RQWURO'LDJQRVWLF 3RZHU &ODPS &21752/',$*1267,& &KDQQHOV 1 Block diagram and pin configuration '5,9(5 ,1 921 /LPLWDWLRQ &+ ,1 2YHU WHPS ,1 &XUUHQW /LPLWDWLRQ &6B ',6 96(16(+ &6 &XUUHQW 6HQVH &+ &+ 287 287 &+ 287 &6 287 &6 &6 /2*,& 29(5/2$'3527(&7,21 $&7,9(32:(5/,0,7$7 ,21 *1' ("1($'5 Table 1. Pin functions Name VCC OUTPUTn GND INPUTn Function Battery connection Power output Ground connection. Must be reverse battery protected by an external diode/resistor network Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state CURRENT SENSEn Analog current sense pin, delivers a current proportional to the load current CS_DIS Active high CMOS compatible pin, to disable the current sense pin DocID018850 Rev 2 5/34 33 Block diagram and pin configuration VNQ5E160MK-E Figure 2. Configuration diagram (top view) 9&& *1' ,1387 &855(176(16( ).054 &855(176(16( ,1387 &855(176(16( ,1387 &855(176(16( &6B',6 9&& 287387 287387 287387 287387 287387 287387 287387 287387 287387 287387 287387 287387 7$% 9&& ("1($'5 Table 2. Suggested connections for unused and not connected pins 6/34 Connection / pin Current sense N.C. Output Input CS_DIS Floating Not allowed X X X X To ground Through 1 kΩ resistor X Not allowed Through 10 kΩ resistor Through 10 kΩ resistor DocID018850 Rev 2 VNQ5E160MK-E 2 Electrical specifications Electrical specifications Figure 3. Current and voltage conventions ,6 9&& 9&& 9)Q ,287Q 287387Q ,&6' 9287Q 9&6' &6B',6 ,6(16(Q ,,1Q &855(17 6(16(Q ,1387Q 6 ,1Q *1' 96(16(Q ,*1' *$3*&)7 1. VFn = VOUTn - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Table 3. Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 41 V -VCC Reverse DC supply voltage 0.3 V -IGND DC reverse ground pin current 200 mA IOUT DC output current Internally limited A -IOUT Reverse DC output current 6 A DC input current -1 to 10 mA DC current sense disable input current -1 to 10 mA 200 mA VCC-41 +VCC V V 34 mJ IIN ICSD -ICSENSE DC reverse CS pin current VCSENSE Current sense maximum voltage EMAX Maximum switching energy (single pulse) (L = 12 mH; RL = 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C; IOUT = IlimL(Typ.)) DocID018850 Rev 2 7/34 33 Electrical specifications VNQ5E160MK-E Table 3. Absolute maximum ratings (continued) Symbol Value Unit VESD Electrostatic discharge (human body model: R = 1.5 KΩ; C = 100 pF) – INPUT – CURRENT SENSE – CS_DIS – OUTPUT – VCC 4000 2000 4000 5000 5000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V Junction operating temperature -40 to 150 °C Storage temperature -55 to 150 °C Tj Tstg 2.2 Parameter Thermal data Table 4. Thermal data 8/34 Symbol Parameter Maximum value Unit Rthj-case Thermal resistance junction-case (with one channel ON) 8 °C/W Rthj-amb Thermal resistance junction-ambient See Figure 33 in the thermal section °C/W DocID018850 Rev 2 VNQ5E160MK-E 2.3 Electrical specifications Electrical characteristics Values specified in this section are for 8 V < VCC < 28 V, -40 °C < Tj < 150 °C, unless otherwise stated. Table 5. Power section Symbol Parameter VCC Operating supply voltage VUSD VUSDhyst RON Vclamp IS IL(off1) VF Test conditions Min. 13 28 V Undervoltage shutdown 3.5 4.5 V Undervoltage shutdown hysteresis 0.5 On-state resistance (2) Clamp voltage 4.5 Typ. Max. Unit IOUT = 1 A; Tj = 25 °C 160 mΩ IOUT = 1 A; Tj = 150 °C 320 mΩ IOUT = 1 A; VCC = 5 V; Tj = 25 °C 210 mΩ 46 52 V 2 (1) 5 (1) µA 8 14 mA 0.01 3 µA 5 µA 0.7 V IS = 20 mA 41 Off-state; VCC = 13 V; Tj = 25 °C; VIN = VOUT = VSENSE = VCSD = 0 V Supply current On-state; VCC = 13 V; VIN = 5 V; IOUT = 0 A Off-state output current(2) Output - VCC diode voltage(2) V VIN = VOUT =0 V; VCC = 13 V; Tj = 25 °C 0 VIN = VOUT = 0 V; VCC = 13 V; Tj = 125 °C 0 -IOUT =1 A; Tj = 150 °C 1. PowerMOS leakage included. 2. For each channel. Table 6. Switching (VCC = 13 V; Tj = 25 °C) Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time RL = 13 Ω (see Figure 5) — 20 — µs td(off) Turn-off delay time RL = 13 Ω (see Figure 5) — 10 — µs Turn-on voltage slope RL = 13 Ω — See Figure 23 — V/µs (dVOUT/dt)off Turn-off voltage slope RL = 13 Ω — See Figure 25 — V/µs WON Switching energy losses during twon RL = 13 Ω (see Figure 5) — 0.05 — mJ WOFF Switching energy losses during twoff RL = 13 Ω (see Figure 5) — 0.03 — mJ (dVOUT/dt)on DocID018850 Rev 2 9/34 33 Electrical specifications VNQ5E160MK-E Table 7. Logic Inputs Symbol Parameter Test conditions VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL VIN = 0.9 V Max. Unit 0.9 V 1 µA 2.1 V 10 0.25 IIN = 1 mA Input clamp voltage CS_DIS low level voltage ICSDL Low level CS_DIS current VCSDH CS_DIS high level voltage ICSDH High level CS_DIS current VCSD(hyst) CS_DIS hysteresis voltage 7 -0.7 V 1 µA 2.1 V VCSD = 2.1 V 10 0.25 ICSD = 1 mA V V 0.9 VCSD = 0.9 V µA V 5.5 IIN = -1 mA CS_DIS clamp voltage Typ. VIN = 2.1 V VCSDL VCSCL Min. V 5.5 ICSD = -1 mA µA 7 -0.7 V V Table 8. Protections and diagnostics (1) Symbol Parameter Test conditions IlimH DC short circuit current IlimL Short circuit current during thermal cycling TTSD Shutdown temperature Reset temperature TRS Thermal reset of STATUS VDEMAG VON Typ. Max. Unit 7 10 14 A 14 A 5 V < VCC < 28 V TR THYST VCC = 13 V Min. VCC = 13 V; TR < Tj < TTSD 2.5 150 175 TRS + 1 TRS + 5 A 200 °C 135 Thermal hysteresis (TTSD-TR) °C 7 Turn-off output voltage clamp IOUT = 1 A; VIN = 0; L = 20 mH Output voltage drop limitation IOUT = 0.03 A; Tj = -40 °C...150 °C (see Figure 6) VCC41 VCC46 °C VCC-52 25 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. 10/34 DocID018850 Rev 2 °C V mV VNQ5E160MK-E Electrical specifications Table 9. Current sense (8 V < VCC < 18 V) Symbol K0 K1 dK1/K1(1) K2 dK2/K2(1) K3 dK3/K3(1) ISENSE0 Parameter Test conditions Min. Typ. Max. Unit IOUT/ISENSE IOUT = 0.025 A; VSENSE = 0.5 V; VCSD = 0 V; Tj = -40 °C to 150 °C 330 600 870 IOUT/ISENSE IOUT = 0.35 A; VSENSE = 0.5 V; VCSD = 0 V; Tj = -40 °C to 150 °C Tj = 25 °C to 150 °C 337 395 475 475 642 555 Current sense ratio drift IOUT = 0.35 A; VSENSE = 0.5 V; VCSD = 0 V; Tj = -40 °C to 150 °C IOUT/ISENSE IOUT = 0.5 A; VSENSE = 4 V; VCSD = 0 V; Tj = -40 °C to 150 °C Tj = 25 °C to 150 °C Current sense ratio drift IOUT = 0.5 A; VSENSE = 4 V; VCSD = 0 V; Tj = -40 °C to 150 °C IOUT/ISENSE IOUT = 1.5 A; VSENSE = 4 V; VCSD = 0 V; Tj = -40 °C to 150 °C Tj = 25 °C to 150 °C Current sense ratio drift IOUT = 1.5 A; VSENSE = 4 V; VCSD = 0 V; Tj = -40 °C to 150 °C Analog sense leakage current - 12 375 407 12 470 470 -8 425 435 583 544 8 465 465 % % 505 495 -6 6 % IOUT = 0 A; VSENSE = 0 V; VCSD = 5 V; VIN = 0 V; Tj = -40 °C to 150 °C 0 1 µA VCSD = 0 V; VIN = 5 V; Tj = -40 °C to 150 °C 0 2 µA IOUT = 1 A; VSENSE = 0 V; VCSD = 5 V; VIN = 5 V; Tj = -40 °C to 150 °C 0 1 µA 5 mA IOL Openload ON-state current detection threshold VIN = 5 V; ISENSE = 5 µA 1 VSENSE Max analog sense output voltage IOUT = 1.5 A; VCSD = 0 V 5 VSENSEH Analog sense output voltage in fault condition(2) VCC = 13 V; RSENSE = 3.9 KΩ; 8 V Analog sense output ISENSEH(2) current in fault condition(2) VCC = 13 V; VSENSE = 5 V; 9 mA Delay response time tDSENSE1H from falling edge of CS_DIS pin VSENSE < 4 V; 0.025 A < IOUT < 1.5 A; ISENSE = 90 % of ISENSE max (see Figure 4) 40 DocID018850 Rev 2 V 100 µs 11/34 33 Electrical specifications VNQ5E160MK-E Table 9. Current sense (8 V < VCC < 18 V) (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit Delay response time tDSENSE1L from rising edge of CS_DIS pin VSENSE < 4 V; 0.025 A < IOUT < 1.5 A; ISENSE = 10 % of ISENSE max (see Figure 4) 5 20 µs Delay response time tDSENSE2H from rising edge of INPUT pin VSENSE < 4 V; 0.025 A < IOUT < 1.5 A; ISENSE = 90 % of ISENSE max (see Figure 4) 120 300 µs Delay response time between rising edge of ΔtDSENSE2H output current and rising edge of current sense VSENSE < 4 V; ISENSE = 90% of ISENSEMAX; IOUT = 90% of IOUTMAX IOUTMAX = 1.5 A (see Figure 7) 110 µs Delay response time tDSENSE2L from falling edge of INPUT pin VSENSE < 4 V; 0.025 A < IOUT < 1.5 A ISENSE = 10 % of ISENSE max (see Figure 4) 250 µs 80 1. Parameter guaranteed by design; it is not tested 2. Fault condition includes: power limitation and overtemperature. Figure 4. Current sense delay characteristics ,1387 &6B',6 /2$'&855(17 6(16(&855(17 W'6(16(+ W'6(16(/ W'6(16(+ W'6(16(/ $*9 12/34 DocID018850 Rev 2 VNQ5E160MK-E Electrical specifications Figure 5. Switching characteristics 9287 W:RQ W:RII G9287GWRQ G9287GWRII WU WI W ,1387 WGRQ WGRII W $*9 Figure 6. Output voltage drop limitation 9&&9287 7M & 7M & 7M & 921 ,287 9215217 $*9 DocID018850 Rev 2 13/34 33 Electrical specifications VNQ5E160MK-E Figure 7. Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) 9,1 ǻW'6(16(+ W ,287 ,2870$; ,2870$; W ,6(16( ,6(16(0$; ,6(16(0$; W $*9 Figure 8. IOUT/ ISENSE vs IOUT *PVU*TFOTF NBY5 K¡$UP¡$ NBY5 K¡$UP¡$ UZQJDBMWBMVF NJO5 K¡$UP¡$ NJO5 K¡$UP¡$ *065" 14/34 DocID018850 Rev 2 ("1($'5 VNQ5E160MK-E Electrical specifications Figure 9. Maximum current sense ratio drift vs load current(1) ELL *065" ("1($'5 1. Parameter guaranteed by design; it is not tested. Table 10. Truth table Input Output Sense (VCSD = 0 V)(1) Normal operation L H L H 0 Nominal Overtemperature L H L L 0 VSENSEH Undervoltage L H L L 0 0 H X (no power limitation) Cycling (power limitation) Nominal Conditions Overload H VSENSEH Short circuit to GND (Power limitation) L H L L 0 VSENSEH Negative output voltage clamp L L 0 1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit. DocID018850 Rev 2 15/34 33 Electrical specifications VNQ5E160MK-E Table 11. Electrical transient requirements (part 1) ISO 7637-2: 2004(E) Test pulse Test levels(1) III IV 1 -75V -100V 2a +37V 3a Number of pulses or test times Burst cycle/pulse repetition time Delays and Impedance Min. Max. 5000 pulses 0.5s 5s 2 ms, 10Ω +50V 5000 pulses 0.2s 5s 50µs, 2Ω -100V -150V 1h 90ms 100ms 0.1µs, 50Ω 3b +75V +100V 1h 90ms 100ms 0.1µs, 50Ω 4 -6V -7V 1 pulse 100ms, 0.01Ω 5b(2) +65V +87V 1 pulse 400ms, 2Ω 1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b. 2. Valid in case of external load dump clamp: 40 V maximum referred to ground. Table 12. Electrical transient requirements (part 2) ISO 7637-2: 2004E Test pulse Test level results III VI 1 C C 2a C C 3a C C 3b C C 4 C C 5b(1) C C 1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. Table 13. Electrical transient requirements (part 3) Class 16/34 Contents C All functions of the device performed as designed after exposure to disturbance. E One or more functions of the device did not perform as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. DocID018850 Rev 2 VNQ5E160MK-E 2.4 Electrical specifications Waveforms Figure 10. Normal operation 1RUPDORSHUDWLRQ ,1387 1RPLQDOORDG 1RPLQDOORDG ,287 96(16( 9&6B',6 $*9 Figure 11. Overload or short to GND 2YHUORDGRU6KRUWWR*1' ,1387 3RZHU/LPLWDWLRQ , /LP+! 7KHUPDOF\FOLQJ , /LP/! ,287 96(16( 9&6B',6 $*9 DocID018850 Rev 2 17/34 33 Electrical specifications VNQ5E160MK-E Figure 12. Intermittent overload ,QWHUPLWWHQW2YHUORDG ,1387 2YHUORDG ,/LP+ ! ,/LP/ ! 1RPLQDOORDG ,287 96(16(+ ! 96(16( 9&6B',6 $*9 Figure 13. TJ evolution in overload or short to GND 7- HYROXWLRQLQ 2YHUORDGRU6KRUWWR*1' ,1387 6HOIOLPLWDWLRQRIIDVWWKHUPDOWUDQVLHQWV 776' 7+<67 75 7-B67$57 7,/LP+! 3RZHU/LPLWDWLRQ ,/LP/ ,287 $*9 18/34 DocID018850 Rev 2 VNQ5E160MK-E 2.5 Electrical specifications Electrical characteristics curves Figure 14. Off-state output current Figure 15. High level input current ,ORIIP$ ,LK$ 9LQ 9 2II6WDWH 9FF 9 9LQ 9RXW 9 7F & 7F & ("1($'5 Figure 16. Input clamp voltage ("1($'5 Figure 17. Input low level voltage 9LFO9 9LO9 OLQ P$ 7F & Figure 18. Input high level voltage 7F & ("1($'5 ("1($'5 Figure 19. Input hysteresis voltage 9LK\VW9 9LK9 7F & ("1($'5 7F& ("1($'5 DocID018850 Rev 2 19/34 33 Electrical specifications VNQ5E160MK-E Figure 20. On-state resistance vs Tcase Figure 21. On-state resistance vs VCC 5RQ2KP 5RQ2KP 7F & ,RXW $ 9FF 9 7F & 7F & 7F & 7F & Figure 22. Undervoltage shutdown 9FF9 ("1($'5 ("1($'5 Figure 23. Turn-on voltage slope 9XVG9 G9RXWGW2Q9PV 9FF 9 5, 2KP 7F & Figure 24. ILIMH vs Tcase 7F& ("1($'5 ("1($'5 Figure 25. Turn-off voltage slope ,OLPK$ G9RXWGW2II9PV 9FF 9 5, 2KP 9FF 9 7F & 20/34 ("1($'5 DocID018850 Rev 2 7F& ("1($'5 VNQ5E160MK-E Electrical specifications Figure 26. CS_DIS high level voltage 9FVGK9 Figure 27. CS_DIS clamp voltage 9FVGFO9 ,LQ P$ 7F & 7F & ("1($'5 ("1($'5 Figure 28. CS_DIS low level voltage 9FVGO9 7F & ("1($'5 DocID018850 Rev 2 21/34 33 Application information 3 VNQ5E160MK-E Application information Figure 29. Application schematic 9 6 && 5SURW &6B',6 'OG 5SURW 0&8 ,1387 287387 5SURW &855(176(16( *1' 56(16( 9*1' &(;7 5*1' '*1' ("1($'5 1. Channel 2, 3, 4 have the same internal circuit as channel 1. 3.1 GND protection network against reverse battery This section provides two solutions for implementing a ground protection network against reverse battery. 3.1.1 Solution 1: resistor in the ground line (RGND only) This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. RGND ≤ 600 mV / (IS(on)max) 2. RGND ≥ (−VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in RGND (when VCC < 0: during reverse battery situations) is: PD = (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum On-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift varies depending on how many devices are ON in the case of several high side drivers sharing the same RGND. 22/34 DocID018850 Rev 2 VNQ5E160MK-E Application information If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). 3.1.2 Solution 2 : diode (DGND) in the ground line A resistor (RGND = 1 kΩ) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (≈ 600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift not varies if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table. 3.3 MCU I/Os protection If a ground protection network is used and negative transient are present on the VCC line, the control pins are pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os: -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC - VIH - VGND) / IIHmax Calculation example: For VCCpeak = -100 V and Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V 5 kΩ ≤ Rprot ≤ 180 kΩ Recommended values: Rprot = 10 kΩ, CEXT = 10 nF. DocID018850 Rev 2 23/34 33 Application information 3.4 VNQ5E160MK-E Current sense and diagnostic The current sense pin performs a double function (see Figure 30: Current sense and diagnostic): • Current mirror of the load current in normal operation, delivering a current proportional to the load one according to a known ratio KX. The current ISENSE can be easily converted to a voltage VSENSE by means of an external resistor RSENSE. Linearity between IOUT and VSENSE is ensured up to 5V minimum (see parameter VSENSE in Table 9: Current sense (8 V < VCC < 18 V)). The current sense accuracy depends on the output current (refer to current sense electrical characteristics Table 9: Current sense (8 V < VCC < 18 V)). • Diagnostic flag in fault conditions, delivering a fixed voltage VSENSEH up to a maximum current ISENSEH in case of the following fault conditions (refer to ): – Power limitation activation – Over-temperature A logic level high on CS_DIS pin sets at the same time all the current sense pins of the device in a high impedance state, thus disabling the current monitoring and diagnostic detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and ADC line among different devices. Figure 30. Current sense and diagnostic 9%$7 9&& 0DLQ026Q 9 2YHUWHPSHUDWXUH ,287.; ,6(16(+ 3ZUB/LP 287Q 96(16(+ &6B',6 &855(17 6(16(Q *1' /RDG 53527 7RX&$'& 56(16( 96( 6(16( ("1($'5 24/34 DocID018850 Rev 2 VNQ5E160MK-E Maximum demagnetization energy (VCC = 13.5 V) Figure 31. Maximum turn-off current versus inductance (for each channel) $ & % ,$ 3.5 Application information /P+ ("1($'5 A: Tjstart = 150 °C single pulse B: Tjstart = 100 °C repetitive pulse C: Tjstart = 125 °C repetitive pulse 9,1,/ 'HPDJQHWL]DWLRQ 'HPDJQHWL]DWLRQ 'HPDJQHWL]DWLRQ W *$3*&)7 1. Values are generated with RL = 0 Ω. In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. DocID018850 Rev 2 25/34 33 Package and PC board thermal data VNQ5E160MK-E 4 Package and PC board thermal data 4.1 PowerSSO-24 thermal data Figure 32. PowerSSO-24 PC board ("1($'5 1. Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area = 77 mm x 86 mm, PCB thickness = 1.6 mm, Cu thickness = 70 mm (front and back side), Copper areas: from minimum pad lay-out to 8 cm2). Figure 33. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) 57+MBDPE&: 3&%&XKHDWVLQNDUHDFPA *$3*&)7 26/34 DocID018850 Rev 2 VNQ5E160MK-E Package and PC board thermal data Figure 34. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON) =7+&: &OO TPRINT FP FP 7LPHV ("1($'5 Figure 35. Thermal fitting model of a double channel HSD in PowerSSO-24 1. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. DocID018850 Rev 2 27/34 33 Package and PC board thermal data VNQ5E160MK-E Equation 1: pulse calculation formula: Z THδ = R TH ⋅δ+Z THtp (1 – δ) where δ = tP/T Table 14. Thermal parameters Area/island (cm2) R1 = R7 = R9 = R11 (°C/W) 28/34 Footprint 2 8 1.2 R2 = R8 = R10 = R12 (°C/W) 6 R3 (°C/W) 6 R4 (°C/W) 7.7 R5 (°C/W) 9 9 8 R6 (°C/W) 28 17 10 C1 = C7 = C9 = C11 (W.s/°C) 0.0008 C2 = C8 = C10 = C12 (W.s/°C) 0.0016 C3 (W.s/°C) 0.025 C4 (W.s/°C) 0.75 C5 (W.s/°C) 1 4 9 C6 (W.s/°C) 2.2 5 17 DocID018850 Rev 2 VNQ5E160MK-E Package and packing information 5 Package and packing information 5.1 ECOPACK® packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.2 PowerSSO-24 mechanical data Figure 36. PowerSSO-24 package dimensions ("1($'5 DocID018850 Rev 2 29/34 33 Package and packing information VNQ5E160MK-E Table 15. PowerSSO-24 mechanical data(1)(2) Millimeters Symbol Min. Typ. A Max. 2.50 A2 2.15 2.40 a1 0 0.10 b 0.33 0.51 c 0.23 0.32 D(3) 10.10 10.50 E(3) 7.40 7.60 e 0.8 e3 8.8 F 2.3 G 0.1 G1 0.06 H 10.1 10.5 h 0.4 k L 5º 0.6 1 O 1.2 Q 0.8 S 2.9 T 3.65 U 1 N 10º X 4.1 4.7 Y 6.5 4.9(4) 7.1 5.5(4) 1. No intrusion allowed inwards the leads. 2. Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side 3. “D and E” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15 mm. 4. Variations for small window leadframe option. 30/34 DocID018850 Rev 2 VNQ5E160MK-E 5.3 Package and packing information Packing information Figure 37. PowerSSO-24 tube shipment (no suffix) Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) & % 49 1225 532 3.5 13.8 0.6 All dimensions are in mm. ! Figure 38. PowerSSO-24 tape and reel shipment (suffix “TR”) 5HHOGLPHQVLRQV %DVH4W\ %XON4W\ $PD[ %PLQ & ) * 1PLQ 7PD[ 7DSHGLPHQVLRQV $FFRUGLQJWR(OHFWURQLF,QGXVWULHV$VVRFLDWLRQ (,$6WDQGDUGUHY$)HE 7DSHZLGWK 7DSH+ROH6SDFLQJ &RPSRQHQW6SDFLQJ +ROH'LDPHWHU +ROH'LDPHWHU +ROH3RVLWLRQ &RPSDUWPHQW'HSWK +ROH6SDFLQJ : 3 3 ' 'PLQ ) .PD[ 3 $OOGLPHQVLRQVDUHLQPP (QG 6WDUW 7R S FRYHU WDSH 1RFRPSRQHQWV &RPSRQHQWV PPPLQ 1RFRPSRQHQWV PPPLQ (PSW\FRPSRQHQWVSRFNHWV VDOHGZLWKFRYHUWDSH 8VHUGLUHFWLRQRIIHHG ("1($'5 DocID018850 Rev 2 31/34 33 Order codes 6 VNQ5E160MK-E Order codes Table 16. Device summary Order codes Package PowerSSO-24 32/34 Tube Tape and reel VNQ5E160MK-E VNQ5E160MKTR-E DocID018850 Rev 2 VNQ5E160MK-E 7 Revision history Revision history Table 17. Document revision history Date Revision Changes 25-May-2011 1 Initial release. 04-Nov-2013 2 Updated disclaimer. DocID018850 Rev 2 33/34 33 VNQ5E160MK-E Please Read Carefully: Information in this document is provided solely in connection with ST products. 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