HD151TS302ARP Spread Spectrum Clock for EMI Solution REJ03D0019-0500Z (Previous ADE-205-690D(Z)) Rev.5.00 May.19.2003 Description The HD151TS302A is a high-performance Spread Spectrum Clock modulator. It is suitable for low EMI solution. Features • • • • Supports 10 MHz to 60 MHz operation. (Designed for XIN = 24 MHz and 48 MHz) 1 copy of clock out with spread spectrum modulation @3.3 V 1 copy of reference clock @3.3 V Programmable spread spectrum modulation (–0.5%, –1.0%, –3.0% down spread modulation and spread spectrum disable mode.) • SOP–8pin • Pin to pin compatible with HD151TS302RP Key Specifications • • • • • • Supply voltages : VDD = 3.3 V±0.165 V Ta = 0 to 70°C operating range Clock output duty cycle = 50±5% Cycle to cycle jitter = ±250 ps typ. Output slew rate = 0.8V/ns min. Ordering Information Part Name Package Type HD151TS302ARPEL SOP-8 pin (JEDEC) Package Code Package Abbreviation Taping Abbreviation (Quantity) FP-8DC RP EL (2,500 pcs / Reel) Note: Please consult the sales office for the above package availability. Rev.5.00, May.19.2003, page 1 of 12 HD151TS302ARP Block Diagram VDD GND CLKOUT XIN OSC 1/m SSCCLKOUT Synthesizer XOUT R=1 MΩ 1/n SSC Modulator SEL0 R=100 kΩ Mode Control SEL1 R=100 kΩ Pin Arrangement SSCCLKOUT 1 8 SEL1 VDD 2 7 CLKOUT GND 3 6 SEL0 XIN 4 5 XOUT (Top view) Rev.5.00, May.19.2003, page 2 of 12 HD151TS302ARP SSC Function Table SEL1 :0 Spread Percentage 00 –1.0% 01 –3.0% 10 SSC OFF 11 –0.5% Note: –3.0% SSC is selected for default by internal pull-up & down resistors. Clock Frequency Table XIN(MHz) SSCCLKOUT(MHz) CLKOUT(MHz) 48 *1 48 48*2 24 24*1 24*2 Notes: 1. With spread spectrum modulation. 2. Without spread spectrum modulation. Pin Descriptions Pin name No. Type Description GND 3 Ground GND pin VDD 2 Power Power supplies pin. Normally 3.3 V. CLKOUT 7 Output Normally 3.3 V reference clock output. SSCCLKOUT 1 Output Spread spectrum modulated clock output. XIN 4 Input Oscillator input. XOUT 5 Output Oscillator output. SEL0 6 Input SSC mode select pin. LVCMOS level input. Pull-up by internal resistor. (100 kΩ). SEL1 8 Input SSC mode select pin. LVCMOS level input. Pull–down by internal resistor (100 kΩ). Rev.5.00, May.19.2003, page 3 of 12 HD151TS302ARP Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VDD –0.5 to 4.6 V VI –0.5 to 4.6 V VO –0.5 to VDD+0.5 V Input clamp current IIK –50 mA VI < 0 Output clamp current IOK –50 mA VO < 0 Continuous output current IO VO = 0 to VDD Input voltage Output voltage *1 Maximum power dissipation at Ta = 55°C (in still air) Storage temperature Notes: Tstg ±50 mA 0.7 W –65 to +150 °C Conditions Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Recommended Operating Conditions Item Symbol Min Typ Max Unit Conditions Supply voltage VDD 3.135 3.3 3.465 V –0.3 — VDD+0.3 V DC input signal voltage High level input voltage VIH 2.0 — VDD+0.3 V Low level input voltage VIL –0.3 — 0.8 V Operating temperature Ta 0 — 70 °C 45 50 55 % Input clock duty cycle Rev.5.00, May.19.2003, page 4 of 12 HD151TS302ARP DC Electrical Characteristics Ta = 0 to 70°C, VDD = 3.3 V±5% Item Symbol Min Typ Max Unit Input low voltage VIL — — 0.8 V Input high voltage VIH 2.0 — — V Input current II — — ±10 µA — — ±100 — — 4 pF SEL0, SEL1 — 7 — mA XIN = 24 MHz, CL = 0 pF, VDD = 3.3 V Input capacitance CI Operating current Test Conditions VI = 0 V or 3.465 V, VDD = 3.465 V, XIN pin VI = 0 V or 3.465 V, VDD = 3.465 V, SEL0, SEL1 pins DC Electrical Characteristics / Clock Output & SSC Clock Output Ta = 0 to 70°C, VDD = 3.3 V±5% Item Symbol Min Typ Max Unit Test Conditions Output voltage VOH 3.1 — — V IOH = –1 mA, VDD = 3.3 V VOL — — 50 mV IOL = 1 mA, VDD = 3.3 V IOH — –30 — mA VOH = 1.5 V IOL — 30 — 1 Output current* Note: 1. Parameters are target of design. Not 100% tested in production. Rev.5.00, May.19.2003, page 5 of 12 VOL = 1.5 V HD151TS302ARP AC Electrical Characteristics / Clock Output & SSC Clock Output Ta = 25°C, VDD = 3.3 V, CL = 15 pF Item Cycle to cycle jitter Output frequency Slew rate *1, 2 Min Typ Max Unit Test Conditions Notes tCCS — | 250 | | 300 | ps SSCCLKOUT, 24 MHz — | 250 | | 300 | SSCCLKOUT, 48 MHz SSCOFF SEL1:0 = 10 Fig1 — | 250 | | 300 | SSCCLKOUT, 24 MHz — | 250 | | 300 | SSCCLKOUT, 48 MHz — | 250 | | 300 | SSCCLKOUT, 24 MHz — | 250 | | 300 | SSCCLKOUT, 48 MHz — | 250 | | 300 | CLKOUT, 24 MHz & 48 MHz Fig1 23.8 — 24.2 SSCCLKOUT, XIN = 24 MHz SSCOFF SEL1:0 = 10 47.3 — 48.7 SSCCLKOUT, XIN = 48 MHz 23.7 — 24.2 SSCCLKOUT, XIN = 24 MHz 47.0 — 48.7 SSCCLKOUT, XIN = 48 MHz 23.1 — 24.2 SSCCLKOUT, XIN = 24 MHz 45.9 — 48.7 SSCCLKOUT, XIN = 48 MHz 23.8 — 24.2 CLKOUT, 24 MHz 47.3 — 48.7 CLKOUT, 48 MHz 0.8 — — V/ns 45 50 55 % *1, 2 *1 Clock duty cycle Symbol tSL *1 MHz — 40 — Ω Spread spectrum *1 modulation frequency — 33 — KHz Input clock frequency 10 — 60 MHz — — 2 ms Output impedance Stabilization time Notes: *1 *1,3 @48 MHz CLKOUT SSC = –0.5% SEL1:0 = 11 Fig1 SSC = –3.0% SEL1:0 = 01 Fig1 SSC = –0.5% SEL1:0 = 11 SSC = –3.0% SEL1:0 = 01 0.4 V to 2.4 V @48 MHz SSCCLKOUT 1. Parameters are target of design. Not 100% tested in production. 2. Cycle to cycle jitter and output frequency are included spread spectrum modulation. 3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after power up. Rev.5.00, May.19.2003, page 6 of 12 HD151TS302ARP SSCCLKOUT (or CLKOUT) tcycle n tcycle n+1 t CCS = (tcycle n) - (tcycle n+1) Figure 1 Cycle to cycle jitter Rev.5.00, May.19.2003, page 7 of 12 HD151TS302ARP Application Information 1. Recommended Circuit Configuration The power supply circuit of the optimal performance on the application of a system should refer to Fig. 2. VDD decoupling is important to both reduce Jitter and EMI radiation. The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability. The C2 decoupling capacitor shown should be a tantalum type. R1 SSCCLKOUT 1 8 VDD 2 7 SEL1 R2 C2 CLKOUT C1 3 6 SEL0 TS300 Series GND GND 4 5 GND Notes: XIN XOUT (Crystal or Reference input) (Crystal or Not connection) C1 = High frequency supply decoupling capacitor. (0.1 µF recommended) C2 = Low frequency supply decoupling capacitor. (22 µF tantalum type recommended) R1, R2 = Match value to line impedance. (22 Ω Reference value) Figure 2 Recommended circuit configuration Rev.5.00, May.19.2003, page 8 of 12 HD151TS302ARP 2. Example Board Layout Configuration VDD (+3.3 V Supply) P 22 µF FB G R1 1 SSCCLKOUT 8 0.1 µF R2 7 G G 3 6 4 5 Crystal connection or Reference input Note: Crystal connection or Not connection G Via to GND plane R1, R2 = Match value to line impedance. (22 Ω Reference value) FB = Ferrite bead. Figure 3 Example Board Layout Rev.5.00, May.19.2003, page 9 of 12 CLKOUT HD151TS302ARP 3. Example of TS300 EMI Solution IC’s Application Spread Spectrum Modulated Clock XTAL XOUT TS30X CPU & ASIC SSC CLKOUT Memory System BUS XIN Graphics System Cont. Ref. Clock 3.3 V CMOS level ref. Clock Fig 4 Ref. Clock Input Example XIN XTAL XOUT TS30X CPU & ASIC SSC CLKOUT System BUS Spread Spectrum Modulated Clock Memory Graphics System Cont. Fig 5 XTAL Ref. Clock Input Example Rev.5.00, May.19.2003, page 10 of 12 HD151TS302ARP Package Dimensions As of January, 2003 Unit: mm 3.95 4.90 5.3 Max 5 8 *0.22 ± 0.03 0.20 ± 0.03 4 1.75 Max 1 0.75 Max + 0.10 6.10 – 0.30 1.08 0.14 – 0.04 *0.42 ± 0.08 0.40 ± 0.06 + 0.11 0˚ – 8˚ 1.27 + 0.67 0.60 – 0.20 0.15 0.25 M *Dimension including the plating thickness Base material dimension Rev.5.00, May.19.2003, page 11 of 12 Package Code JEDEC JEITA Mass (reference value) FP-8DC Conforms — 0.085 g HD151TS302ARP Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. 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Renesas Technology Corporation, All rights reserved. Printed in Japan. Colophon 0.0 Rev.5.00, May.19.2003, page 12 of 12